patch_ca0132.c 26 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018
  1. /*
  2. * HD audio interface patch for Creative CA0132 chip
  3. *
  4. * Copyright (c) 2011, Creative Technology Ltd.
  5. *
  6. * Based on patch_ca0110.c
  7. * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
  8. *
  9. * This driver is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This driver is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <linux/pci.h>
  27. #include <linux/mutex.h>
  28. #include <linux/module.h>
  29. #include <sound/core.h>
  30. #include "hda_codec.h"
  31. #include "hda_local.h"
  32. #include "hda_auto_parser.h"
  33. #define WIDGET_CHIP_CTRL 0x15
  34. #define WIDGET_DSP_CTRL 0x16
  35. #define WUH_MEM_CONNID 10
  36. #define DSP_MEM_CONNID 16
  37. enum hda_cmd_vendor_io {
  38. /* for DspIO node */
  39. VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
  40. VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
  41. VENDOR_DSPIO_STATUS = 0xF01,
  42. VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
  43. VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
  44. VENDOR_DSPIO_DSP_INIT = 0x703,
  45. VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
  46. VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
  47. /* for ChipIO node */
  48. VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
  49. VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
  50. VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
  51. VENDOR_CHIPIO_DATA_LOW = 0x300,
  52. VENDOR_CHIPIO_DATA_HIGH = 0x400,
  53. VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
  54. VENDOR_CHIPIO_STATUS = 0xF01,
  55. VENDOR_CHIPIO_HIC_POST_READ = 0x702,
  56. VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
  57. VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
  58. VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
  59. VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
  60. VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
  61. VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
  62. VENDOR_CHIPIO_FLAG_SET = 0x70F,
  63. VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
  64. VENDOR_CHIPIO_PARAMETER_SET = 0x710,
  65. VENDOR_CHIPIO_PARAMETER_GET = 0xF10,
  66. VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
  67. VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
  68. VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
  69. VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
  70. VENDOR_CHIPIO_PARAMETER_EX_ID_GET = 0xF17,
  71. VENDOR_CHIPIO_PARAMETER_EX_ID_SET = 0x717,
  72. VENDOR_CHIPIO_PARAMETER_EX_VALUE_GET = 0xF18,
  73. VENDOR_CHIPIO_PARAMETER_EX_VALUE_SET = 0x718
  74. };
  75. /*
  76. * Control flag IDs
  77. */
  78. enum control_flag_id {
  79. /* Connection manager stream setup is bypassed/enabled */
  80. CONTROL_FLAG_C_MGR = 0,
  81. /* DSP DMA is bypassed/enabled */
  82. CONTROL_FLAG_DMA = 1,
  83. /* 8051 'idle' mode is disabled/enabled */
  84. CONTROL_FLAG_IDLE_ENABLE = 2,
  85. /* Tracker for the SPDIF-in path is bypassed/enabled */
  86. CONTROL_FLAG_TRACKER = 3,
  87. /* DigitalOut to Spdif2Out connection is disabled/enabled */
  88. CONTROL_FLAG_SPDIF2OUT = 4,
  89. /* Digital Microphone is disabled/enabled */
  90. CONTROL_FLAG_DMIC = 5,
  91. /* ADC_B rate is 48 kHz/96 kHz */
  92. CONTROL_FLAG_ADC_B_96KHZ = 6,
  93. /* ADC_C rate is 48 kHz/96 kHz */
  94. CONTROL_FLAG_ADC_C_96KHZ = 7,
  95. /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
  96. CONTROL_FLAG_DAC_96KHZ = 8,
  97. /* DSP rate is 48 kHz/96 kHz */
  98. CONTROL_FLAG_DSP_96KHZ = 9,
  99. /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
  100. CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
  101. /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
  102. CONTROL_FLAG_SRC_RATE_96KHZ = 11,
  103. /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
  104. CONTROL_FLAG_DECODE_LOOP = 12,
  105. /* De-emphasis filter on DAC-1 disabled/enabled */
  106. CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
  107. /* De-emphasis filter on DAC-2 disabled/enabled */
  108. CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
  109. /* De-emphasis filter on DAC-3 disabled/enabled */
  110. CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
  111. /* High-pass filter on ADC_B disabled/enabled */
  112. CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
  113. /* High-pass filter on ADC_C disabled/enabled */
  114. CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
  115. /* Common mode on Port_A disabled/enabled */
  116. CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
  117. /* Common mode on Port_D disabled/enabled */
  118. CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
  119. /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
  120. CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
  121. /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
  122. CONTROL_FLAG_PORT_D_10K0HM_LOAD = 21,
  123. /* ASI rate is 48kHz/96kHz */
  124. CONTROL_FLAG_ASI_96KHZ = 22,
  125. /* DAC power settings able to control attached ports no/yes */
  126. CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
  127. /* Clock Stop OK reporting is disabled/enabled */
  128. CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
  129. /* Number of control flags */
  130. CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
  131. };
  132. /*
  133. * Control parameter IDs
  134. */
  135. enum control_parameter_id {
  136. /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
  137. CONTROL_PARAM_SPDIF1_SOURCE = 2,
  138. /* Stream Control */
  139. /* Select stream with the given ID */
  140. CONTROL_PARAM_STREAM_ID = 24,
  141. /* Source connection point for the selected stream */
  142. CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
  143. /* Destination connection point for the selected stream */
  144. CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
  145. /* Number of audio channels in the selected stream */
  146. CONTROL_PARAM_STREAMS_CHANNELS = 27,
  147. /*Enable control for the selected stream */
  148. CONTROL_PARAM_STREAM_CONTROL = 28,
  149. /* Connection Point Control */
  150. /* Select connection point with the given ID */
  151. CONTROL_PARAM_CONN_POINT_ID = 29,
  152. /* Connection point sample rate */
  153. CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
  154. /* Node Control */
  155. /* Select HDA node with the given ID */
  156. CONTROL_PARAM_NODE_ID = 31
  157. };
  158. /*
  159. * Dsp Io Status codes
  160. */
  161. enum hda_vendor_status_dspio {
  162. /* Success */
  163. VENDOR_STATUS_DSPIO_OK = 0x00,
  164. /* Busy, unable to accept new command, the host must retry */
  165. VENDOR_STATUS_DSPIO_BUSY = 0x01,
  166. /* SCP command queue is full */
  167. VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
  168. /* SCP response queue is empty */
  169. VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
  170. };
  171. /*
  172. * Chip Io Status codes
  173. */
  174. enum hda_vendor_status_chipio {
  175. /* Success */
  176. VENDOR_STATUS_CHIPIO_OK = 0x00,
  177. /* Busy, unable to accept new command, the host must retry */
  178. VENDOR_STATUS_CHIPIO_BUSY = 0x01
  179. };
  180. /*
  181. * CA0132 sample rate
  182. */
  183. enum ca0132_sample_rate {
  184. SR_6_000 = 0x00,
  185. SR_8_000 = 0x01,
  186. SR_9_600 = 0x02,
  187. SR_11_025 = 0x03,
  188. SR_16_000 = 0x04,
  189. SR_22_050 = 0x05,
  190. SR_24_000 = 0x06,
  191. SR_32_000 = 0x07,
  192. SR_44_100 = 0x08,
  193. SR_48_000 = 0x09,
  194. SR_88_200 = 0x0A,
  195. SR_96_000 = 0x0B,
  196. SR_144_000 = 0x0C,
  197. SR_176_400 = 0x0D,
  198. SR_192_000 = 0x0E,
  199. SR_384_000 = 0x0F,
  200. SR_COUNT = 0x10,
  201. SR_RATE_UNKNOWN = 0x1F
  202. };
  203. /*
  204. * Scp Helper function
  205. */
  206. enum get_set {
  207. IS_SET = 0,
  208. IS_GET = 1,
  209. };
  210. /*
  211. * Duplicated from ca0110 codec
  212. */
  213. static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
  214. {
  215. if (pin) {
  216. snd_hda_set_pin_ctl(codec, pin, PIN_HP);
  217. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  218. snd_hda_codec_write(codec, pin, 0,
  219. AC_VERB_SET_AMP_GAIN_MUTE,
  220. AMP_OUT_UNMUTE);
  221. }
  222. if (dac)
  223. snd_hda_codec_write(codec, dac, 0,
  224. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
  225. }
  226. static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
  227. {
  228. if (pin) {
  229. snd_hda_set_pin_ctl(codec, pin, PIN_IN |
  230. snd_hda_get_default_vref(codec, pin));
  231. if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
  232. snd_hda_codec_write(codec, pin, 0,
  233. AC_VERB_SET_AMP_GAIN_MUTE,
  234. AMP_IN_UNMUTE(0));
  235. }
  236. if (adc)
  237. snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  238. AMP_IN_UNMUTE(0));
  239. }
  240. static char *dirstr[2] = { "Playback", "Capture" };
  241. static int _add_switch(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
  242. int chan, int dir)
  243. {
  244. char namestr[44];
  245. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  246. struct snd_kcontrol_new knew =
  247. HDA_CODEC_MUTE_MONO(namestr, nid, chan, 0, type);
  248. sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
  249. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  250. }
  251. static int _add_volume(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
  252. int chan, int dir)
  253. {
  254. char namestr[44];
  255. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  256. struct snd_kcontrol_new knew =
  257. HDA_CODEC_VOLUME_MONO(namestr, nid, chan, 0, type);
  258. sprintf(namestr, "%s %s Volume", pfx, dirstr[dir]);
  259. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  260. }
  261. #define add_out_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 0)
  262. #define add_out_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 0)
  263. #define add_in_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 1)
  264. #define add_in_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 1)
  265. #define add_mono_switch(codec, nid, pfx, chan) \
  266. _add_switch(codec, nid, pfx, chan, 0)
  267. #define add_mono_volume(codec, nid, pfx, chan) \
  268. _add_volume(codec, nid, pfx, chan, 0)
  269. #define add_in_mono_switch(codec, nid, pfx, chan) \
  270. _add_switch(codec, nid, pfx, chan, 1)
  271. #define add_in_mono_volume(codec, nid, pfx, chan) \
  272. _add_volume(codec, nid, pfx, chan, 1)
  273. /*
  274. * CA0132 specific
  275. */
  276. struct ca0132_spec {
  277. struct auto_pin_cfg autocfg;
  278. struct hda_multi_out multiout;
  279. hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
  280. hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
  281. hda_nid_t hp_dac;
  282. hda_nid_t input_pins[AUTO_PIN_LAST];
  283. hda_nid_t adcs[AUTO_PIN_LAST];
  284. hda_nid_t dig_out;
  285. hda_nid_t dig_in;
  286. unsigned int num_inputs;
  287. long curr_hp_switch;
  288. long curr_hp_volume[2];
  289. long curr_speaker_switch;
  290. struct mutex chipio_mutex;
  291. const char *input_labels[AUTO_PIN_LAST];
  292. struct hda_pcm pcm_rec[2]; /* PCM information */
  293. };
  294. /* Chip access helper function */
  295. static int chipio_send(struct hda_codec *codec,
  296. unsigned int reg,
  297. unsigned int data)
  298. {
  299. unsigned int res;
  300. int retry = 50;
  301. /* send bits of data specified by reg */
  302. do {
  303. res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  304. reg, data);
  305. if (res == VENDOR_STATUS_CHIPIO_OK)
  306. return 0;
  307. } while (--retry);
  308. return -EIO;
  309. }
  310. /*
  311. * Write chip address through the vendor widget -- NOT protected by the Mutex!
  312. */
  313. static int chipio_write_address(struct hda_codec *codec,
  314. unsigned int chip_addx)
  315. {
  316. int res;
  317. /* send low 16 bits of the address */
  318. res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
  319. chip_addx & 0xffff);
  320. if (res != -EIO) {
  321. /* send high 16 bits of the address */
  322. res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
  323. chip_addx >> 16);
  324. }
  325. return res;
  326. }
  327. /*
  328. * Write data through the vendor widget -- NOT protected by the Mutex!
  329. */
  330. static int chipio_write_data(struct hda_codec *codec, unsigned int data)
  331. {
  332. int res;
  333. /* send low 16 bits of the data */
  334. res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
  335. if (res != -EIO) {
  336. /* send high 16 bits of the data */
  337. res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
  338. data >> 16);
  339. }
  340. return res;
  341. }
  342. /*
  343. * Read data through the vendor widget -- NOT protected by the Mutex!
  344. */
  345. static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
  346. {
  347. int res;
  348. /* post read */
  349. res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
  350. if (res != -EIO) {
  351. /* read status */
  352. res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
  353. }
  354. if (res != -EIO) {
  355. /* read data */
  356. *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  357. VENDOR_CHIPIO_HIC_READ_DATA,
  358. 0);
  359. }
  360. return res;
  361. }
  362. /*
  363. * Write given value to the given address through the chip I/O widget.
  364. * protected by the Mutex
  365. */
  366. static int chipio_write(struct hda_codec *codec,
  367. unsigned int chip_addx, const unsigned int data)
  368. {
  369. struct ca0132_spec *spec = codec->spec;
  370. int err;
  371. mutex_lock(&spec->chipio_mutex);
  372. /* write the address, and if successful proceed to write data */
  373. err = chipio_write_address(codec, chip_addx);
  374. if (err < 0)
  375. goto exit;
  376. err = chipio_write_data(codec, data);
  377. if (err < 0)
  378. goto exit;
  379. exit:
  380. mutex_unlock(&spec->chipio_mutex);
  381. return err;
  382. }
  383. /*
  384. * Read the given address through the chip I/O widget
  385. * protected by the Mutex
  386. */
  387. static int chipio_read(struct hda_codec *codec,
  388. unsigned int chip_addx, unsigned int *data)
  389. {
  390. struct ca0132_spec *spec = codec->spec;
  391. int err;
  392. mutex_lock(&spec->chipio_mutex);
  393. /* write the address, and if successful proceed to write data */
  394. err = chipio_write_address(codec, chip_addx);
  395. if (err < 0)
  396. goto exit;
  397. err = chipio_read_data(codec, data);
  398. if (err < 0)
  399. goto exit;
  400. exit:
  401. mutex_unlock(&spec->chipio_mutex);
  402. return err;
  403. }
  404. /*
  405. * PCM callbacks
  406. */
  407. static int ca0132_playback_pcm_open(struct hda_pcm_stream *hinfo,
  408. struct hda_codec *codec,
  409. struct snd_pcm_substream *substream)
  410. {
  411. struct ca0132_spec *spec = codec->spec;
  412. return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream,
  413. hinfo);
  414. }
  415. static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  416. struct hda_codec *codec,
  417. unsigned int stream_tag,
  418. unsigned int format,
  419. struct snd_pcm_substream *substream)
  420. {
  421. struct ca0132_spec *spec = codec->spec;
  422. return snd_hda_multi_out_analog_prepare(codec, &spec->multiout,
  423. stream_tag, format, substream);
  424. }
  425. static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  426. struct hda_codec *codec,
  427. struct snd_pcm_substream *substream)
  428. {
  429. struct ca0132_spec *spec = codec->spec;
  430. return snd_hda_multi_out_analog_cleanup(codec, &spec->multiout);
  431. }
  432. /*
  433. * Digital out
  434. */
  435. static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
  436. struct hda_codec *codec,
  437. struct snd_pcm_substream *substream)
  438. {
  439. struct ca0132_spec *spec = codec->spec;
  440. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  441. }
  442. static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  443. struct hda_codec *codec,
  444. unsigned int stream_tag,
  445. unsigned int format,
  446. struct snd_pcm_substream *substream)
  447. {
  448. struct ca0132_spec *spec = codec->spec;
  449. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  450. stream_tag, format, substream);
  451. }
  452. static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  453. struct hda_codec *codec,
  454. struct snd_pcm_substream *substream)
  455. {
  456. struct ca0132_spec *spec = codec->spec;
  457. return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
  458. }
  459. static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
  460. struct hda_codec *codec,
  461. struct snd_pcm_substream *substream)
  462. {
  463. struct ca0132_spec *spec = codec->spec;
  464. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  465. }
  466. /*
  467. */
  468. static struct hda_pcm_stream ca0132_pcm_analog_playback = {
  469. .substreams = 1,
  470. .channels_min = 2,
  471. .channels_max = 2,
  472. .ops = {
  473. .open = ca0132_playback_pcm_open,
  474. .prepare = ca0132_playback_pcm_prepare,
  475. .cleanup = ca0132_playback_pcm_cleanup
  476. },
  477. };
  478. static struct hda_pcm_stream ca0132_pcm_analog_capture = {
  479. .substreams = 1,
  480. .channels_min = 2,
  481. .channels_max = 2,
  482. };
  483. static struct hda_pcm_stream ca0132_pcm_digital_playback = {
  484. .substreams = 1,
  485. .channels_min = 2,
  486. .channels_max = 2,
  487. .ops = {
  488. .open = ca0132_dig_playback_pcm_open,
  489. .close = ca0132_dig_playback_pcm_close,
  490. .prepare = ca0132_dig_playback_pcm_prepare,
  491. .cleanup = ca0132_dig_playback_pcm_cleanup
  492. },
  493. };
  494. static struct hda_pcm_stream ca0132_pcm_digital_capture = {
  495. .substreams = 1,
  496. .channels_min = 2,
  497. .channels_max = 2,
  498. };
  499. static int ca0132_build_pcms(struct hda_codec *codec)
  500. {
  501. struct ca0132_spec *spec = codec->spec;
  502. struct hda_pcm *info = spec->pcm_rec;
  503. codec->pcm_info = info;
  504. codec->num_pcms = 0;
  505. info->name = "CA0132 Analog";
  506. info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
  507. info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
  508. info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
  509. spec->multiout.max_channels;
  510. info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
  511. info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_inputs;
  512. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
  513. codec->num_pcms++;
  514. if (!spec->dig_out && !spec->dig_in)
  515. return 0;
  516. info++;
  517. info->name = "CA0132 Digital";
  518. info->pcm_type = HDA_PCM_TYPE_SPDIF;
  519. if (spec->dig_out) {
  520. info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
  521. ca0132_pcm_digital_playback;
  522. info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
  523. }
  524. if (spec->dig_in) {
  525. info->stream[SNDRV_PCM_STREAM_CAPTURE] =
  526. ca0132_pcm_digital_capture;
  527. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
  528. }
  529. codec->num_pcms++;
  530. return 0;
  531. }
  532. #define REG_CODEC_MUTE 0x18b014
  533. #define REG_CODEC_HP_VOL_L 0x18b070
  534. #define REG_CODEC_HP_VOL_R 0x18b074
  535. static int ca0132_hp_switch_get(struct snd_kcontrol *kcontrol,
  536. struct snd_ctl_elem_value *ucontrol)
  537. {
  538. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  539. struct ca0132_spec *spec = codec->spec;
  540. long *valp = ucontrol->value.integer.value;
  541. *valp = spec->curr_hp_switch;
  542. return 0;
  543. }
  544. static int ca0132_hp_switch_put(struct snd_kcontrol *kcontrol,
  545. struct snd_ctl_elem_value *ucontrol)
  546. {
  547. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  548. struct ca0132_spec *spec = codec->spec;
  549. long *valp = ucontrol->value.integer.value;
  550. unsigned int data;
  551. int err;
  552. /* any change? */
  553. if (spec->curr_hp_switch == *valp)
  554. return 0;
  555. snd_hda_power_up(codec);
  556. err = chipio_read(codec, REG_CODEC_MUTE, &data);
  557. if (err < 0)
  558. goto exit;
  559. /* *valp 0 is mute, 1 is unmute */
  560. data = (data & 0x7f) | (*valp ? 0 : 0x80);
  561. err = chipio_write(codec, REG_CODEC_MUTE, data);
  562. if (err < 0)
  563. goto exit;
  564. spec->curr_hp_switch = *valp;
  565. exit:
  566. snd_hda_power_down(codec);
  567. return err < 0 ? err : 1;
  568. }
  569. static int ca0132_speaker_switch_get(struct snd_kcontrol *kcontrol,
  570. struct snd_ctl_elem_value *ucontrol)
  571. {
  572. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  573. struct ca0132_spec *spec = codec->spec;
  574. long *valp = ucontrol->value.integer.value;
  575. *valp = spec->curr_speaker_switch;
  576. return 0;
  577. }
  578. static int ca0132_speaker_switch_put(struct snd_kcontrol *kcontrol,
  579. struct snd_ctl_elem_value *ucontrol)
  580. {
  581. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  582. struct ca0132_spec *spec = codec->spec;
  583. long *valp = ucontrol->value.integer.value;
  584. unsigned int data;
  585. int err;
  586. /* any change? */
  587. if (spec->curr_speaker_switch == *valp)
  588. return 0;
  589. snd_hda_power_up(codec);
  590. err = chipio_read(codec, REG_CODEC_MUTE, &data);
  591. if (err < 0)
  592. goto exit;
  593. /* *valp 0 is mute, 1 is unmute */
  594. data = (data & 0xef) | (*valp ? 0 : 0x10);
  595. err = chipio_write(codec, REG_CODEC_MUTE, data);
  596. if (err < 0)
  597. goto exit;
  598. spec->curr_speaker_switch = *valp;
  599. exit:
  600. snd_hda_power_down(codec);
  601. return err < 0 ? err : 1;
  602. }
  603. static int ca0132_hp_volume_get(struct snd_kcontrol *kcontrol,
  604. struct snd_ctl_elem_value *ucontrol)
  605. {
  606. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  607. struct ca0132_spec *spec = codec->spec;
  608. long *valp = ucontrol->value.integer.value;
  609. *valp++ = spec->curr_hp_volume[0];
  610. *valp = spec->curr_hp_volume[1];
  611. return 0;
  612. }
  613. static int ca0132_hp_volume_put(struct snd_kcontrol *kcontrol,
  614. struct snd_ctl_elem_value *ucontrol)
  615. {
  616. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  617. struct ca0132_spec *spec = codec->spec;
  618. long *valp = ucontrol->value.integer.value;
  619. long left_vol, right_vol;
  620. unsigned int data;
  621. int val;
  622. int err;
  623. left_vol = *valp++;
  624. right_vol = *valp;
  625. /* any change? */
  626. if ((spec->curr_hp_volume[0] == left_vol) &&
  627. (spec->curr_hp_volume[1] == right_vol))
  628. return 0;
  629. snd_hda_power_up(codec);
  630. err = chipio_read(codec, REG_CODEC_HP_VOL_L, &data);
  631. if (err < 0)
  632. goto exit;
  633. val = 31 - left_vol;
  634. data = (data & 0xe0) | val;
  635. err = chipio_write(codec, REG_CODEC_HP_VOL_L, data);
  636. if (err < 0)
  637. goto exit;
  638. val = 31 - right_vol;
  639. data = (data & 0xe0) | val;
  640. err = chipio_write(codec, REG_CODEC_HP_VOL_R, data);
  641. if (err < 0)
  642. goto exit;
  643. spec->curr_hp_volume[0] = left_vol;
  644. spec->curr_hp_volume[1] = right_vol;
  645. exit:
  646. snd_hda_power_down(codec);
  647. return err < 0 ? err : 1;
  648. }
  649. static int add_hp_switch(struct hda_codec *codec, hda_nid_t nid)
  650. {
  651. struct snd_kcontrol_new knew =
  652. HDA_CODEC_MUTE_MONO("Headphone Playback Switch",
  653. nid, 1, 0, HDA_OUTPUT);
  654. knew.get = ca0132_hp_switch_get;
  655. knew.put = ca0132_hp_switch_put;
  656. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  657. }
  658. static int add_hp_volume(struct hda_codec *codec, hda_nid_t nid)
  659. {
  660. struct snd_kcontrol_new knew =
  661. HDA_CODEC_VOLUME_MONO("Headphone Playback Volume",
  662. nid, 3, 0, HDA_OUTPUT);
  663. knew.get = ca0132_hp_volume_get;
  664. knew.put = ca0132_hp_volume_put;
  665. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  666. }
  667. static int add_speaker_switch(struct hda_codec *codec, hda_nid_t nid)
  668. {
  669. struct snd_kcontrol_new knew =
  670. HDA_CODEC_MUTE_MONO("Speaker Playback Switch",
  671. nid, 1, 0, HDA_OUTPUT);
  672. knew.get = ca0132_speaker_switch_get;
  673. knew.put = ca0132_speaker_switch_put;
  674. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  675. }
  676. static void ca0132_fix_hp_caps(struct hda_codec *codec)
  677. {
  678. struct ca0132_spec *spec = codec->spec;
  679. struct auto_pin_cfg *cfg = &spec->autocfg;
  680. unsigned int caps;
  681. /* set mute-capable, 1db step, 32 steps, ofs 6 */
  682. caps = 0x80031f06;
  683. snd_hda_override_amp_caps(codec, cfg->hp_pins[0], HDA_OUTPUT, caps);
  684. }
  685. static int ca0132_build_controls(struct hda_codec *codec)
  686. {
  687. struct ca0132_spec *spec = codec->spec;
  688. struct auto_pin_cfg *cfg = &spec->autocfg;
  689. int i, err;
  690. if (spec->multiout.num_dacs) {
  691. err = add_speaker_switch(codec, spec->out_pins[0]);
  692. if (err < 0)
  693. return err;
  694. }
  695. if (cfg->hp_outs) {
  696. ca0132_fix_hp_caps(codec);
  697. err = add_hp_switch(codec, cfg->hp_pins[0]);
  698. if (err < 0)
  699. return err;
  700. err = add_hp_volume(codec, cfg->hp_pins[0]);
  701. if (err < 0)
  702. return err;
  703. }
  704. for (i = 0; i < spec->num_inputs; i++) {
  705. const char *label = spec->input_labels[i];
  706. err = add_in_switch(codec, spec->adcs[i], label);
  707. if (err < 0)
  708. return err;
  709. err = add_in_volume(codec, spec->adcs[i], label);
  710. if (err < 0)
  711. return err;
  712. if (cfg->inputs[i].type == AUTO_PIN_MIC) {
  713. /* add Mic-Boost */
  714. err = add_in_mono_volume(codec, spec->input_pins[i],
  715. "Mic Boost", 1);
  716. if (err < 0)
  717. return err;
  718. }
  719. }
  720. if (spec->dig_out) {
  721. err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
  722. spec->dig_out);
  723. if (err < 0)
  724. return err;
  725. err = add_out_volume(codec, spec->dig_out, "IEC958");
  726. if (err < 0)
  727. return err;
  728. }
  729. if (spec->dig_in) {
  730. err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
  731. if (err < 0)
  732. return err;
  733. err = add_in_volume(codec, spec->dig_in, "IEC958");
  734. if (err < 0)
  735. return err;
  736. }
  737. return 0;
  738. }
  739. static void ca0132_set_ct_ext(struct hda_codec *codec, int enable)
  740. {
  741. /* Set Creative extension */
  742. snd_printdd("SET CREATIVE EXTENSION\n");
  743. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  744. VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE,
  745. enable);
  746. msleep(20);
  747. }
  748. static void ca0132_config(struct hda_codec *codec)
  749. {
  750. struct ca0132_spec *spec = codec->spec;
  751. struct auto_pin_cfg *cfg = &spec->autocfg;
  752. codec->pcm_format_first = 1;
  753. codec->no_sticky_stream = 1;
  754. /* line-outs */
  755. cfg->line_outs = 1;
  756. cfg->line_out_pins[0] = 0x0b; /* front */
  757. cfg->line_out_type = AUTO_PIN_LINE_OUT;
  758. spec->dacs[0] = 0x02;
  759. spec->out_pins[0] = 0x0b;
  760. spec->multiout.dac_nids = spec->dacs;
  761. spec->multiout.num_dacs = 1;
  762. spec->multiout.max_channels = 2;
  763. /* headphone */
  764. cfg->hp_outs = 1;
  765. cfg->hp_pins[0] = 0x0f;
  766. spec->hp_dac = 0;
  767. spec->multiout.hp_nid = 0;
  768. /* inputs */
  769. cfg->num_inputs = 2; /* Mic-in and line-in */
  770. cfg->inputs[0].pin = 0x12;
  771. cfg->inputs[0].type = AUTO_PIN_MIC;
  772. cfg->inputs[1].pin = 0x11;
  773. cfg->inputs[1].type = AUTO_PIN_LINE_IN;
  774. /* Mic-in */
  775. spec->input_pins[0] = 0x12;
  776. spec->input_labels[0] = "Mic";
  777. spec->adcs[0] = 0x07;
  778. /* Line-In */
  779. spec->input_pins[1] = 0x11;
  780. spec->input_labels[1] = "Line";
  781. spec->adcs[1] = 0x08;
  782. spec->num_inputs = 2;
  783. }
  784. static void ca0132_init_chip(struct hda_codec *codec)
  785. {
  786. struct ca0132_spec *spec = codec->spec;
  787. mutex_init(&spec->chipio_mutex);
  788. }
  789. static void ca0132_exit_chip(struct hda_codec *codec)
  790. {
  791. /* put any chip cleanup stuffs here. */
  792. }
  793. static int ca0132_init(struct hda_codec *codec)
  794. {
  795. struct ca0132_spec *spec = codec->spec;
  796. struct auto_pin_cfg *cfg = &spec->autocfg;
  797. int i;
  798. for (i = 0; i < spec->multiout.num_dacs; i++) {
  799. init_output(codec, spec->out_pins[i],
  800. spec->multiout.dac_nids[i]);
  801. }
  802. init_output(codec, cfg->hp_pins[0], spec->hp_dac);
  803. init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
  804. for (i = 0; i < spec->num_inputs; i++)
  805. init_input(codec, spec->input_pins[i], spec->adcs[i]);
  806. init_input(codec, cfg->dig_in_pin, spec->dig_in);
  807. ca0132_set_ct_ext(codec, 1);
  808. return 0;
  809. }
  810. static void ca0132_free(struct hda_codec *codec)
  811. {
  812. ca0132_set_ct_ext(codec, 0);
  813. ca0132_exit_chip(codec);
  814. kfree(codec->spec);
  815. }
  816. static struct hda_codec_ops ca0132_patch_ops = {
  817. .build_controls = ca0132_build_controls,
  818. .build_pcms = ca0132_build_pcms,
  819. .init = ca0132_init,
  820. .free = ca0132_free,
  821. };
  822. static int patch_ca0132(struct hda_codec *codec)
  823. {
  824. struct ca0132_spec *spec;
  825. snd_printdd("patch_ca0132\n");
  826. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  827. if (!spec)
  828. return -ENOMEM;
  829. codec->spec = spec;
  830. ca0132_init_chip(codec);
  831. ca0132_config(codec);
  832. codec->patch_ops = ca0132_patch_ops;
  833. return 0;
  834. }
  835. /*
  836. * patch entries
  837. */
  838. static struct hda_codec_preset snd_hda_preset_ca0132[] = {
  839. { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
  840. {} /* terminator */
  841. };
  842. MODULE_ALIAS("snd-hda-codec-id:11020011");
  843. MODULE_LICENSE("GPL");
  844. MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec");
  845. static struct hda_codec_preset_list ca0132_list = {
  846. .preset = snd_hda_preset_ca0132,
  847. .owner = THIS_MODULE,
  848. };
  849. static int __init patch_ca0132_init(void)
  850. {
  851. return snd_hda_add_codec_preset(&ca0132_list);
  852. }
  853. static void __exit patch_ca0132_exit(void)
  854. {
  855. snd_hda_delete_codec_preset(&ca0132_list);
  856. }
  857. module_init(patch_ca0132_init)
  858. module_exit(patch_ca0132_exit)