main.c 103 KB

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  1. /*
  2. *
  3. * Broadcom B43legacy wireless driver
  4. *
  5. * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
  7. * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
  8. * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  9. * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10. * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11. *
  12. * Some parts of the code in this file are derived from the ipw2200
  13. * driver Copyright(c) 2003 - 2004 Intel Corporation.
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; see the file COPYING. If not, write to
  26. * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27. * Boston, MA 02110-1301, USA.
  28. *
  29. */
  30. #include <linux/delay.h>
  31. #include <linux/init.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/if_arp.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/version.h>
  36. #include <linux/firmware.h>
  37. #include <linux/wireless.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/dma-mapping.h>
  41. #include <net/dst.h>
  42. #include <asm/unaligned.h>
  43. #include "b43legacy.h"
  44. #include "main.h"
  45. #include "debugfs.h"
  46. #include "phy.h"
  47. #include "dma.h"
  48. #include "pio.h"
  49. #include "sysfs.h"
  50. #include "xmit.h"
  51. #include "radio.h"
  52. MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  53. MODULE_AUTHOR("Martin Langer");
  54. MODULE_AUTHOR("Stefano Brivio");
  55. MODULE_AUTHOR("Michael Buesch");
  56. MODULE_LICENSE("GPL");
  57. MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
  58. #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  59. static int modparam_pio;
  60. module_param_named(pio, modparam_pio, int, 0444);
  61. MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  62. #elif defined(CONFIG_B43LEGACY_DMA)
  63. # define modparam_pio 0
  64. #elif defined(CONFIG_B43LEGACY_PIO)
  65. # define modparam_pio 1
  66. #endif
  67. static int modparam_bad_frames_preempt;
  68. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  69. MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  70. " Preemption");
  71. static char modparam_fwpostfix[16];
  72. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  73. MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  74. /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  75. static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  76. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  77. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  78. SSB_DEVTABLE_END
  79. };
  80. MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  81. /* Channel and ratetables are shared for all devices.
  82. * They can't be const, because ieee80211 puts some precalculated
  83. * data in there. This data is the same for all devices, so we don't
  84. * get concurrency issues */
  85. #define RATETAB_ENT(_rateid, _flags) \
  86. { \
  87. .rate = B43legacy_RATE_TO_100KBPS(_rateid), \
  88. .val = (_rateid), \
  89. .val2 = (_rateid), \
  90. .flags = (_flags), \
  91. }
  92. static struct ieee80211_rate __b43legacy_ratetable[] = {
  93. RATETAB_ENT(B43legacy_CCK_RATE_1MB, IEEE80211_RATE_CCK),
  94. RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
  95. RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
  96. RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
  97. RATETAB_ENT(B43legacy_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
  98. RATETAB_ENT(B43legacy_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
  99. RATETAB_ENT(B43legacy_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
  100. RATETAB_ENT(B43legacy_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
  101. RATETAB_ENT(B43legacy_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
  102. RATETAB_ENT(B43legacy_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
  103. RATETAB_ENT(B43legacy_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
  104. RATETAB_ENT(B43legacy_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
  105. };
  106. #define b43legacy_a_ratetable (__b43legacy_ratetable + 4)
  107. #define b43legacy_a_ratetable_size 8
  108. #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
  109. #define b43legacy_b_ratetable_size 4
  110. #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
  111. #define b43legacy_g_ratetable_size 12
  112. #define CHANTAB_ENT(_chanid, _freq) \
  113. { \
  114. .chan = (_chanid), \
  115. .freq = (_freq), \
  116. .val = (_chanid), \
  117. .flag = IEEE80211_CHAN_W_SCAN | \
  118. IEEE80211_CHAN_W_ACTIVE_SCAN | \
  119. IEEE80211_CHAN_W_IBSS, \
  120. .power_level = 0x0A, \
  121. .antenna_max = 0xFF, \
  122. }
  123. static struct ieee80211_channel b43legacy_bg_chantable[] = {
  124. CHANTAB_ENT(1, 2412),
  125. CHANTAB_ENT(2, 2417),
  126. CHANTAB_ENT(3, 2422),
  127. CHANTAB_ENT(4, 2427),
  128. CHANTAB_ENT(5, 2432),
  129. CHANTAB_ENT(6, 2437),
  130. CHANTAB_ENT(7, 2442),
  131. CHANTAB_ENT(8, 2447),
  132. CHANTAB_ENT(9, 2452),
  133. CHANTAB_ENT(10, 2457),
  134. CHANTAB_ENT(11, 2462),
  135. CHANTAB_ENT(12, 2467),
  136. CHANTAB_ENT(13, 2472),
  137. CHANTAB_ENT(14, 2484),
  138. };
  139. #define b43legacy_bg_chantable_size ARRAY_SIZE(b43legacy_bg_chantable)
  140. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
  141. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
  142. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
  143. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
  144. static int b43legacy_ratelimit(struct b43legacy_wl *wl)
  145. {
  146. if (!wl || !wl->current_dev)
  147. return 1;
  148. if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
  149. return 1;
  150. /* We are up and running.
  151. * Ratelimit the messages to avoid DoS over the net. */
  152. return net_ratelimit();
  153. }
  154. void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
  155. {
  156. va_list args;
  157. if (!b43legacy_ratelimit(wl))
  158. return;
  159. va_start(args, fmt);
  160. printk(KERN_INFO "b43legacy-%s: ",
  161. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  162. vprintk(fmt, args);
  163. va_end(args);
  164. }
  165. void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
  166. {
  167. va_list args;
  168. if (!b43legacy_ratelimit(wl))
  169. return;
  170. va_start(args, fmt);
  171. printk(KERN_ERR "b43legacy-%s ERROR: ",
  172. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  173. vprintk(fmt, args);
  174. va_end(args);
  175. }
  176. void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
  177. {
  178. va_list args;
  179. if (!b43legacy_ratelimit(wl))
  180. return;
  181. va_start(args, fmt);
  182. printk(KERN_WARNING "b43legacy-%s warning: ",
  183. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  184. vprintk(fmt, args);
  185. va_end(args);
  186. }
  187. #if B43legacy_DEBUG
  188. void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
  189. {
  190. va_list args;
  191. va_start(args, fmt);
  192. printk(KERN_DEBUG "b43legacy-%s debug: ",
  193. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  194. vprintk(fmt, args);
  195. va_end(args);
  196. }
  197. #endif /* DEBUG */
  198. static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
  199. u32 val)
  200. {
  201. u32 status;
  202. B43legacy_WARN_ON(offset % 4 != 0);
  203. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  204. if (status & B43legacy_MACCTL_BE)
  205. val = swab32(val);
  206. b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
  207. mmiowb();
  208. b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
  209. }
  210. static inline
  211. void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
  212. u16 routing, u16 offset)
  213. {
  214. u32 control;
  215. /* "offset" is the WORD offset. */
  216. control = routing;
  217. control <<= 16;
  218. control |= offset;
  219. b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
  220. }
  221. u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
  222. u16 routing, u16 offset)
  223. {
  224. u32 ret;
  225. if (routing == B43legacy_SHM_SHARED) {
  226. B43legacy_WARN_ON((offset & 0x0001) != 0);
  227. if (offset & 0x0003) {
  228. /* Unaligned access */
  229. b43legacy_shm_control_word(dev, routing, offset >> 2);
  230. ret = b43legacy_read16(dev,
  231. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  232. ret <<= 16;
  233. b43legacy_shm_control_word(dev, routing,
  234. (offset >> 2) + 1);
  235. ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  236. return ret;
  237. }
  238. offset >>= 2;
  239. }
  240. b43legacy_shm_control_word(dev, routing, offset);
  241. ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
  242. return ret;
  243. }
  244. u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
  245. u16 routing, u16 offset)
  246. {
  247. u16 ret;
  248. if (routing == B43legacy_SHM_SHARED) {
  249. B43legacy_WARN_ON((offset & 0x0001) != 0);
  250. if (offset & 0x0003) {
  251. /* Unaligned access */
  252. b43legacy_shm_control_word(dev, routing, offset >> 2);
  253. ret = b43legacy_read16(dev,
  254. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  255. return ret;
  256. }
  257. offset >>= 2;
  258. }
  259. b43legacy_shm_control_word(dev, routing, offset);
  260. ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  261. return ret;
  262. }
  263. void b43legacy_shm_write32(struct b43legacy_wldev *dev,
  264. u16 routing, u16 offset,
  265. u32 value)
  266. {
  267. if (routing == B43legacy_SHM_SHARED) {
  268. B43legacy_WARN_ON((offset & 0x0001) != 0);
  269. if (offset & 0x0003) {
  270. /* Unaligned access */
  271. b43legacy_shm_control_word(dev, routing, offset >> 2);
  272. mmiowb();
  273. b43legacy_write16(dev,
  274. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  275. (value >> 16) & 0xffff);
  276. mmiowb();
  277. b43legacy_shm_control_word(dev, routing,
  278. (offset >> 2) + 1);
  279. mmiowb();
  280. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
  281. value & 0xffff);
  282. return;
  283. }
  284. offset >>= 2;
  285. }
  286. b43legacy_shm_control_word(dev, routing, offset);
  287. mmiowb();
  288. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
  289. }
  290. void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
  291. u16 value)
  292. {
  293. if (routing == B43legacy_SHM_SHARED) {
  294. B43legacy_WARN_ON((offset & 0x0001) != 0);
  295. if (offset & 0x0003) {
  296. /* Unaligned access */
  297. b43legacy_shm_control_word(dev, routing, offset >> 2);
  298. mmiowb();
  299. b43legacy_write16(dev,
  300. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  301. value);
  302. return;
  303. }
  304. offset >>= 2;
  305. }
  306. b43legacy_shm_control_word(dev, routing, offset);
  307. mmiowb();
  308. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
  309. }
  310. /* Read HostFlags */
  311. u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
  312. {
  313. u32 ret;
  314. ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  315. B43legacy_SHM_SH_HOSTFHI);
  316. ret <<= 16;
  317. ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  318. B43legacy_SHM_SH_HOSTFLO);
  319. return ret;
  320. }
  321. /* Write HostFlags */
  322. void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
  323. {
  324. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  325. B43legacy_SHM_SH_HOSTFLO,
  326. (value & 0x0000FFFF));
  327. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  328. B43legacy_SHM_SH_HOSTFHI,
  329. ((value & 0xFFFF0000) >> 16));
  330. }
  331. void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
  332. {
  333. /* We need to be careful. As we read the TSF from multiple
  334. * registers, we should take care of register overflows.
  335. * In theory, the whole tsf read process should be atomic.
  336. * We try to be atomic here, by restaring the read process,
  337. * if any of the high registers changed (overflew).
  338. */
  339. if (dev->dev->id.revision >= 3) {
  340. u32 low;
  341. u32 high;
  342. u32 high2;
  343. do {
  344. high = b43legacy_read32(dev,
  345. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  346. low = b43legacy_read32(dev,
  347. B43legacy_MMIO_REV3PLUS_TSF_LOW);
  348. high2 = b43legacy_read32(dev,
  349. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  350. } while (unlikely(high != high2));
  351. *tsf = high;
  352. *tsf <<= 32;
  353. *tsf |= low;
  354. } else {
  355. u64 tmp;
  356. u16 v0;
  357. u16 v1;
  358. u16 v2;
  359. u16 v3;
  360. u16 test1;
  361. u16 test2;
  362. u16 test3;
  363. do {
  364. v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  365. v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  366. v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  367. v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
  368. test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  369. test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  370. test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  371. } while (v3 != test3 || v2 != test2 || v1 != test1);
  372. *tsf = v3;
  373. *tsf <<= 48;
  374. tmp = v2;
  375. tmp <<= 32;
  376. *tsf |= tmp;
  377. tmp = v1;
  378. tmp <<= 16;
  379. *tsf |= tmp;
  380. *tsf |= v0;
  381. }
  382. }
  383. static void b43legacy_time_lock(struct b43legacy_wldev *dev)
  384. {
  385. u32 status;
  386. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  387. status |= B43legacy_MACCTL_TBTTHOLD;
  388. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
  389. mmiowb();
  390. }
  391. static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
  392. {
  393. u32 status;
  394. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  395. status &= ~B43legacy_MACCTL_TBTTHOLD;
  396. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
  397. }
  398. static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
  399. {
  400. /* Be careful with the in-progress timer.
  401. * First zero out the low register, so we have a full
  402. * register-overflow duration to complete the operation.
  403. */
  404. if (dev->dev->id.revision >= 3) {
  405. u32 lo = (tsf & 0x00000000FFFFFFFFULL);
  406. u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
  407. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
  408. mmiowb();
  409. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
  410. hi);
  411. mmiowb();
  412. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
  413. lo);
  414. } else {
  415. u16 v0 = (tsf & 0x000000000000FFFFULL);
  416. u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
  417. u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
  418. u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
  419. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
  420. mmiowb();
  421. b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
  422. mmiowb();
  423. b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
  424. mmiowb();
  425. b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
  426. mmiowb();
  427. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
  428. }
  429. }
  430. void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
  431. {
  432. b43legacy_time_lock(dev);
  433. b43legacy_tsf_write_locked(dev, tsf);
  434. b43legacy_time_unlock(dev);
  435. }
  436. static
  437. void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
  438. u16 offset, const u8 *mac)
  439. {
  440. static const u8 zero_addr[ETH_ALEN] = { 0 };
  441. u16 data;
  442. if (!mac)
  443. mac = zero_addr;
  444. offset |= 0x0020;
  445. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
  446. data = mac[0];
  447. data |= mac[1] << 8;
  448. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  449. data = mac[2];
  450. data |= mac[3] << 8;
  451. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  452. data = mac[4];
  453. data |= mac[5] << 8;
  454. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  455. }
  456. static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
  457. {
  458. static const u8 zero_addr[ETH_ALEN] = { 0 };
  459. const u8 *mac = dev->wl->mac_addr;
  460. const u8 *bssid = dev->wl->bssid;
  461. u8 mac_bssid[ETH_ALEN * 2];
  462. int i;
  463. u32 tmp;
  464. if (!bssid)
  465. bssid = zero_addr;
  466. if (!mac)
  467. mac = zero_addr;
  468. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
  469. memcpy(mac_bssid, mac, ETH_ALEN);
  470. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  471. /* Write our MAC address and BSSID to template ram */
  472. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  473. tmp = (u32)(mac_bssid[i + 0]);
  474. tmp |= (u32)(mac_bssid[i + 1]) << 8;
  475. tmp |= (u32)(mac_bssid[i + 2]) << 16;
  476. tmp |= (u32)(mac_bssid[i + 3]) << 24;
  477. b43legacy_ram_write(dev, 0x20 + i, tmp);
  478. b43legacy_ram_write(dev, 0x78 + i, tmp);
  479. b43legacy_ram_write(dev, 0x478 + i, tmp);
  480. }
  481. }
  482. static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
  483. {
  484. b43legacy_write_mac_bssid_templates(dev);
  485. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
  486. dev->wl->mac_addr);
  487. }
  488. static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
  489. u16 slot_time)
  490. {
  491. /* slot_time is in usec. */
  492. if (dev->phy.type != B43legacy_PHYTYPE_G)
  493. return;
  494. b43legacy_write16(dev, 0x684, 510 + slot_time);
  495. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
  496. slot_time);
  497. }
  498. static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
  499. {
  500. b43legacy_set_slot_time(dev, 9);
  501. dev->short_slot = 1;
  502. }
  503. static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
  504. {
  505. b43legacy_set_slot_time(dev, 20);
  506. dev->short_slot = 0;
  507. }
  508. /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
  509. * Returns the _previously_ enabled IRQ mask.
  510. */
  511. static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
  512. u32 mask)
  513. {
  514. u32 old_mask;
  515. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  516. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
  517. mask);
  518. return old_mask;
  519. }
  520. /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
  521. * Returns the _previously_ enabled IRQ mask.
  522. */
  523. static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
  524. u32 mask)
  525. {
  526. u32 old_mask;
  527. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  528. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
  529. return old_mask;
  530. }
  531. /* Synchronize IRQ top- and bottom-half.
  532. * IRQs must be masked before calling this.
  533. * This must not be called with the irq_lock held.
  534. */
  535. static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
  536. {
  537. synchronize_irq(dev->dev->irq);
  538. tasklet_kill(&dev->isr_tasklet);
  539. }
  540. /* DummyTransmission function, as documented on
  541. * http://bcm-specs.sipsolutions.net/DummyTransmission
  542. */
  543. void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
  544. {
  545. struct b43legacy_phy *phy = &dev->phy;
  546. unsigned int i;
  547. unsigned int max_loop;
  548. u16 value;
  549. u32 buffer[5] = {
  550. 0x00000000,
  551. 0x00D40000,
  552. 0x00000000,
  553. 0x01000000,
  554. 0x00000000,
  555. };
  556. switch (phy->type) {
  557. case B43legacy_PHYTYPE_B:
  558. case B43legacy_PHYTYPE_G:
  559. max_loop = 0xFA;
  560. buffer[0] = 0x000B846E;
  561. break;
  562. default:
  563. B43legacy_BUG_ON(1);
  564. return;
  565. }
  566. for (i = 0; i < 5; i++)
  567. b43legacy_ram_write(dev, i * 4, buffer[i]);
  568. /* dummy read follows */
  569. b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  570. b43legacy_write16(dev, 0x0568, 0x0000);
  571. b43legacy_write16(dev, 0x07C0, 0x0000);
  572. b43legacy_write16(dev, 0x050C, 0x0000);
  573. b43legacy_write16(dev, 0x0508, 0x0000);
  574. b43legacy_write16(dev, 0x050A, 0x0000);
  575. b43legacy_write16(dev, 0x054C, 0x0000);
  576. b43legacy_write16(dev, 0x056A, 0x0014);
  577. b43legacy_write16(dev, 0x0568, 0x0826);
  578. b43legacy_write16(dev, 0x0500, 0x0000);
  579. b43legacy_write16(dev, 0x0502, 0x0030);
  580. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  581. b43legacy_radio_write16(dev, 0x0051, 0x0017);
  582. for (i = 0x00; i < max_loop; i++) {
  583. value = b43legacy_read16(dev, 0x050E);
  584. if (value & 0x0080)
  585. break;
  586. udelay(10);
  587. }
  588. for (i = 0x00; i < 0x0A; i++) {
  589. value = b43legacy_read16(dev, 0x050E);
  590. if (value & 0x0400)
  591. break;
  592. udelay(10);
  593. }
  594. for (i = 0x00; i < 0x0A; i++) {
  595. value = b43legacy_read16(dev, 0x0690);
  596. if (!(value & 0x0100))
  597. break;
  598. udelay(10);
  599. }
  600. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  601. b43legacy_radio_write16(dev, 0x0051, 0x0037);
  602. }
  603. /* Turn the Analog ON/OFF */
  604. static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
  605. {
  606. b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
  607. }
  608. void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
  609. {
  610. u32 tmslow;
  611. u32 macctl;
  612. flags |= B43legacy_TMSLOW_PHYCLKEN;
  613. flags |= B43legacy_TMSLOW_PHYRESET;
  614. ssb_device_enable(dev->dev, flags);
  615. msleep(2); /* Wait for the PLL to turn on. */
  616. /* Now take the PHY out of Reset again */
  617. tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
  618. tmslow |= SSB_TMSLOW_FGC;
  619. tmslow &= ~B43legacy_TMSLOW_PHYRESET;
  620. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  621. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  622. msleep(1);
  623. tmslow &= ~SSB_TMSLOW_FGC;
  624. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  625. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  626. msleep(1);
  627. /* Turn Analog ON */
  628. b43legacy_switch_analog(dev, 1);
  629. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  630. macctl &= ~B43legacy_MACCTL_GMODE;
  631. if (flags & B43legacy_TMSLOW_GMODE) {
  632. macctl |= B43legacy_MACCTL_GMODE;
  633. dev->phy.gmode = 1;
  634. } else
  635. dev->phy.gmode = 0;
  636. macctl |= B43legacy_MACCTL_IHR_ENABLED;
  637. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  638. }
  639. static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
  640. {
  641. u32 v0;
  642. u32 v1;
  643. u16 tmp;
  644. struct b43legacy_txstatus stat;
  645. while (1) {
  646. v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  647. if (!(v0 & 0x00000001))
  648. break;
  649. v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  650. stat.cookie = (v0 >> 16);
  651. stat.seq = (v1 & 0x0000FFFF);
  652. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  653. tmp = (v0 & 0x0000FFFF);
  654. stat.frame_count = ((tmp & 0xF000) >> 12);
  655. stat.rts_count = ((tmp & 0x0F00) >> 8);
  656. stat.supp_reason = ((tmp & 0x001C) >> 2);
  657. stat.pm_indicated = !!(tmp & 0x0080);
  658. stat.intermediate = !!(tmp & 0x0040);
  659. stat.for_ampdu = !!(tmp & 0x0020);
  660. stat.acked = !!(tmp & 0x0002);
  661. b43legacy_handle_txstatus(dev, &stat);
  662. }
  663. }
  664. static void drain_txstatus_queue(struct b43legacy_wldev *dev)
  665. {
  666. u32 dummy;
  667. if (dev->dev->id.revision < 5)
  668. return;
  669. /* Read all entries from the microcode TXstatus FIFO
  670. * and throw them away.
  671. */
  672. while (1) {
  673. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  674. if (!(dummy & 0x00000001))
  675. break;
  676. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  677. }
  678. }
  679. static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
  680. {
  681. u32 val = 0;
  682. val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
  683. val <<= 16;
  684. val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
  685. return val;
  686. }
  687. static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
  688. {
  689. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
  690. (jssi & 0x0000FFFF));
  691. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
  692. (jssi & 0xFFFF0000) >> 16);
  693. }
  694. static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
  695. {
  696. b43legacy_jssi_write(dev, 0x7F7F7F7F);
  697. b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
  698. b43legacy_read32(dev,
  699. B43legacy_MMIO_MACCMD)
  700. | (1 << 4));
  701. B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
  702. dev->phy.channel);
  703. }
  704. static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
  705. {
  706. /* Top half of Link Quality calculation. */
  707. if (dev->noisecalc.calculation_running)
  708. return;
  709. dev->noisecalc.channel_at_start = dev->phy.channel;
  710. dev->noisecalc.calculation_running = 1;
  711. dev->noisecalc.nr_samples = 0;
  712. b43legacy_generate_noise_sample(dev);
  713. }
  714. static void handle_irq_noise(struct b43legacy_wldev *dev)
  715. {
  716. struct b43legacy_phy *phy = &dev->phy;
  717. u16 tmp;
  718. u8 noise[4];
  719. u8 i;
  720. u8 j;
  721. s32 average;
  722. /* Bottom half of Link Quality calculation. */
  723. B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
  724. if (dev->noisecalc.channel_at_start != phy->channel)
  725. goto drop_calculation;
  726. *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
  727. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  728. noise[2] == 0x7F || noise[3] == 0x7F)
  729. goto generate_new;
  730. /* Get the noise samples. */
  731. B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
  732. i = dev->noisecalc.nr_samples;
  733. noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  734. noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  735. noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  736. noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  737. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  738. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  739. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  740. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  741. dev->noisecalc.nr_samples++;
  742. if (dev->noisecalc.nr_samples == 8) {
  743. /* Calculate the Link Quality by the noise samples. */
  744. average = 0;
  745. for (i = 0; i < 8; i++) {
  746. for (j = 0; j < 4; j++)
  747. average += dev->noisecalc.samples[i][j];
  748. }
  749. average /= (8 * 4);
  750. average *= 125;
  751. average += 64;
  752. average /= 128;
  753. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  754. 0x40C);
  755. tmp = (tmp / 128) & 0x1F;
  756. if (tmp >= 8)
  757. average += 2;
  758. else
  759. average -= 25;
  760. if (tmp == 8)
  761. average -= 72;
  762. else
  763. average -= 48;
  764. dev->stats.link_noise = average;
  765. drop_calculation:
  766. dev->noisecalc.calculation_running = 0;
  767. return;
  768. }
  769. generate_new:
  770. b43legacy_generate_noise_sample(dev);
  771. }
  772. static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
  773. {
  774. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
  775. /* TODO: PS TBTT */
  776. } else {
  777. if (1/*FIXME: the last PSpoll frame was sent successfully */)
  778. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  779. }
  780. dev->reg124_set_0x4 = 0;
  781. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
  782. dev->reg124_set_0x4 = 1;
  783. }
  784. static void handle_irq_atim_end(struct b43legacy_wldev *dev)
  785. {
  786. if (!dev->reg124_set_0x4) /*FIXME rename this variable*/
  787. return;
  788. b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
  789. b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
  790. | 0x4);
  791. }
  792. static void handle_irq_pmq(struct b43legacy_wldev *dev)
  793. {
  794. u32 tmp;
  795. /* TODO: AP mode. */
  796. while (1) {
  797. tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
  798. if (!(tmp & 0x00000008))
  799. break;
  800. }
  801. /* 16bit write is odd, but correct. */
  802. b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
  803. }
  804. static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
  805. const u8 *data, u16 size,
  806. u16 ram_offset,
  807. u16 shm_size_offset, u8 rate)
  808. {
  809. u32 i;
  810. u32 tmp;
  811. struct b43legacy_plcp_hdr4 plcp;
  812. plcp.data = 0;
  813. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  814. b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  815. ram_offset += sizeof(u32);
  816. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  817. * So leave the first two bytes of the next write blank.
  818. */
  819. tmp = (u32)(data[0]) << 16;
  820. tmp |= (u32)(data[1]) << 24;
  821. b43legacy_ram_write(dev, ram_offset, tmp);
  822. ram_offset += sizeof(u32);
  823. for (i = 2; i < size; i += sizeof(u32)) {
  824. tmp = (u32)(data[i + 0]);
  825. if (i + 1 < size)
  826. tmp |= (u32)(data[i + 1]) << 8;
  827. if (i + 2 < size)
  828. tmp |= (u32)(data[i + 2]) << 16;
  829. if (i + 3 < size)
  830. tmp |= (u32)(data[i + 3]) << 24;
  831. b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
  832. }
  833. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
  834. size + sizeof(struct b43legacy_plcp_hdr6));
  835. }
  836. static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
  837. u16 ram_offset,
  838. u16 shm_size_offset, u8 rate)
  839. {
  840. int len;
  841. const u8 *data;
  842. B43legacy_WARN_ON(!dev->cached_beacon);
  843. len = min((size_t)dev->cached_beacon->len,
  844. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  845. data = (const u8 *)(dev->cached_beacon->data);
  846. b43legacy_write_template_common(dev, data,
  847. len, ram_offset,
  848. shm_size_offset, rate);
  849. }
  850. static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
  851. u16 shm_offset, u16 size,
  852. u8 rate)
  853. {
  854. struct b43legacy_plcp_hdr4 plcp;
  855. u32 tmp;
  856. __le16 dur;
  857. plcp.data = 0;
  858. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  859. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  860. dev->wl->vif,
  861. size,
  862. B43legacy_RATE_TO_100KBPS(rate));
  863. /* Write PLCP in two parts and timing for packet transfer */
  864. tmp = le32_to_cpu(plcp.data);
  865. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
  866. tmp & 0xFFFF);
  867. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
  868. tmp >> 16);
  869. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
  870. le16_to_cpu(dur));
  871. }
  872. /* Instead of using custom probe response template, this function
  873. * just patches custom beacon template by:
  874. * 1) Changing packet type
  875. * 2) Patching duration field
  876. * 3) Stripping TIM
  877. */
  878. static u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
  879. u16 *dest_size, u8 rate)
  880. {
  881. const u8 *src_data;
  882. u8 *dest_data;
  883. u16 src_size;
  884. u16 elem_size;
  885. u16 src_pos;
  886. u16 dest_pos;
  887. __le16 dur;
  888. struct ieee80211_hdr *hdr;
  889. B43legacy_WARN_ON(!dev->cached_beacon);
  890. src_size = dev->cached_beacon->len;
  891. src_data = (const u8 *)dev->cached_beacon->data;
  892. if (unlikely(src_size < 0x24)) {
  893. b43legacydbg(dev->wl, "b43legacy_generate_probe_resp: "
  894. "invalid beacon\n");
  895. return NULL;
  896. }
  897. dest_data = kmalloc(src_size, GFP_ATOMIC);
  898. if (unlikely(!dest_data))
  899. return NULL;
  900. /* 0x24 is offset of first variable-len Information-Element
  901. * in beacon frame.
  902. */
  903. memcpy(dest_data, src_data, 0x24);
  904. src_pos = 0x24;
  905. dest_pos = 0x24;
  906. for (; src_pos < src_size - 2; src_pos += elem_size) {
  907. elem_size = src_data[src_pos + 1] + 2;
  908. if (src_data[src_pos] != 0x05) { /* TIM */
  909. memcpy(dest_data + dest_pos, src_data + src_pos,
  910. elem_size);
  911. dest_pos += elem_size;
  912. }
  913. }
  914. *dest_size = dest_pos;
  915. hdr = (struct ieee80211_hdr *)dest_data;
  916. /* Set the frame control. */
  917. hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
  918. IEEE80211_STYPE_PROBE_RESP);
  919. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  920. dev->wl->vif,
  921. *dest_size,
  922. B43legacy_RATE_TO_100KBPS(rate));
  923. hdr->duration_id = dur;
  924. return dest_data;
  925. }
  926. static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
  927. u16 ram_offset,
  928. u16 shm_size_offset, u8 rate)
  929. {
  930. u8 *probe_resp_data;
  931. u16 size;
  932. B43legacy_WARN_ON(!dev->cached_beacon);
  933. size = dev->cached_beacon->len;
  934. probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
  935. if (unlikely(!probe_resp_data))
  936. return;
  937. /* Looks like PLCP headers plus packet timings are stored for
  938. * all possible basic rates
  939. */
  940. b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
  941. B43legacy_CCK_RATE_1MB);
  942. b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
  943. B43legacy_CCK_RATE_2MB);
  944. b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
  945. B43legacy_CCK_RATE_5MB);
  946. b43legacy_write_probe_resp_plcp(dev, 0x350, size,
  947. B43legacy_CCK_RATE_11MB);
  948. size = min((size_t)size,
  949. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  950. b43legacy_write_template_common(dev, probe_resp_data,
  951. size, ram_offset,
  952. shm_size_offset, rate);
  953. kfree(probe_resp_data);
  954. }
  955. static int b43legacy_refresh_cached_beacon(struct b43legacy_wldev *dev,
  956. struct sk_buff *beacon)
  957. {
  958. if (dev->cached_beacon)
  959. kfree_skb(dev->cached_beacon);
  960. dev->cached_beacon = beacon;
  961. return 0;
  962. }
  963. static void b43legacy_update_templates(struct b43legacy_wldev *dev)
  964. {
  965. u32 status;
  966. B43legacy_WARN_ON(!dev->cached_beacon);
  967. b43legacy_write_beacon_template(dev, 0x68, 0x18,
  968. B43legacy_CCK_RATE_1MB);
  969. b43legacy_write_beacon_template(dev, 0x468, 0x1A,
  970. B43legacy_CCK_RATE_1MB);
  971. b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
  972. B43legacy_CCK_RATE_11MB);
  973. status = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
  974. status |= 0x03;
  975. b43legacy_write32(dev, B43legacy_MMIO_MACCMD, status);
  976. }
  977. static void b43legacy_refresh_templates(struct b43legacy_wldev *dev,
  978. struct sk_buff *beacon)
  979. {
  980. int err;
  981. err = b43legacy_refresh_cached_beacon(dev, beacon);
  982. if (unlikely(err))
  983. return;
  984. b43legacy_update_templates(dev);
  985. }
  986. static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
  987. const u8 *ssid, u8 ssid_len)
  988. {
  989. u32 tmp;
  990. u16 i;
  991. u16 len;
  992. len = min((u16)ssid_len, (u16)0x100);
  993. for (i = 0; i < len; i += sizeof(u32)) {
  994. tmp = (u32)(ssid[i + 0]);
  995. if (i + 1 < len)
  996. tmp |= (u32)(ssid[i + 1]) << 8;
  997. if (i + 2 < len)
  998. tmp |= (u32)(ssid[i + 2]) << 16;
  999. if (i + 3 < len)
  1000. tmp |= (u32)(ssid[i + 3]) << 24;
  1001. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
  1002. 0x380 + i, tmp);
  1003. }
  1004. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1005. 0x48, len);
  1006. }
  1007. static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
  1008. u16 beacon_int)
  1009. {
  1010. b43legacy_time_lock(dev);
  1011. if (dev->dev->id.revision >= 3)
  1012. b43legacy_write32(dev, 0x188, (beacon_int << 16));
  1013. else {
  1014. b43legacy_write16(dev, 0x606, (beacon_int >> 6));
  1015. b43legacy_write16(dev, 0x610, beacon_int);
  1016. }
  1017. b43legacy_time_unlock(dev);
  1018. }
  1019. static void handle_irq_beacon(struct b43legacy_wldev *dev)
  1020. {
  1021. u32 status;
  1022. if (!b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
  1023. return;
  1024. dev->irq_savedstate &= ~B43legacy_IRQ_BEACON;
  1025. status = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
  1026. if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
  1027. /* ACK beacon IRQ. */
  1028. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1029. B43legacy_IRQ_BEACON);
  1030. dev->irq_savedstate |= B43legacy_IRQ_BEACON;
  1031. if (dev->cached_beacon)
  1032. kfree_skb(dev->cached_beacon);
  1033. dev->cached_beacon = NULL;
  1034. return;
  1035. }
  1036. if (!(status & 0x1)) {
  1037. b43legacy_write_beacon_template(dev, 0x68, 0x18,
  1038. B43legacy_CCK_RATE_1MB);
  1039. status |= 0x1;
  1040. b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
  1041. status);
  1042. }
  1043. if (!(status & 0x2)) {
  1044. b43legacy_write_beacon_template(dev, 0x468, 0x1A,
  1045. B43legacy_CCK_RATE_1MB);
  1046. status |= 0x2;
  1047. b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
  1048. status);
  1049. }
  1050. }
  1051. static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
  1052. {
  1053. }
  1054. /* Interrupt handler bottom-half */
  1055. static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
  1056. {
  1057. u32 reason;
  1058. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1059. u32 merged_dma_reason = 0;
  1060. int i;
  1061. unsigned long flags;
  1062. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1063. B43legacy_WARN_ON(b43legacy_status(dev) <
  1064. B43legacy_STAT_INITIALIZED);
  1065. reason = dev->irq_reason;
  1066. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1067. dma_reason[i] = dev->dma_reason[i];
  1068. merged_dma_reason |= dma_reason[i];
  1069. }
  1070. if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
  1071. b43legacyerr(dev->wl, "MAC transmission error\n");
  1072. if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
  1073. b43legacyerr(dev->wl, "PHY transmission error\n");
  1074. rmb();
  1075. if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
  1076. b43legacyerr(dev->wl, "Too many PHY TX errors, "
  1077. "restarting the controller\n");
  1078. b43legacy_controller_restart(dev, "PHY TX errors");
  1079. }
  1080. }
  1081. if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
  1082. B43legacy_DMAIRQ_NONFATALMASK))) {
  1083. if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
  1084. b43legacyerr(dev->wl, "Fatal DMA error: "
  1085. "0x%08X, 0x%08X, 0x%08X, "
  1086. "0x%08X, 0x%08X, 0x%08X\n",
  1087. dma_reason[0], dma_reason[1],
  1088. dma_reason[2], dma_reason[3],
  1089. dma_reason[4], dma_reason[5]);
  1090. b43legacy_controller_restart(dev, "DMA error");
  1091. mmiowb();
  1092. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1093. return;
  1094. }
  1095. if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
  1096. b43legacyerr(dev->wl, "DMA error: "
  1097. "0x%08X, 0x%08X, 0x%08X, "
  1098. "0x%08X, 0x%08X, 0x%08X\n",
  1099. dma_reason[0], dma_reason[1],
  1100. dma_reason[2], dma_reason[3],
  1101. dma_reason[4], dma_reason[5]);
  1102. }
  1103. if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
  1104. handle_irq_ucode_debug(dev);
  1105. if (reason & B43legacy_IRQ_TBTT_INDI)
  1106. handle_irq_tbtt_indication(dev);
  1107. if (reason & B43legacy_IRQ_ATIM_END)
  1108. handle_irq_atim_end(dev);
  1109. if (reason & B43legacy_IRQ_BEACON)
  1110. handle_irq_beacon(dev);
  1111. if (reason & B43legacy_IRQ_PMQ)
  1112. handle_irq_pmq(dev);
  1113. if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
  1114. ;/*TODO*/
  1115. if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
  1116. handle_irq_noise(dev);
  1117. /* Check the DMA reason registers for received data. */
  1118. if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
  1119. if (b43legacy_using_pio(dev))
  1120. b43legacy_pio_rx(dev->pio.queue0);
  1121. else
  1122. b43legacy_dma_rx(dev->dma.rx_ring0);
  1123. }
  1124. B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
  1125. B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
  1126. if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
  1127. if (b43legacy_using_pio(dev))
  1128. b43legacy_pio_rx(dev->pio.queue3);
  1129. else
  1130. b43legacy_dma_rx(dev->dma.rx_ring3);
  1131. }
  1132. B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
  1133. B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
  1134. if (reason & B43legacy_IRQ_TX_OK)
  1135. handle_irq_transmit_status(dev);
  1136. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1137. mmiowb();
  1138. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1139. }
  1140. static void pio_irq_workaround(struct b43legacy_wldev *dev,
  1141. u16 base, int queueidx)
  1142. {
  1143. u16 rxctl;
  1144. rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
  1145. if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
  1146. dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
  1147. else
  1148. dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
  1149. }
  1150. static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
  1151. {
  1152. if (b43legacy_using_pio(dev) &&
  1153. (dev->dev->id.revision < 3) &&
  1154. (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
  1155. /* Apply a PIO specific workaround to the dma_reasons */
  1156. pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
  1157. pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
  1158. pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
  1159. pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
  1160. }
  1161. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
  1162. b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
  1163. dev->dma_reason[0]);
  1164. b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
  1165. dev->dma_reason[1]);
  1166. b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
  1167. dev->dma_reason[2]);
  1168. b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
  1169. dev->dma_reason[3]);
  1170. b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
  1171. dev->dma_reason[4]);
  1172. b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
  1173. dev->dma_reason[5]);
  1174. }
  1175. /* Interrupt handler top-half */
  1176. static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
  1177. {
  1178. irqreturn_t ret = IRQ_NONE;
  1179. struct b43legacy_wldev *dev = dev_id;
  1180. u32 reason;
  1181. if (!dev)
  1182. return IRQ_NONE;
  1183. spin_lock(&dev->wl->irq_lock);
  1184. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  1185. goto out;
  1186. reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1187. if (reason == 0xffffffff) /* shared IRQ */
  1188. goto out;
  1189. ret = IRQ_HANDLED;
  1190. reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  1191. if (!reason)
  1192. goto out;
  1193. dev->dma_reason[0] = b43legacy_read32(dev,
  1194. B43legacy_MMIO_DMA0_REASON)
  1195. & 0x0001DC00;
  1196. dev->dma_reason[1] = b43legacy_read32(dev,
  1197. B43legacy_MMIO_DMA1_REASON)
  1198. & 0x0000DC00;
  1199. dev->dma_reason[2] = b43legacy_read32(dev,
  1200. B43legacy_MMIO_DMA2_REASON)
  1201. & 0x0000DC00;
  1202. dev->dma_reason[3] = b43legacy_read32(dev,
  1203. B43legacy_MMIO_DMA3_REASON)
  1204. & 0x0001DC00;
  1205. dev->dma_reason[4] = b43legacy_read32(dev,
  1206. B43legacy_MMIO_DMA4_REASON)
  1207. & 0x0000DC00;
  1208. dev->dma_reason[5] = b43legacy_read32(dev,
  1209. B43legacy_MMIO_DMA5_REASON)
  1210. & 0x0000DC00;
  1211. b43legacy_interrupt_ack(dev, reason);
  1212. /* disable all IRQs. They are enabled again in the bottom half. */
  1213. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  1214. B43legacy_IRQ_ALL);
  1215. /* save the reason code and call our bottom half. */
  1216. dev->irq_reason = reason;
  1217. tasklet_schedule(&dev->isr_tasklet);
  1218. out:
  1219. mmiowb();
  1220. spin_unlock(&dev->wl->irq_lock);
  1221. return ret;
  1222. }
  1223. static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
  1224. {
  1225. release_firmware(dev->fw.ucode);
  1226. dev->fw.ucode = NULL;
  1227. release_firmware(dev->fw.pcm);
  1228. dev->fw.pcm = NULL;
  1229. release_firmware(dev->fw.initvals);
  1230. dev->fw.initvals = NULL;
  1231. release_firmware(dev->fw.initvals_band);
  1232. dev->fw.initvals_band = NULL;
  1233. }
  1234. static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
  1235. {
  1236. b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
  1237. "Drivers/b43#devicefirmware "
  1238. "and download the correct firmware (version 3).\n");
  1239. }
  1240. static int do_request_fw(struct b43legacy_wldev *dev,
  1241. const char *name,
  1242. const struct firmware **fw)
  1243. {
  1244. char path[sizeof(modparam_fwpostfix) + 32];
  1245. struct b43legacy_fw_header *hdr;
  1246. u32 size;
  1247. int err;
  1248. if (!name)
  1249. return 0;
  1250. snprintf(path, ARRAY_SIZE(path),
  1251. "b43legacy%s/%s.fw",
  1252. modparam_fwpostfix, name);
  1253. err = request_firmware(fw, path, dev->dev->dev);
  1254. if (err) {
  1255. b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
  1256. "or load failed.\n", path);
  1257. return err;
  1258. }
  1259. if ((*fw)->size < sizeof(struct b43legacy_fw_header))
  1260. goto err_format;
  1261. hdr = (struct b43legacy_fw_header *)((*fw)->data);
  1262. switch (hdr->type) {
  1263. case B43legacy_FW_TYPE_UCODE:
  1264. case B43legacy_FW_TYPE_PCM:
  1265. size = be32_to_cpu(hdr->size);
  1266. if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
  1267. goto err_format;
  1268. /* fallthrough */
  1269. case B43legacy_FW_TYPE_IV:
  1270. if (hdr->ver != 1)
  1271. goto err_format;
  1272. break;
  1273. default:
  1274. goto err_format;
  1275. }
  1276. return err;
  1277. err_format:
  1278. b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
  1279. return -EPROTO;
  1280. }
  1281. static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
  1282. {
  1283. struct b43legacy_firmware *fw = &dev->fw;
  1284. const u8 rev = dev->dev->id.revision;
  1285. const char *filename;
  1286. u32 tmshigh;
  1287. int err;
  1288. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  1289. if (!fw->ucode) {
  1290. if (rev == 2)
  1291. filename = "ucode2";
  1292. else if (rev == 4)
  1293. filename = "ucode4";
  1294. else
  1295. filename = "ucode5";
  1296. err = do_request_fw(dev, filename, &fw->ucode);
  1297. if (err)
  1298. goto err_load;
  1299. }
  1300. if (!fw->pcm) {
  1301. if (rev < 5)
  1302. filename = "pcm4";
  1303. else
  1304. filename = "pcm5";
  1305. err = do_request_fw(dev, filename, &fw->pcm);
  1306. if (err)
  1307. goto err_load;
  1308. }
  1309. if (!fw->initvals) {
  1310. switch (dev->phy.type) {
  1311. case B43legacy_PHYTYPE_G:
  1312. if ((rev >= 5) && (rev <= 10))
  1313. filename = "b0g0initvals5";
  1314. else if (rev == 2 || rev == 4)
  1315. filename = "b0g0initvals2";
  1316. else
  1317. goto err_no_initvals;
  1318. break;
  1319. default:
  1320. goto err_no_initvals;
  1321. }
  1322. err = do_request_fw(dev, filename, &fw->initvals);
  1323. if (err)
  1324. goto err_load;
  1325. }
  1326. if (!fw->initvals_band) {
  1327. switch (dev->phy.type) {
  1328. case B43legacy_PHYTYPE_G:
  1329. if ((rev >= 5) && (rev <= 10))
  1330. filename = "b0g0bsinitvals5";
  1331. else if (rev >= 11)
  1332. filename = NULL;
  1333. else if (rev == 2 || rev == 4)
  1334. filename = NULL;
  1335. else
  1336. goto err_no_initvals;
  1337. break;
  1338. default:
  1339. goto err_no_initvals;
  1340. }
  1341. err = do_request_fw(dev, filename, &fw->initvals_band);
  1342. if (err)
  1343. goto err_load;
  1344. }
  1345. return 0;
  1346. err_load:
  1347. b43legacy_print_fw_helptext(dev->wl);
  1348. goto error;
  1349. err_no_initvals:
  1350. err = -ENODEV;
  1351. b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
  1352. "core rev %u\n", dev->phy.type, rev);
  1353. goto error;
  1354. error:
  1355. b43legacy_release_firmware(dev);
  1356. return err;
  1357. }
  1358. static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
  1359. {
  1360. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1361. const __be32 *data;
  1362. unsigned int i;
  1363. unsigned int len;
  1364. u16 fwrev;
  1365. u16 fwpatch;
  1366. u16 fwdate;
  1367. u16 fwtime;
  1368. u32 tmp, macctl;
  1369. int err = 0;
  1370. /* Jump the microcode PSM to offset 0 */
  1371. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1372. B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
  1373. macctl |= B43legacy_MACCTL_PSM_JMP0;
  1374. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1375. /* Zero out all microcode PSM registers and shared memory. */
  1376. for (i = 0; i < 64; i++)
  1377. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
  1378. for (i = 0; i < 4096; i += 2)
  1379. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
  1380. /* Upload Microcode. */
  1381. data = (__be32 *) (dev->fw.ucode->data + hdr_len);
  1382. len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
  1383. b43legacy_shm_control_word(dev,
  1384. B43legacy_SHM_UCODE |
  1385. B43legacy_SHM_AUTOINC_W,
  1386. 0x0000);
  1387. for (i = 0; i < len; i++) {
  1388. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1389. be32_to_cpu(data[i]));
  1390. udelay(10);
  1391. }
  1392. if (dev->fw.pcm) {
  1393. /* Upload PCM data. */
  1394. data = (__be32 *) (dev->fw.pcm->data + hdr_len);
  1395. len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
  1396. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
  1397. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
  1398. /* No need for autoinc bit in SHM_HW */
  1399. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
  1400. for (i = 0; i < len; i++) {
  1401. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1402. be32_to_cpu(data[i]));
  1403. udelay(10);
  1404. }
  1405. }
  1406. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1407. B43legacy_IRQ_ALL);
  1408. /* Start the microcode PSM */
  1409. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1410. macctl &= ~B43legacy_MACCTL_PSM_JMP0;
  1411. macctl |= B43legacy_MACCTL_PSM_RUN;
  1412. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1413. /* Wait for the microcode to load and respond */
  1414. i = 0;
  1415. while (1) {
  1416. tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1417. if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
  1418. break;
  1419. i++;
  1420. if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
  1421. b43legacyerr(dev->wl, "Microcode not responding\n");
  1422. b43legacy_print_fw_helptext(dev->wl);
  1423. err = -ENODEV;
  1424. goto error;
  1425. }
  1426. msleep_interruptible(50);
  1427. if (signal_pending(current)) {
  1428. err = -EINTR;
  1429. goto error;
  1430. }
  1431. }
  1432. /* dummy read follows */
  1433. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1434. /* Get and check the revisions. */
  1435. fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1436. B43legacy_SHM_SH_UCODEREV);
  1437. fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1438. B43legacy_SHM_SH_UCODEPATCH);
  1439. fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1440. B43legacy_SHM_SH_UCODEDATE);
  1441. fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1442. B43legacy_SHM_SH_UCODETIME);
  1443. if (fwrev > 0x128) {
  1444. b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
  1445. " Only firmware from binary drivers version 3.x"
  1446. " is supported. You must change your firmware"
  1447. " files.\n");
  1448. b43legacy_print_fw_helptext(dev->wl);
  1449. err = -EOPNOTSUPP;
  1450. goto error;
  1451. }
  1452. b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
  1453. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
  1454. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  1455. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
  1456. fwtime & 0x1F);
  1457. dev->fw.rev = fwrev;
  1458. dev->fw.patch = fwpatch;
  1459. return 0;
  1460. error:
  1461. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1462. macctl &= ~B43legacy_MACCTL_PSM_RUN;
  1463. macctl |= B43legacy_MACCTL_PSM_JMP0;
  1464. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1465. return err;
  1466. }
  1467. static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
  1468. const struct b43legacy_iv *ivals,
  1469. size_t count,
  1470. size_t array_size)
  1471. {
  1472. const struct b43legacy_iv *iv;
  1473. u16 offset;
  1474. size_t i;
  1475. bool bit32;
  1476. BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
  1477. iv = ivals;
  1478. for (i = 0; i < count; i++) {
  1479. if (array_size < sizeof(iv->offset_size))
  1480. goto err_format;
  1481. array_size -= sizeof(iv->offset_size);
  1482. offset = be16_to_cpu(iv->offset_size);
  1483. bit32 = !!(offset & B43legacy_IV_32BIT);
  1484. offset &= B43legacy_IV_OFFSET_MASK;
  1485. if (offset >= 0x1000)
  1486. goto err_format;
  1487. if (bit32) {
  1488. u32 value;
  1489. if (array_size < sizeof(iv->data.d32))
  1490. goto err_format;
  1491. array_size -= sizeof(iv->data.d32);
  1492. value = be32_to_cpu(get_unaligned(&iv->data.d32));
  1493. b43legacy_write32(dev, offset, value);
  1494. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1495. sizeof(__be16) +
  1496. sizeof(__be32));
  1497. } else {
  1498. u16 value;
  1499. if (array_size < sizeof(iv->data.d16))
  1500. goto err_format;
  1501. array_size -= sizeof(iv->data.d16);
  1502. value = be16_to_cpu(iv->data.d16);
  1503. b43legacy_write16(dev, offset, value);
  1504. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1505. sizeof(__be16) +
  1506. sizeof(__be16));
  1507. }
  1508. }
  1509. if (array_size)
  1510. goto err_format;
  1511. return 0;
  1512. err_format:
  1513. b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
  1514. b43legacy_print_fw_helptext(dev->wl);
  1515. return -EPROTO;
  1516. }
  1517. static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
  1518. {
  1519. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1520. const struct b43legacy_fw_header *hdr;
  1521. struct b43legacy_firmware *fw = &dev->fw;
  1522. const struct b43legacy_iv *ivals;
  1523. size_t count;
  1524. int err;
  1525. hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
  1526. ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
  1527. count = be32_to_cpu(hdr->size);
  1528. err = b43legacy_write_initvals(dev, ivals, count,
  1529. fw->initvals->size - hdr_len);
  1530. if (err)
  1531. goto out;
  1532. if (fw->initvals_band) {
  1533. hdr = (const struct b43legacy_fw_header *)
  1534. (fw->initvals_band->data);
  1535. ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
  1536. + hdr_len);
  1537. count = be32_to_cpu(hdr->size);
  1538. err = b43legacy_write_initvals(dev, ivals, count,
  1539. fw->initvals_band->size - hdr_len);
  1540. if (err)
  1541. goto out;
  1542. }
  1543. out:
  1544. return err;
  1545. }
  1546. /* Initialize the GPIOs
  1547. * http://bcm-specs.sipsolutions.net/GPIO
  1548. */
  1549. static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
  1550. {
  1551. struct ssb_bus *bus = dev->dev->bus;
  1552. struct ssb_device *gpiodev, *pcidev = NULL;
  1553. u32 mask;
  1554. u32 set;
  1555. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1556. b43legacy_read32(dev,
  1557. B43legacy_MMIO_MACCTL)
  1558. & 0xFFFF3FFF);
  1559. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1560. b43legacy_read16(dev,
  1561. B43legacy_MMIO_GPIO_MASK)
  1562. | 0x000F);
  1563. mask = 0x0000001F;
  1564. set = 0x0000000F;
  1565. if (dev->dev->bus->chip_id == 0x4301) {
  1566. mask |= 0x0060;
  1567. set |= 0x0060;
  1568. }
  1569. if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
  1570. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1571. b43legacy_read16(dev,
  1572. B43legacy_MMIO_GPIO_MASK)
  1573. | 0x0200);
  1574. mask |= 0x0200;
  1575. set |= 0x0200;
  1576. }
  1577. if (dev->dev->id.revision >= 2)
  1578. mask |= 0x0010; /* FIXME: This is redundant. */
  1579. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1580. pcidev = bus->pcicore.dev;
  1581. #endif
  1582. gpiodev = bus->chipco.dev ? : pcidev;
  1583. if (!gpiodev)
  1584. return 0;
  1585. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
  1586. (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
  1587. & mask) | set);
  1588. return 0;
  1589. }
  1590. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  1591. static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
  1592. {
  1593. struct ssb_bus *bus = dev->dev->bus;
  1594. struct ssb_device *gpiodev, *pcidev = NULL;
  1595. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1596. pcidev = bus->pcicore.dev;
  1597. #endif
  1598. gpiodev = bus->chipco.dev ? : pcidev;
  1599. if (!gpiodev)
  1600. return;
  1601. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
  1602. }
  1603. /* http://bcm-specs.sipsolutions.net/EnableMac */
  1604. void b43legacy_mac_enable(struct b43legacy_wldev *dev)
  1605. {
  1606. dev->mac_suspended--;
  1607. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1608. B43legacy_WARN_ON(irqs_disabled());
  1609. if (dev->mac_suspended == 0) {
  1610. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1611. b43legacy_read32(dev,
  1612. B43legacy_MMIO_MACCTL)
  1613. | B43legacy_MACCTL_ENABLED);
  1614. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1615. B43legacy_IRQ_MAC_SUSPENDED);
  1616. /* the next two are dummy reads */
  1617. b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1618. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1619. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  1620. /* Re-enable IRQs. */
  1621. spin_lock_irq(&dev->wl->irq_lock);
  1622. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1623. spin_unlock_irq(&dev->wl->irq_lock);
  1624. }
  1625. }
  1626. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  1627. void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
  1628. {
  1629. int i;
  1630. u32 tmp;
  1631. might_sleep();
  1632. B43legacy_WARN_ON(irqs_disabled());
  1633. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1634. if (dev->mac_suspended == 0) {
  1635. /* Mask IRQs before suspending MAC. Otherwise
  1636. * the MAC stays busy and won't suspend. */
  1637. spin_lock_irq(&dev->wl->irq_lock);
  1638. tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  1639. spin_unlock_irq(&dev->wl->irq_lock);
  1640. b43legacy_synchronize_irq(dev);
  1641. dev->irq_savedstate = tmp;
  1642. b43legacy_power_saving_ctl_bits(dev, -1, 1);
  1643. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1644. b43legacy_read32(dev,
  1645. B43legacy_MMIO_MACCTL)
  1646. & ~B43legacy_MACCTL_ENABLED);
  1647. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1648. for (i = 40; i; i--) {
  1649. tmp = b43legacy_read32(dev,
  1650. B43legacy_MMIO_GEN_IRQ_REASON);
  1651. if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
  1652. goto out;
  1653. msleep(1);
  1654. }
  1655. b43legacyerr(dev->wl, "MAC suspend failed\n");
  1656. }
  1657. out:
  1658. dev->mac_suspended++;
  1659. }
  1660. static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
  1661. {
  1662. struct b43legacy_wl *wl = dev->wl;
  1663. u32 ctl;
  1664. u16 cfp_pretbtt;
  1665. ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1666. /* Reset status to STA infrastructure mode. */
  1667. ctl &= ~B43legacy_MACCTL_AP;
  1668. ctl &= ~B43legacy_MACCTL_KEEP_CTL;
  1669. ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
  1670. ctl &= ~B43legacy_MACCTL_KEEP_BAD;
  1671. ctl &= ~B43legacy_MACCTL_PROMISC;
  1672. ctl &= ~B43legacy_MACCTL_BEACPROMISC;
  1673. ctl |= B43legacy_MACCTL_INFRA;
  1674. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  1675. ctl |= B43legacy_MACCTL_AP;
  1676. else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
  1677. ctl &= ~B43legacy_MACCTL_INFRA;
  1678. if (wl->filter_flags & FIF_CONTROL)
  1679. ctl |= B43legacy_MACCTL_KEEP_CTL;
  1680. if (wl->filter_flags & FIF_FCSFAIL)
  1681. ctl |= B43legacy_MACCTL_KEEP_BAD;
  1682. if (wl->filter_flags & FIF_PLCPFAIL)
  1683. ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
  1684. if (wl->filter_flags & FIF_PROMISC_IN_BSS)
  1685. ctl |= B43legacy_MACCTL_PROMISC;
  1686. if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
  1687. ctl |= B43legacy_MACCTL_BEACPROMISC;
  1688. /* Workaround: On old hardware the HW-MAC-address-filter
  1689. * doesn't work properly, so always run promisc in filter
  1690. * it in software. */
  1691. if (dev->dev->id.revision <= 4)
  1692. ctl |= B43legacy_MACCTL_PROMISC;
  1693. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
  1694. cfp_pretbtt = 2;
  1695. if ((ctl & B43legacy_MACCTL_INFRA) &&
  1696. !(ctl & B43legacy_MACCTL_AP)) {
  1697. if (dev->dev->bus->chip_id == 0x4306 &&
  1698. dev->dev->bus->chip_rev == 3)
  1699. cfp_pretbtt = 100;
  1700. else
  1701. cfp_pretbtt = 50;
  1702. }
  1703. b43legacy_write16(dev, 0x612, cfp_pretbtt);
  1704. }
  1705. static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
  1706. u16 rate,
  1707. int is_ofdm)
  1708. {
  1709. u16 offset;
  1710. if (is_ofdm) {
  1711. offset = 0x480;
  1712. offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  1713. } else {
  1714. offset = 0x4C0;
  1715. offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  1716. }
  1717. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
  1718. b43legacy_shm_read16(dev,
  1719. B43legacy_SHM_SHARED, offset));
  1720. }
  1721. static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
  1722. {
  1723. switch (dev->phy.type) {
  1724. case B43legacy_PHYTYPE_G:
  1725. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
  1726. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
  1727. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
  1728. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
  1729. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
  1730. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
  1731. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
  1732. /* fallthrough */
  1733. case B43legacy_PHYTYPE_B:
  1734. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
  1735. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
  1736. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
  1737. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
  1738. break;
  1739. default:
  1740. B43legacy_BUG_ON(1);
  1741. }
  1742. }
  1743. /* Set the TX-Antenna for management frames sent by firmware. */
  1744. static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
  1745. int antenna)
  1746. {
  1747. u16 ant = 0;
  1748. u16 tmp;
  1749. switch (antenna) {
  1750. case B43legacy_ANTENNA0:
  1751. ant |= B43legacy_TX4_PHY_ANT0;
  1752. break;
  1753. case B43legacy_ANTENNA1:
  1754. ant |= B43legacy_TX4_PHY_ANT1;
  1755. break;
  1756. case B43legacy_ANTENNA_AUTO:
  1757. ant |= B43legacy_TX4_PHY_ANTLAST;
  1758. break;
  1759. default:
  1760. B43legacy_BUG_ON(1);
  1761. }
  1762. /* FIXME We also need to set the other flags of the PHY control
  1763. * field somewhere. */
  1764. /* For Beacons */
  1765. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1766. B43legacy_SHM_SH_BEACPHYCTL);
  1767. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1768. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1769. B43legacy_SHM_SH_BEACPHYCTL, tmp);
  1770. /* For ACK/CTS */
  1771. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1772. B43legacy_SHM_SH_ACKCTSPHYCTL);
  1773. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1774. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1775. B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
  1776. /* For Probe Resposes */
  1777. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1778. B43legacy_SHM_SH_PRPHYCTL);
  1779. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1780. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1781. B43legacy_SHM_SH_PRPHYCTL, tmp);
  1782. }
  1783. /* This is the opposite of b43legacy_chip_init() */
  1784. static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
  1785. {
  1786. b43legacy_radio_turn_off(dev, 1);
  1787. b43legacy_gpio_cleanup(dev);
  1788. /* firmware is released later */
  1789. }
  1790. /* Initialize the chip
  1791. * http://bcm-specs.sipsolutions.net/ChipInit
  1792. */
  1793. static int b43legacy_chip_init(struct b43legacy_wldev *dev)
  1794. {
  1795. struct b43legacy_phy *phy = &dev->phy;
  1796. int err;
  1797. int tmp;
  1798. u32 value32, macctl;
  1799. u16 value16;
  1800. /* Initialize the MAC control */
  1801. macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
  1802. if (dev->phy.gmode)
  1803. macctl |= B43legacy_MACCTL_GMODE;
  1804. macctl |= B43legacy_MACCTL_INFRA;
  1805. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1806. err = b43legacy_request_firmware(dev);
  1807. if (err)
  1808. goto out;
  1809. err = b43legacy_upload_microcode(dev);
  1810. if (err)
  1811. goto out; /* firmware is released later */
  1812. err = b43legacy_gpio_init(dev);
  1813. if (err)
  1814. goto out; /* firmware is released later */
  1815. err = b43legacy_upload_initvals(dev);
  1816. if (err)
  1817. goto err_gpio_clean;
  1818. b43legacy_radio_turn_on(dev);
  1819. b43legacy_write16(dev, 0x03E6, 0x0000);
  1820. err = b43legacy_phy_init(dev);
  1821. if (err)
  1822. goto err_radio_off;
  1823. /* Select initial Interference Mitigation. */
  1824. tmp = phy->interfmode;
  1825. phy->interfmode = B43legacy_INTERFMODE_NONE;
  1826. b43legacy_radio_set_interference_mitigation(dev, tmp);
  1827. b43legacy_phy_set_antenna_diversity(dev);
  1828. b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
  1829. if (phy->type == B43legacy_PHYTYPE_B) {
  1830. value16 = b43legacy_read16(dev, 0x005E);
  1831. value16 |= 0x0004;
  1832. b43legacy_write16(dev, 0x005E, value16);
  1833. }
  1834. b43legacy_write32(dev, 0x0100, 0x01000000);
  1835. if (dev->dev->id.revision < 5)
  1836. b43legacy_write32(dev, 0x010C, 0x01000000);
  1837. value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1838. value32 &= ~B43legacy_MACCTL_INFRA;
  1839. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
  1840. value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1841. value32 |= B43legacy_MACCTL_INFRA;
  1842. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
  1843. if (b43legacy_using_pio(dev)) {
  1844. b43legacy_write32(dev, 0x0210, 0x00000100);
  1845. b43legacy_write32(dev, 0x0230, 0x00000100);
  1846. b43legacy_write32(dev, 0x0250, 0x00000100);
  1847. b43legacy_write32(dev, 0x0270, 0x00000100);
  1848. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
  1849. 0x0000);
  1850. }
  1851. /* Probe Response Timeout value */
  1852. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  1853. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
  1854. /* Initially set the wireless operation mode. */
  1855. b43legacy_adjust_opmode(dev);
  1856. if (dev->dev->id.revision < 3) {
  1857. b43legacy_write16(dev, 0x060E, 0x0000);
  1858. b43legacy_write16(dev, 0x0610, 0x8000);
  1859. b43legacy_write16(dev, 0x0604, 0x0000);
  1860. b43legacy_write16(dev, 0x0606, 0x0200);
  1861. } else {
  1862. b43legacy_write32(dev, 0x0188, 0x80000000);
  1863. b43legacy_write32(dev, 0x018C, 0x02000000);
  1864. }
  1865. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
  1866. b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
  1867. b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  1868. b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  1869. b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  1870. b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  1871. b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  1872. value32 = ssb_read32(dev->dev, SSB_TMSLOW);
  1873. value32 |= 0x00100000;
  1874. ssb_write32(dev->dev, SSB_TMSLOW, value32);
  1875. b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
  1876. dev->dev->bus->chipco.fast_pwrup_delay);
  1877. /* PHY TX errors counter. */
  1878. atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
  1879. B43legacy_WARN_ON(err != 0);
  1880. b43legacydbg(dev->wl, "Chip initialized\n");
  1881. out:
  1882. return err;
  1883. err_radio_off:
  1884. b43legacy_radio_turn_off(dev, 1);
  1885. err_gpio_clean:
  1886. b43legacy_gpio_cleanup(dev);
  1887. goto out;
  1888. }
  1889. static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
  1890. {
  1891. struct b43legacy_phy *phy = &dev->phy;
  1892. if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
  1893. return;
  1894. b43legacy_mac_suspend(dev);
  1895. b43legacy_phy_lo_g_measure(dev);
  1896. b43legacy_mac_enable(dev);
  1897. }
  1898. static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
  1899. {
  1900. b43legacy_phy_lo_mark_all_unused(dev);
  1901. if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
  1902. b43legacy_mac_suspend(dev);
  1903. b43legacy_calc_nrssi_slope(dev);
  1904. b43legacy_mac_enable(dev);
  1905. }
  1906. }
  1907. static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
  1908. {
  1909. /* Update device statistics. */
  1910. b43legacy_calculate_link_quality(dev);
  1911. }
  1912. static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
  1913. {
  1914. b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
  1915. atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
  1916. wmb();
  1917. }
  1918. static void do_periodic_work(struct b43legacy_wldev *dev)
  1919. {
  1920. unsigned int state;
  1921. state = dev->periodic_state;
  1922. if (state % 8 == 0)
  1923. b43legacy_periodic_every120sec(dev);
  1924. if (state % 4 == 0)
  1925. b43legacy_periodic_every60sec(dev);
  1926. if (state % 2 == 0)
  1927. b43legacy_periodic_every30sec(dev);
  1928. b43legacy_periodic_every15sec(dev);
  1929. }
  1930. /* Periodic work locking policy:
  1931. * The whole periodic work handler is protected by
  1932. * wl->mutex. If another lock is needed somewhere in the
  1933. * pwork callchain, it's aquired in-place, where it's needed.
  1934. */
  1935. static void b43legacy_periodic_work_handler(struct work_struct *work)
  1936. {
  1937. struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
  1938. periodic_work.work);
  1939. struct b43legacy_wl *wl = dev->wl;
  1940. unsigned long delay;
  1941. mutex_lock(&wl->mutex);
  1942. if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
  1943. goto out;
  1944. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
  1945. goto out_requeue;
  1946. do_periodic_work(dev);
  1947. dev->periodic_state++;
  1948. out_requeue:
  1949. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
  1950. delay = msecs_to_jiffies(50);
  1951. else
  1952. delay = round_jiffies_relative(HZ * 15);
  1953. queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
  1954. out:
  1955. mutex_unlock(&wl->mutex);
  1956. }
  1957. static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
  1958. {
  1959. struct delayed_work *work = &dev->periodic_work;
  1960. dev->periodic_state = 0;
  1961. INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
  1962. queue_delayed_work(dev->wl->hw->workqueue, work, 0);
  1963. }
  1964. /* Validate access to the chip (SHM) */
  1965. static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
  1966. {
  1967. u32 value;
  1968. u32 shm_backup;
  1969. shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
  1970. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
  1971. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  1972. 0xAA5555AA)
  1973. goto error;
  1974. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
  1975. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  1976. 0x55AAAA55)
  1977. goto error;
  1978. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
  1979. value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1980. if ((value | B43legacy_MACCTL_GMODE) !=
  1981. (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
  1982. goto error;
  1983. value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1984. if (value)
  1985. goto error;
  1986. return 0;
  1987. error:
  1988. b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
  1989. return -ENODEV;
  1990. }
  1991. static void b43legacy_security_init(struct b43legacy_wldev *dev)
  1992. {
  1993. dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
  1994. B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
  1995. dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1996. 0x0056);
  1997. /* KTP is a word address, but we address SHM bytewise.
  1998. * So multiply by two.
  1999. */
  2000. dev->ktp *= 2;
  2001. if (dev->dev->id.revision >= 5)
  2002. /* Number of RCMTA address slots */
  2003. b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
  2004. dev->max_nr_keys - 8);
  2005. }
  2006. static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
  2007. {
  2008. struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
  2009. unsigned long flags;
  2010. /* Don't take wl->mutex here, as it could deadlock with
  2011. * hwrng internal locking. It's not needed to take
  2012. * wl->mutex here, anyway. */
  2013. spin_lock_irqsave(&wl->irq_lock, flags);
  2014. *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
  2015. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2016. return (sizeof(u16));
  2017. }
  2018. static void b43legacy_rng_exit(struct b43legacy_wl *wl)
  2019. {
  2020. if (wl->rng_initialized)
  2021. hwrng_unregister(&wl->rng);
  2022. }
  2023. static int b43legacy_rng_init(struct b43legacy_wl *wl)
  2024. {
  2025. int err;
  2026. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  2027. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  2028. wl->rng.name = wl->rng_name;
  2029. wl->rng.data_read = b43legacy_rng_read;
  2030. wl->rng.priv = (unsigned long)wl;
  2031. wl->rng_initialized = 1;
  2032. err = hwrng_register(&wl->rng);
  2033. if (err) {
  2034. wl->rng_initialized = 0;
  2035. b43legacyerr(wl, "Failed to register the random "
  2036. "number generator (%d)\n", err);
  2037. }
  2038. return err;
  2039. }
  2040. static int b43legacy_op_tx(struct ieee80211_hw *hw,
  2041. struct sk_buff *skb,
  2042. struct ieee80211_tx_control *ctl)
  2043. {
  2044. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2045. struct b43legacy_wldev *dev = wl->current_dev;
  2046. int err = -ENODEV;
  2047. unsigned long flags;
  2048. if (unlikely(!dev))
  2049. goto out;
  2050. if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
  2051. goto out;
  2052. /* DMA-TX is done without a global lock. */
  2053. if (b43legacy_using_pio(dev)) {
  2054. spin_lock_irqsave(&wl->irq_lock, flags);
  2055. err = b43legacy_pio_tx(dev, skb, ctl);
  2056. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2057. } else
  2058. err = b43legacy_dma_tx(dev, skb, ctl);
  2059. out:
  2060. if (unlikely(err))
  2061. return NETDEV_TX_BUSY;
  2062. return NETDEV_TX_OK;
  2063. }
  2064. static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
  2065. int queue,
  2066. const struct ieee80211_tx_queue_params *params)
  2067. {
  2068. return 0;
  2069. }
  2070. static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
  2071. struct ieee80211_tx_queue_stats *stats)
  2072. {
  2073. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2074. struct b43legacy_wldev *dev = wl->current_dev;
  2075. unsigned long flags;
  2076. int err = -ENODEV;
  2077. if (!dev)
  2078. goto out;
  2079. spin_lock_irqsave(&wl->irq_lock, flags);
  2080. if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
  2081. if (b43legacy_using_pio(dev))
  2082. b43legacy_pio_get_tx_stats(dev, stats);
  2083. else
  2084. b43legacy_dma_get_tx_stats(dev, stats);
  2085. err = 0;
  2086. }
  2087. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2088. out:
  2089. return err;
  2090. }
  2091. static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
  2092. struct ieee80211_low_level_stats *stats)
  2093. {
  2094. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2095. unsigned long flags;
  2096. spin_lock_irqsave(&wl->irq_lock, flags);
  2097. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  2098. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2099. return 0;
  2100. }
  2101. static const char *phymode_to_string(unsigned int phymode)
  2102. {
  2103. switch (phymode) {
  2104. case B43legacy_PHYMODE_B:
  2105. return "B";
  2106. case B43legacy_PHYMODE_G:
  2107. return "G";
  2108. default:
  2109. B43legacy_BUG_ON(1);
  2110. }
  2111. return "";
  2112. }
  2113. static int find_wldev_for_phymode(struct b43legacy_wl *wl,
  2114. unsigned int phymode,
  2115. struct b43legacy_wldev **dev,
  2116. bool *gmode)
  2117. {
  2118. struct b43legacy_wldev *d;
  2119. list_for_each_entry(d, &wl->devlist, list) {
  2120. if (d->phy.possible_phymodes & phymode) {
  2121. /* Ok, this device supports the PHY-mode.
  2122. * Set the gmode bit. */
  2123. *gmode = 1;
  2124. *dev = d;
  2125. return 0;
  2126. }
  2127. }
  2128. return -ESRCH;
  2129. }
  2130. static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
  2131. {
  2132. struct ssb_device *sdev = dev->dev;
  2133. u32 tmslow;
  2134. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2135. tmslow &= ~B43legacy_TMSLOW_GMODE;
  2136. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2137. tmslow |= SSB_TMSLOW_FGC;
  2138. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2139. msleep(1);
  2140. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2141. tmslow &= ~SSB_TMSLOW_FGC;
  2142. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2143. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2144. msleep(1);
  2145. }
  2146. /* Expects wl->mutex locked */
  2147. static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
  2148. unsigned int new_mode)
  2149. {
  2150. struct b43legacy_wldev *up_dev;
  2151. struct b43legacy_wldev *down_dev;
  2152. int err;
  2153. bool gmode = 0;
  2154. int prev_status;
  2155. err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
  2156. if (err) {
  2157. b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
  2158. phymode_to_string(new_mode));
  2159. return err;
  2160. }
  2161. if ((up_dev == wl->current_dev) &&
  2162. (!!wl->current_dev->phy.gmode == !!gmode))
  2163. /* This device is already running. */
  2164. return 0;
  2165. b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
  2166. phymode_to_string(new_mode));
  2167. down_dev = wl->current_dev;
  2168. prev_status = b43legacy_status(down_dev);
  2169. /* Shutdown the currently running core. */
  2170. if (prev_status >= B43legacy_STAT_STARTED)
  2171. b43legacy_wireless_core_stop(down_dev);
  2172. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2173. b43legacy_wireless_core_exit(down_dev);
  2174. if (down_dev != up_dev)
  2175. /* We switch to a different core, so we put PHY into
  2176. * RESET on the old core. */
  2177. b43legacy_put_phy_into_reset(down_dev);
  2178. /* Now start the new core. */
  2179. up_dev->phy.gmode = gmode;
  2180. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2181. err = b43legacy_wireless_core_init(up_dev);
  2182. if (err) {
  2183. b43legacyerr(wl, "Fatal: Could not initialize device"
  2184. " for newly selected %s-PHY mode\n",
  2185. phymode_to_string(new_mode));
  2186. goto init_failure;
  2187. }
  2188. }
  2189. if (prev_status >= B43legacy_STAT_STARTED) {
  2190. err = b43legacy_wireless_core_start(up_dev);
  2191. if (err) {
  2192. b43legacyerr(wl, "Fatal: Coult not start device for "
  2193. "newly selected %s-PHY mode\n",
  2194. phymode_to_string(new_mode));
  2195. b43legacy_wireless_core_exit(up_dev);
  2196. goto init_failure;
  2197. }
  2198. }
  2199. B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
  2200. b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
  2201. wl->current_dev = up_dev;
  2202. return 0;
  2203. init_failure:
  2204. /* Whoops, failed to init the new core. No core is operating now. */
  2205. wl->current_dev = NULL;
  2206. return err;
  2207. }
  2208. static int b43legacy_antenna_from_ieee80211(u8 antenna)
  2209. {
  2210. switch (antenna) {
  2211. case 0: /* default/diversity */
  2212. return B43legacy_ANTENNA_DEFAULT;
  2213. case 1: /* Antenna 0 */
  2214. return B43legacy_ANTENNA0;
  2215. case 2: /* Antenna 1 */
  2216. return B43legacy_ANTENNA1;
  2217. default:
  2218. return B43legacy_ANTENNA_DEFAULT;
  2219. }
  2220. }
  2221. static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
  2222. struct ieee80211_conf *conf)
  2223. {
  2224. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2225. struct b43legacy_wldev *dev;
  2226. struct b43legacy_phy *phy;
  2227. unsigned long flags;
  2228. unsigned int new_phymode = 0xFFFF;
  2229. int antenna_tx;
  2230. int antenna_rx;
  2231. int err = 0;
  2232. u32 savedirqs;
  2233. antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
  2234. antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
  2235. mutex_lock(&wl->mutex);
  2236. /* Switch the PHY mode (if necessary). */
  2237. switch (conf->phymode) {
  2238. case MODE_IEEE80211B:
  2239. new_phymode = B43legacy_PHYMODE_B;
  2240. break;
  2241. case MODE_IEEE80211G:
  2242. new_phymode = B43legacy_PHYMODE_G;
  2243. break;
  2244. default:
  2245. B43legacy_WARN_ON(1);
  2246. }
  2247. err = b43legacy_switch_phymode(wl, new_phymode);
  2248. if (err)
  2249. goto out_unlock_mutex;
  2250. dev = wl->current_dev;
  2251. phy = &dev->phy;
  2252. /* Disable IRQs while reconfiguring the device.
  2253. * This makes it possible to drop the spinlock throughout
  2254. * the reconfiguration process. */
  2255. spin_lock_irqsave(&wl->irq_lock, flags);
  2256. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2257. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2258. goto out_unlock_mutex;
  2259. }
  2260. savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  2261. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2262. b43legacy_synchronize_irq(dev);
  2263. /* Switch to the requested channel.
  2264. * The firmware takes care of races with the TX handler. */
  2265. if (conf->channel_val != phy->channel)
  2266. b43legacy_radio_selectchannel(dev, conf->channel_val, 0);
  2267. /* Enable/Disable ShortSlot timing. */
  2268. if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
  2269. != dev->short_slot) {
  2270. B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
  2271. if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
  2272. b43legacy_short_slot_timing_enable(dev);
  2273. else
  2274. b43legacy_short_slot_timing_disable(dev);
  2275. }
  2276. dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  2277. /* Adjust the desired TX power level. */
  2278. if (conf->power_level != 0) {
  2279. if (conf->power_level != phy->power_level) {
  2280. phy->power_level = conf->power_level;
  2281. b43legacy_phy_xmitpower(dev);
  2282. }
  2283. }
  2284. /* Antennas for RX and management frame TX. */
  2285. b43legacy_mgmtframe_txantenna(dev, antenna_tx);
  2286. /* Update templates for AP mode. */
  2287. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  2288. b43legacy_set_beacon_int(dev, conf->beacon_int);
  2289. if (!!conf->radio_enabled != phy->radio_on) {
  2290. if (conf->radio_enabled) {
  2291. b43legacy_radio_turn_on(dev);
  2292. b43legacyinfo(dev->wl, "Radio turned on by software\n");
  2293. if (!dev->radio_hw_enable)
  2294. b43legacyinfo(dev->wl, "The hardware RF-kill"
  2295. " button still turns the radio"
  2296. " physically off. Press the"
  2297. " button to turn it on.\n");
  2298. } else {
  2299. b43legacy_radio_turn_off(dev, 0);
  2300. b43legacyinfo(dev->wl, "Radio turned off by"
  2301. " software\n");
  2302. }
  2303. }
  2304. spin_lock_irqsave(&wl->irq_lock, flags);
  2305. b43legacy_interrupt_enable(dev, savedirqs);
  2306. mmiowb();
  2307. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2308. out_unlock_mutex:
  2309. mutex_unlock(&wl->mutex);
  2310. return err;
  2311. }
  2312. static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
  2313. unsigned int changed,
  2314. unsigned int *fflags,
  2315. int mc_count,
  2316. struct dev_addr_list *mc_list)
  2317. {
  2318. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2319. struct b43legacy_wldev *dev = wl->current_dev;
  2320. unsigned long flags;
  2321. if (!dev) {
  2322. *fflags = 0;
  2323. return;
  2324. }
  2325. spin_lock_irqsave(&wl->irq_lock, flags);
  2326. *fflags &= FIF_PROMISC_IN_BSS |
  2327. FIF_ALLMULTI |
  2328. FIF_FCSFAIL |
  2329. FIF_PLCPFAIL |
  2330. FIF_CONTROL |
  2331. FIF_OTHER_BSS |
  2332. FIF_BCN_PRBRESP_PROMISC;
  2333. changed &= FIF_PROMISC_IN_BSS |
  2334. FIF_ALLMULTI |
  2335. FIF_FCSFAIL |
  2336. FIF_PLCPFAIL |
  2337. FIF_CONTROL |
  2338. FIF_OTHER_BSS |
  2339. FIF_BCN_PRBRESP_PROMISC;
  2340. wl->filter_flags = *fflags;
  2341. if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
  2342. b43legacy_adjust_opmode(dev);
  2343. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2344. }
  2345. static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
  2346. struct ieee80211_vif *vif,
  2347. struct ieee80211_if_conf *conf)
  2348. {
  2349. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2350. struct b43legacy_wldev *dev = wl->current_dev;
  2351. unsigned long flags;
  2352. if (!dev)
  2353. return -ENODEV;
  2354. mutex_lock(&wl->mutex);
  2355. spin_lock_irqsave(&wl->irq_lock, flags);
  2356. B43legacy_WARN_ON(wl->vif != vif);
  2357. if (conf->bssid)
  2358. memcpy(wl->bssid, conf->bssid, ETH_ALEN);
  2359. else
  2360. memset(wl->bssid, 0, ETH_ALEN);
  2361. if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
  2362. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
  2363. B43legacy_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
  2364. b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
  2365. if (conf->beacon)
  2366. b43legacy_refresh_templates(dev, conf->beacon);
  2367. }
  2368. b43legacy_write_mac_bssid_templates(dev);
  2369. }
  2370. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2371. mutex_unlock(&wl->mutex);
  2372. return 0;
  2373. }
  2374. /* Locking: wl->mutex */
  2375. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
  2376. {
  2377. struct b43legacy_wl *wl = dev->wl;
  2378. unsigned long flags;
  2379. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  2380. return;
  2381. /* Disable and sync interrupts. We must do this before than
  2382. * setting the status to INITIALIZED, as the interrupt handler
  2383. * won't care about IRQs then. */
  2384. spin_lock_irqsave(&wl->irq_lock, flags);
  2385. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  2386. B43legacy_IRQ_ALL);
  2387. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
  2388. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2389. b43legacy_synchronize_irq(dev);
  2390. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2391. mutex_unlock(&wl->mutex);
  2392. /* Must unlock as it would otherwise deadlock. No races here.
  2393. * Cancel the possibly running self-rearming periodic work. */
  2394. cancel_delayed_work_sync(&dev->periodic_work);
  2395. mutex_lock(&wl->mutex);
  2396. ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
  2397. b43legacy_mac_suspend(dev);
  2398. free_irq(dev->dev->irq, dev);
  2399. b43legacydbg(wl, "Wireless interface stopped\n");
  2400. }
  2401. /* Locking: wl->mutex */
  2402. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
  2403. {
  2404. int err;
  2405. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
  2406. drain_txstatus_queue(dev);
  2407. err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
  2408. IRQF_SHARED, KBUILD_MODNAME, dev);
  2409. if (err) {
  2410. b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
  2411. dev->dev->irq);
  2412. goto out;
  2413. }
  2414. /* We are ready to run. */
  2415. b43legacy_set_status(dev, B43legacy_STAT_STARTED);
  2416. /* Start data flow (TX/RX) */
  2417. b43legacy_mac_enable(dev);
  2418. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  2419. ieee80211_start_queues(dev->wl->hw);
  2420. /* Start maintenance work */
  2421. b43legacy_periodic_tasks_setup(dev);
  2422. b43legacydbg(dev->wl, "Wireless interface started\n");
  2423. out:
  2424. return err;
  2425. }
  2426. /* Get PHY and RADIO versioning numbers */
  2427. static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
  2428. {
  2429. struct b43legacy_phy *phy = &dev->phy;
  2430. u32 tmp;
  2431. u8 analog_type;
  2432. u8 phy_type;
  2433. u8 phy_rev;
  2434. u16 radio_manuf;
  2435. u16 radio_ver;
  2436. u16 radio_rev;
  2437. int unsupported = 0;
  2438. /* Get PHY versioning */
  2439. tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
  2440. analog_type = (tmp & B43legacy_PHYVER_ANALOG)
  2441. >> B43legacy_PHYVER_ANALOG_SHIFT;
  2442. phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
  2443. phy_rev = (tmp & B43legacy_PHYVER_VERSION);
  2444. switch (phy_type) {
  2445. case B43legacy_PHYTYPE_B:
  2446. if (phy_rev != 2 && phy_rev != 4
  2447. && phy_rev != 6 && phy_rev != 7)
  2448. unsupported = 1;
  2449. break;
  2450. case B43legacy_PHYTYPE_G:
  2451. if (phy_rev > 8)
  2452. unsupported = 1;
  2453. break;
  2454. default:
  2455. unsupported = 1;
  2456. };
  2457. if (unsupported) {
  2458. b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
  2459. "(Analog %u, Type %u, Revision %u)\n",
  2460. analog_type, phy_type, phy_rev);
  2461. return -EOPNOTSUPP;
  2462. }
  2463. b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
  2464. analog_type, phy_type, phy_rev);
  2465. /* Get RADIO versioning */
  2466. if (dev->dev->bus->chip_id == 0x4317) {
  2467. if (dev->dev->bus->chip_rev == 0)
  2468. tmp = 0x3205017F;
  2469. else if (dev->dev->bus->chip_rev == 1)
  2470. tmp = 0x4205017F;
  2471. else
  2472. tmp = 0x5205017F;
  2473. } else {
  2474. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2475. B43legacy_RADIOCTL_ID);
  2476. tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
  2477. tmp <<= 16;
  2478. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2479. B43legacy_RADIOCTL_ID);
  2480. tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
  2481. }
  2482. radio_manuf = (tmp & 0x00000FFF);
  2483. radio_ver = (tmp & 0x0FFFF000) >> 12;
  2484. radio_rev = (tmp & 0xF0000000) >> 28;
  2485. switch (phy_type) {
  2486. case B43legacy_PHYTYPE_B:
  2487. if ((radio_ver & 0xFFF0) != 0x2050)
  2488. unsupported = 1;
  2489. break;
  2490. case B43legacy_PHYTYPE_G:
  2491. if (radio_ver != 0x2050)
  2492. unsupported = 1;
  2493. break;
  2494. default:
  2495. B43legacy_BUG_ON(1);
  2496. }
  2497. if (unsupported) {
  2498. b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
  2499. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  2500. radio_manuf, radio_ver, radio_rev);
  2501. return -EOPNOTSUPP;
  2502. }
  2503. b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
  2504. " Revision %u\n", radio_manuf, radio_ver, radio_rev);
  2505. phy->radio_manuf = radio_manuf;
  2506. phy->radio_ver = radio_ver;
  2507. phy->radio_rev = radio_rev;
  2508. phy->analog = analog_type;
  2509. phy->type = phy_type;
  2510. phy->rev = phy_rev;
  2511. return 0;
  2512. }
  2513. static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
  2514. struct b43legacy_phy *phy)
  2515. {
  2516. struct b43legacy_lopair *lo;
  2517. int i;
  2518. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2519. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2520. /* Assume the radio is enabled. If it's not enabled, the state will
  2521. * immediately get fixed on the first periodic work run. */
  2522. dev->radio_hw_enable = 1;
  2523. phy->savedpctlreg = 0xFFFF;
  2524. phy->aci_enable = 0;
  2525. phy->aci_wlan_automatic = 0;
  2526. phy->aci_hw_rssi = 0;
  2527. lo = phy->_lo_pairs;
  2528. if (lo)
  2529. memset(lo, 0, sizeof(struct b43legacy_lopair) *
  2530. B43legacy_LO_COUNT);
  2531. phy->max_lb_gain = 0;
  2532. phy->trsw_rx_gain = 0;
  2533. /* Set default attenuation values. */
  2534. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2535. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2536. phy->txctl1 = b43legacy_default_txctl1(dev);
  2537. phy->txpwr_offset = 0;
  2538. /* NRSSI */
  2539. phy->nrssislope = 0;
  2540. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2541. phy->nrssi[i] = -1000;
  2542. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2543. phy->nrssi_lt[i] = i;
  2544. phy->lofcal = 0xFFFF;
  2545. phy->initval = 0xFFFF;
  2546. phy->interfmode = B43legacy_INTERFMODE_NONE;
  2547. phy->channel = 0xFF;
  2548. }
  2549. static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
  2550. {
  2551. /* Flags */
  2552. dev->reg124_set_0x4 = 0;
  2553. /* Stats */
  2554. memset(&dev->stats, 0, sizeof(dev->stats));
  2555. setup_struct_phy_for_init(dev, &dev->phy);
  2556. /* IRQ related flags */
  2557. dev->irq_reason = 0;
  2558. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  2559. dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
  2560. dev->mac_suspended = 1;
  2561. /* Noise calculation context */
  2562. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  2563. }
  2564. static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
  2565. {
  2566. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2567. struct ssb_bus *bus = dev->dev->bus;
  2568. u32 tmp;
  2569. if (bus->pcicore.dev &&
  2570. bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
  2571. bus->pcicore.dev->id.revision <= 5) {
  2572. /* IMCFGLO timeouts workaround. */
  2573. tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
  2574. tmp &= ~SSB_IMCFGLO_REQTO;
  2575. tmp &= ~SSB_IMCFGLO_SERTO;
  2576. switch (bus->bustype) {
  2577. case SSB_BUSTYPE_PCI:
  2578. case SSB_BUSTYPE_PCMCIA:
  2579. tmp |= 0x32;
  2580. break;
  2581. case SSB_BUSTYPE_SSB:
  2582. tmp |= 0x53;
  2583. break;
  2584. }
  2585. ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
  2586. }
  2587. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  2588. }
  2589. /* Write the short and long frame retry limit values. */
  2590. static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
  2591. unsigned int short_retry,
  2592. unsigned int long_retry)
  2593. {
  2594. /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
  2595. * the chip-internal counter. */
  2596. short_retry = min(short_retry, (unsigned int)0xF);
  2597. long_retry = min(long_retry, (unsigned int)0xF);
  2598. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
  2599. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
  2600. }
  2601. /* Shutdown a wireless core */
  2602. /* Locking: wl->mutex */
  2603. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
  2604. {
  2605. struct b43legacy_wl *wl = dev->wl;
  2606. struct b43legacy_phy *phy = &dev->phy;
  2607. u32 macctl;
  2608. B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
  2609. if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
  2610. return;
  2611. b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
  2612. /* Stop the microcode PSM. */
  2613. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  2614. macctl &= ~B43legacy_MACCTL_PSM_RUN;
  2615. macctl |= B43legacy_MACCTL_PSM_JMP0;
  2616. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  2617. mutex_unlock(&wl->mutex);
  2618. /* Must unlock as it would otherwise deadlock. No races here.
  2619. * Cancel possibly pending workqueues. */
  2620. cancel_work_sync(&dev->restart_work);
  2621. mutex_lock(&wl->mutex);
  2622. b43legacy_leds_exit(dev);
  2623. b43legacy_rng_exit(dev->wl);
  2624. b43legacy_pio_free(dev);
  2625. b43legacy_dma_free(dev);
  2626. b43legacy_chip_exit(dev);
  2627. b43legacy_radio_turn_off(dev, 1);
  2628. b43legacy_switch_analog(dev, 0);
  2629. if (phy->dyn_tssi_tbl)
  2630. kfree(phy->tssi2dbm);
  2631. kfree(phy->lo_control);
  2632. phy->lo_control = NULL;
  2633. ssb_device_disable(dev->dev, 0);
  2634. ssb_bus_may_powerdown(dev->dev->bus);
  2635. }
  2636. static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
  2637. {
  2638. struct b43legacy_phy *phy = &dev->phy;
  2639. int i;
  2640. /* Set default attenuation values. */
  2641. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2642. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2643. phy->txctl1 = b43legacy_default_txctl1(dev);
  2644. phy->txctl2 = 0xFFFF;
  2645. phy->txpwr_offset = 0;
  2646. /* NRSSI */
  2647. phy->nrssislope = 0;
  2648. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2649. phy->nrssi[i] = -1000;
  2650. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2651. phy->nrssi_lt[i] = i;
  2652. phy->lofcal = 0xFFFF;
  2653. phy->initval = 0xFFFF;
  2654. phy->aci_enable = 0;
  2655. phy->aci_wlan_automatic = 0;
  2656. phy->aci_hw_rssi = 0;
  2657. phy->antenna_diversity = 0xFFFF;
  2658. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2659. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2660. /* Flags */
  2661. phy->calibrated = 0;
  2662. if (phy->_lo_pairs)
  2663. memset(phy->_lo_pairs, 0,
  2664. sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
  2665. memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
  2666. }
  2667. /* Initialize a wireless core */
  2668. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
  2669. {
  2670. struct b43legacy_wl *wl = dev->wl;
  2671. struct ssb_bus *bus = dev->dev->bus;
  2672. struct b43legacy_phy *phy = &dev->phy;
  2673. struct ssb_sprom *sprom = &dev->dev->bus->sprom;
  2674. int err;
  2675. u32 hf;
  2676. u32 tmp;
  2677. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2678. err = ssb_bus_powerup(bus, 0);
  2679. if (err)
  2680. goto out;
  2681. if (!ssb_device_is_enabled(dev->dev)) {
  2682. tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
  2683. b43legacy_wireless_core_reset(dev, tmp);
  2684. }
  2685. if ((phy->type == B43legacy_PHYTYPE_B) ||
  2686. (phy->type == B43legacy_PHYTYPE_G)) {
  2687. phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
  2688. * B43legacy_LO_COUNT,
  2689. GFP_KERNEL);
  2690. if (!phy->_lo_pairs)
  2691. return -ENOMEM;
  2692. }
  2693. setup_struct_wldev_for_init(dev);
  2694. err = b43legacy_phy_init_tssi2dbm_table(dev);
  2695. if (err)
  2696. goto err_kfree_lo_control;
  2697. /* Enable IRQ routing to this device. */
  2698. ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
  2699. b43legacy_imcfglo_timeouts_workaround(dev);
  2700. prepare_phy_data_for_init(dev);
  2701. b43legacy_phy_calibrate(dev);
  2702. err = b43legacy_chip_init(dev);
  2703. if (err)
  2704. goto err_kfree_tssitbl;
  2705. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2706. B43legacy_SHM_SH_WLCOREREV,
  2707. dev->dev->id.revision);
  2708. hf = b43legacy_hf_read(dev);
  2709. if (phy->type == B43legacy_PHYTYPE_G) {
  2710. hf |= B43legacy_HF_SYMW;
  2711. if (phy->rev == 1)
  2712. hf |= B43legacy_HF_GDCW;
  2713. if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
  2714. hf |= B43legacy_HF_OFDMPABOOST;
  2715. } else if (phy->type == B43legacy_PHYTYPE_B) {
  2716. hf |= B43legacy_HF_SYMW;
  2717. if (phy->rev >= 2 && phy->radio_ver == 0x2050)
  2718. hf &= ~B43legacy_HF_GDCW;
  2719. }
  2720. b43legacy_hf_write(dev, hf);
  2721. b43legacy_set_retry_limits(dev,
  2722. B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
  2723. B43legacy_DEFAULT_LONG_RETRY_LIMIT);
  2724. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2725. 0x0044, 3);
  2726. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2727. 0x0046, 2);
  2728. /* Disable sending probe responses from firmware.
  2729. * Setting the MaxTime to one usec will always trigger
  2730. * a timeout, so we never send any probe resp.
  2731. * A timeout of zero is infinite. */
  2732. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2733. B43legacy_SHM_SH_PRMAXTIME, 1);
  2734. b43legacy_rate_memory_init(dev);
  2735. /* Minimum Contention Window */
  2736. if (phy->type == B43legacy_PHYTYPE_B)
  2737. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2738. 0x0003, 31);
  2739. else
  2740. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2741. 0x0003, 15);
  2742. /* Maximum Contention Window */
  2743. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2744. 0x0004, 1023);
  2745. do {
  2746. if (b43legacy_using_pio(dev))
  2747. err = b43legacy_pio_init(dev);
  2748. else {
  2749. err = b43legacy_dma_init(dev);
  2750. if (!err)
  2751. b43legacy_qos_init(dev);
  2752. }
  2753. } while (err == -EAGAIN);
  2754. if (err)
  2755. goto err_chip_exit;
  2756. b43legacy_write16(dev, 0x0612, 0x0050);
  2757. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0416, 0x0050);
  2758. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0414, 0x01F4);
  2759. ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
  2760. b43legacy_upload_card_macaddress(dev);
  2761. b43legacy_security_init(dev);
  2762. b43legacy_rng_init(wl);
  2763. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2764. b43legacy_leds_init(dev);
  2765. out:
  2766. return err;
  2767. err_chip_exit:
  2768. b43legacy_chip_exit(dev);
  2769. err_kfree_tssitbl:
  2770. if (phy->dyn_tssi_tbl)
  2771. kfree(phy->tssi2dbm);
  2772. err_kfree_lo_control:
  2773. kfree(phy->lo_control);
  2774. phy->lo_control = NULL;
  2775. ssb_bus_may_powerdown(bus);
  2776. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2777. return err;
  2778. }
  2779. static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
  2780. struct ieee80211_if_init_conf *conf)
  2781. {
  2782. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2783. struct b43legacy_wldev *dev;
  2784. unsigned long flags;
  2785. int err = -EOPNOTSUPP;
  2786. /* TODO: allow WDS/AP devices to coexist */
  2787. if (conf->type != IEEE80211_IF_TYPE_AP &&
  2788. conf->type != IEEE80211_IF_TYPE_STA &&
  2789. conf->type != IEEE80211_IF_TYPE_WDS &&
  2790. conf->type != IEEE80211_IF_TYPE_IBSS)
  2791. return -EOPNOTSUPP;
  2792. mutex_lock(&wl->mutex);
  2793. if (wl->operating)
  2794. goto out_mutex_unlock;
  2795. b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
  2796. dev = wl->current_dev;
  2797. wl->operating = 1;
  2798. wl->vif = conf->vif;
  2799. wl->if_type = conf->type;
  2800. memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
  2801. spin_lock_irqsave(&wl->irq_lock, flags);
  2802. b43legacy_adjust_opmode(dev);
  2803. b43legacy_upload_card_macaddress(dev);
  2804. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2805. err = 0;
  2806. out_mutex_unlock:
  2807. mutex_unlock(&wl->mutex);
  2808. return err;
  2809. }
  2810. static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
  2811. struct ieee80211_if_init_conf *conf)
  2812. {
  2813. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2814. struct b43legacy_wldev *dev = wl->current_dev;
  2815. unsigned long flags;
  2816. b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
  2817. mutex_lock(&wl->mutex);
  2818. B43legacy_WARN_ON(!wl->operating);
  2819. B43legacy_WARN_ON(wl->vif != conf->vif);
  2820. wl->vif = NULL;
  2821. wl->operating = 0;
  2822. spin_lock_irqsave(&wl->irq_lock, flags);
  2823. b43legacy_adjust_opmode(dev);
  2824. memset(wl->mac_addr, 0, ETH_ALEN);
  2825. b43legacy_upload_card_macaddress(dev);
  2826. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2827. mutex_unlock(&wl->mutex);
  2828. }
  2829. static int b43legacy_op_start(struct ieee80211_hw *hw)
  2830. {
  2831. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2832. struct b43legacy_wldev *dev = wl->current_dev;
  2833. int did_init = 0;
  2834. int err = 0;
  2835. bool do_rfkill_exit = 0;
  2836. /* First register RFkill.
  2837. * LEDs that are registered later depend on it. */
  2838. b43legacy_rfkill_init(dev);
  2839. /* Kill all old instance specific information to make sure
  2840. * the card won't use it in the short timeframe between start
  2841. * and mac80211 reconfiguring it. */
  2842. memset(wl->bssid, 0, ETH_ALEN);
  2843. memset(wl->mac_addr, 0, ETH_ALEN);
  2844. wl->filter_flags = 0;
  2845. mutex_lock(&wl->mutex);
  2846. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
  2847. err = b43legacy_wireless_core_init(dev);
  2848. if (err) {
  2849. do_rfkill_exit = 1;
  2850. goto out_mutex_unlock;
  2851. }
  2852. did_init = 1;
  2853. }
  2854. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2855. err = b43legacy_wireless_core_start(dev);
  2856. if (err) {
  2857. if (did_init)
  2858. b43legacy_wireless_core_exit(dev);
  2859. do_rfkill_exit = 1;
  2860. goto out_mutex_unlock;
  2861. }
  2862. }
  2863. out_mutex_unlock:
  2864. mutex_unlock(&wl->mutex);
  2865. if (do_rfkill_exit)
  2866. b43legacy_rfkill_exit(dev);
  2867. return err;
  2868. }
  2869. static void b43legacy_op_stop(struct ieee80211_hw *hw)
  2870. {
  2871. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2872. struct b43legacy_wldev *dev = wl->current_dev;
  2873. b43legacy_rfkill_exit(dev);
  2874. mutex_lock(&wl->mutex);
  2875. if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
  2876. b43legacy_wireless_core_stop(dev);
  2877. b43legacy_wireless_core_exit(dev);
  2878. mutex_unlock(&wl->mutex);
  2879. }
  2880. static int b43legacy_op_set_retry_limit(struct ieee80211_hw *hw,
  2881. u32 short_retry_limit,
  2882. u32 long_retry_limit)
  2883. {
  2884. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2885. struct b43legacy_wldev *dev;
  2886. int err = 0;
  2887. mutex_lock(&wl->mutex);
  2888. dev = wl->current_dev;
  2889. if (unlikely(!dev ||
  2890. (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED))) {
  2891. err = -ENODEV;
  2892. goto out_unlock;
  2893. }
  2894. b43legacy_set_retry_limits(dev, short_retry_limit, long_retry_limit);
  2895. out_unlock:
  2896. mutex_unlock(&wl->mutex);
  2897. return err;
  2898. }
  2899. static const struct ieee80211_ops b43legacy_hw_ops = {
  2900. .tx = b43legacy_op_tx,
  2901. .conf_tx = b43legacy_op_conf_tx,
  2902. .add_interface = b43legacy_op_add_interface,
  2903. .remove_interface = b43legacy_op_remove_interface,
  2904. .config = b43legacy_op_dev_config,
  2905. .config_interface = b43legacy_op_config_interface,
  2906. .configure_filter = b43legacy_op_configure_filter,
  2907. .get_stats = b43legacy_op_get_stats,
  2908. .get_tx_stats = b43legacy_op_get_tx_stats,
  2909. .start = b43legacy_op_start,
  2910. .stop = b43legacy_op_stop,
  2911. .set_retry_limit = b43legacy_op_set_retry_limit,
  2912. };
  2913. /* Hard-reset the chip. Do not call this directly.
  2914. * Use b43legacy_controller_restart()
  2915. */
  2916. static void b43legacy_chip_reset(struct work_struct *work)
  2917. {
  2918. struct b43legacy_wldev *dev =
  2919. container_of(work, struct b43legacy_wldev, restart_work);
  2920. struct b43legacy_wl *wl = dev->wl;
  2921. int err = 0;
  2922. int prev_status;
  2923. mutex_lock(&wl->mutex);
  2924. prev_status = b43legacy_status(dev);
  2925. /* Bring the device down... */
  2926. if (prev_status >= B43legacy_STAT_STARTED)
  2927. b43legacy_wireless_core_stop(dev);
  2928. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2929. b43legacy_wireless_core_exit(dev);
  2930. /* ...and up again. */
  2931. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2932. err = b43legacy_wireless_core_init(dev);
  2933. if (err)
  2934. goto out;
  2935. }
  2936. if (prev_status >= B43legacy_STAT_STARTED) {
  2937. err = b43legacy_wireless_core_start(dev);
  2938. if (err) {
  2939. b43legacy_wireless_core_exit(dev);
  2940. goto out;
  2941. }
  2942. }
  2943. out:
  2944. mutex_unlock(&wl->mutex);
  2945. if (err)
  2946. b43legacyerr(wl, "Controller restart FAILED\n");
  2947. else
  2948. b43legacyinfo(wl, "Controller restarted\n");
  2949. }
  2950. static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
  2951. int have_bphy,
  2952. int have_gphy)
  2953. {
  2954. struct ieee80211_hw *hw = dev->wl->hw;
  2955. struct ieee80211_hw_mode *mode;
  2956. struct b43legacy_phy *phy = &dev->phy;
  2957. int cnt = 0;
  2958. int err;
  2959. phy->possible_phymodes = 0;
  2960. for (; 1; cnt++) {
  2961. if (have_bphy) {
  2962. B43legacy_WARN_ON(cnt >= B43legacy_MAX_PHYHWMODES);
  2963. mode = &phy->hwmodes[cnt];
  2964. mode->mode = MODE_IEEE80211B;
  2965. mode->num_channels = b43legacy_bg_chantable_size;
  2966. mode->channels = b43legacy_bg_chantable;
  2967. mode->num_rates = b43legacy_b_ratetable_size;
  2968. mode->rates = b43legacy_b_ratetable;
  2969. err = ieee80211_register_hwmode(hw, mode);
  2970. if (err)
  2971. return err;
  2972. phy->possible_phymodes |= B43legacy_PHYMODE_B;
  2973. have_bphy = 0;
  2974. continue;
  2975. }
  2976. if (have_gphy) {
  2977. B43legacy_WARN_ON(cnt >= B43legacy_MAX_PHYHWMODES);
  2978. mode = &phy->hwmodes[cnt];
  2979. mode->mode = MODE_IEEE80211G;
  2980. mode->num_channels = b43legacy_bg_chantable_size;
  2981. mode->channels = b43legacy_bg_chantable;
  2982. mode->num_rates = b43legacy_g_ratetable_size;
  2983. mode->rates = b43legacy_g_ratetable;
  2984. err = ieee80211_register_hwmode(hw, mode);
  2985. if (err)
  2986. return err;
  2987. phy->possible_phymodes |= B43legacy_PHYMODE_G;
  2988. have_gphy = 0;
  2989. continue;
  2990. }
  2991. break;
  2992. }
  2993. return 0;
  2994. }
  2995. static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
  2996. {
  2997. /* We release firmware that late to not be required to re-request
  2998. * is all the time when we reinit the core. */
  2999. b43legacy_release_firmware(dev);
  3000. }
  3001. static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
  3002. {
  3003. struct b43legacy_wl *wl = dev->wl;
  3004. struct ssb_bus *bus = dev->dev->bus;
  3005. struct pci_dev *pdev = bus->host_pci;
  3006. int err;
  3007. int have_bphy = 0;
  3008. int have_gphy = 0;
  3009. u32 tmp;
  3010. /* Do NOT do any device initialization here.
  3011. * Do it in wireless_core_init() instead.
  3012. * This function is for gathering basic information about the HW, only.
  3013. * Also some structs may be set up here. But most likely you want to
  3014. * have that in core_init(), too.
  3015. */
  3016. err = ssb_bus_powerup(bus, 0);
  3017. if (err) {
  3018. b43legacyerr(wl, "Bus powerup failed\n");
  3019. goto out;
  3020. }
  3021. /* Get the PHY type. */
  3022. if (dev->dev->id.revision >= 5) {
  3023. u32 tmshigh;
  3024. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  3025. have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
  3026. if (!have_gphy)
  3027. have_bphy = 1;
  3028. } else if (dev->dev->id.revision == 4)
  3029. have_gphy = 1;
  3030. else
  3031. have_bphy = 1;
  3032. dev->phy.gmode = (have_gphy || have_bphy);
  3033. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3034. b43legacy_wireless_core_reset(dev, tmp);
  3035. err = b43legacy_phy_versioning(dev);
  3036. if (err)
  3037. goto err_powerdown;
  3038. /* Check if this device supports multiband. */
  3039. if (!pdev ||
  3040. (pdev->device != 0x4312 &&
  3041. pdev->device != 0x4319 &&
  3042. pdev->device != 0x4324)) {
  3043. /* No multiband support. */
  3044. have_bphy = 0;
  3045. have_gphy = 0;
  3046. switch (dev->phy.type) {
  3047. case B43legacy_PHYTYPE_B:
  3048. have_bphy = 1;
  3049. break;
  3050. case B43legacy_PHYTYPE_G:
  3051. have_gphy = 1;
  3052. break;
  3053. default:
  3054. B43legacy_BUG_ON(1);
  3055. }
  3056. }
  3057. dev->phy.gmode = (have_gphy || have_bphy);
  3058. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3059. b43legacy_wireless_core_reset(dev, tmp);
  3060. err = b43legacy_validate_chipaccess(dev);
  3061. if (err)
  3062. goto err_powerdown;
  3063. err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
  3064. if (err)
  3065. goto err_powerdown;
  3066. /* Now set some default "current_dev" */
  3067. if (!wl->current_dev)
  3068. wl->current_dev = dev;
  3069. INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
  3070. b43legacy_radio_turn_off(dev, 1);
  3071. b43legacy_switch_analog(dev, 0);
  3072. ssb_device_disable(dev->dev, 0);
  3073. ssb_bus_may_powerdown(bus);
  3074. out:
  3075. return err;
  3076. err_powerdown:
  3077. ssb_bus_may_powerdown(bus);
  3078. return err;
  3079. }
  3080. static void b43legacy_one_core_detach(struct ssb_device *dev)
  3081. {
  3082. struct b43legacy_wldev *wldev;
  3083. struct b43legacy_wl *wl;
  3084. wldev = ssb_get_drvdata(dev);
  3085. wl = wldev->wl;
  3086. cancel_work_sync(&wldev->restart_work);
  3087. b43legacy_debugfs_remove_device(wldev);
  3088. b43legacy_wireless_core_detach(wldev);
  3089. list_del(&wldev->list);
  3090. wl->nr_devs--;
  3091. ssb_set_drvdata(dev, NULL);
  3092. kfree(wldev);
  3093. }
  3094. static int b43legacy_one_core_attach(struct ssb_device *dev,
  3095. struct b43legacy_wl *wl)
  3096. {
  3097. struct b43legacy_wldev *wldev;
  3098. struct pci_dev *pdev;
  3099. int err = -ENOMEM;
  3100. if (!list_empty(&wl->devlist)) {
  3101. /* We are not the first core on this chip. */
  3102. pdev = dev->bus->host_pci;
  3103. /* Only special chips support more than one wireless
  3104. * core, although some of the other chips have more than
  3105. * one wireless core as well. Check for this and
  3106. * bail out early.
  3107. */
  3108. if (!pdev ||
  3109. ((pdev->device != 0x4321) &&
  3110. (pdev->device != 0x4313) &&
  3111. (pdev->device != 0x431A))) {
  3112. b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
  3113. return -ENODEV;
  3114. }
  3115. }
  3116. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  3117. if (!wldev)
  3118. goto out;
  3119. wldev->dev = dev;
  3120. wldev->wl = wl;
  3121. b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
  3122. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  3123. tasklet_init(&wldev->isr_tasklet,
  3124. (void (*)(unsigned long))b43legacy_interrupt_tasklet,
  3125. (unsigned long)wldev);
  3126. if (modparam_pio)
  3127. wldev->__using_pio = 1;
  3128. INIT_LIST_HEAD(&wldev->list);
  3129. err = b43legacy_wireless_core_attach(wldev);
  3130. if (err)
  3131. goto err_kfree_wldev;
  3132. list_add(&wldev->list, &wl->devlist);
  3133. wl->nr_devs++;
  3134. ssb_set_drvdata(dev, wldev);
  3135. b43legacy_debugfs_add_device(wldev);
  3136. out:
  3137. return err;
  3138. err_kfree_wldev:
  3139. kfree(wldev);
  3140. return err;
  3141. }
  3142. static void b43legacy_sprom_fixup(struct ssb_bus *bus)
  3143. {
  3144. /* boardflags workarounds */
  3145. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  3146. bus->boardinfo.type == 0x4E &&
  3147. bus->boardinfo.rev > 0x40)
  3148. bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
  3149. }
  3150. static void b43legacy_wireless_exit(struct ssb_device *dev,
  3151. struct b43legacy_wl *wl)
  3152. {
  3153. struct ieee80211_hw *hw = wl->hw;
  3154. ssb_set_devtypedata(dev, NULL);
  3155. ieee80211_free_hw(hw);
  3156. }
  3157. static int b43legacy_wireless_init(struct ssb_device *dev)
  3158. {
  3159. struct ssb_sprom *sprom = &dev->bus->sprom;
  3160. struct ieee80211_hw *hw;
  3161. struct b43legacy_wl *wl;
  3162. int err = -ENOMEM;
  3163. b43legacy_sprom_fixup(dev->bus);
  3164. hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
  3165. if (!hw) {
  3166. b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
  3167. goto out;
  3168. }
  3169. /* fill hw info */
  3170. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  3171. IEEE80211_HW_RX_INCLUDES_FCS;
  3172. hw->max_signal = 100;
  3173. hw->max_rssi = -110;
  3174. hw->max_noise = -110;
  3175. hw->queues = 1; /* FIXME: hardware has more queues */
  3176. SET_IEEE80211_DEV(hw, dev->dev);
  3177. if (is_valid_ether_addr(sprom->et1mac))
  3178. SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
  3179. else
  3180. SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
  3181. /* Get and initialize struct b43legacy_wl */
  3182. wl = hw_to_b43legacy_wl(hw);
  3183. memset(wl, 0, sizeof(*wl));
  3184. wl->hw = hw;
  3185. spin_lock_init(&wl->irq_lock);
  3186. spin_lock_init(&wl->leds_lock);
  3187. mutex_init(&wl->mutex);
  3188. INIT_LIST_HEAD(&wl->devlist);
  3189. ssb_set_devtypedata(dev, wl);
  3190. b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
  3191. err = 0;
  3192. out:
  3193. return err;
  3194. }
  3195. static int b43legacy_probe(struct ssb_device *dev,
  3196. const struct ssb_device_id *id)
  3197. {
  3198. struct b43legacy_wl *wl;
  3199. int err;
  3200. int first = 0;
  3201. wl = ssb_get_devtypedata(dev);
  3202. if (!wl) {
  3203. /* Probing the first core - setup common struct b43legacy_wl */
  3204. first = 1;
  3205. err = b43legacy_wireless_init(dev);
  3206. if (err)
  3207. goto out;
  3208. wl = ssb_get_devtypedata(dev);
  3209. B43legacy_WARN_ON(!wl);
  3210. }
  3211. err = b43legacy_one_core_attach(dev, wl);
  3212. if (err)
  3213. goto err_wireless_exit;
  3214. if (first) {
  3215. err = ieee80211_register_hw(wl->hw);
  3216. if (err)
  3217. goto err_one_core_detach;
  3218. }
  3219. out:
  3220. return err;
  3221. err_one_core_detach:
  3222. b43legacy_one_core_detach(dev);
  3223. err_wireless_exit:
  3224. if (first)
  3225. b43legacy_wireless_exit(dev, wl);
  3226. return err;
  3227. }
  3228. static void b43legacy_remove(struct ssb_device *dev)
  3229. {
  3230. struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
  3231. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3232. B43legacy_WARN_ON(!wl);
  3233. if (wl->current_dev == wldev)
  3234. ieee80211_unregister_hw(wl->hw);
  3235. b43legacy_one_core_detach(dev);
  3236. if (list_empty(&wl->devlist))
  3237. /* Last core on the chip unregistered.
  3238. * We can destroy common struct b43legacy_wl.
  3239. */
  3240. b43legacy_wireless_exit(dev, wl);
  3241. }
  3242. /* Perform a hardware reset. This can be called from any context. */
  3243. void b43legacy_controller_restart(struct b43legacy_wldev *dev,
  3244. const char *reason)
  3245. {
  3246. /* Must avoid requeueing, if we are in shutdown. */
  3247. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
  3248. return;
  3249. b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
  3250. queue_work(dev->wl->hw->workqueue, &dev->restart_work);
  3251. }
  3252. #ifdef CONFIG_PM
  3253. static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
  3254. {
  3255. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3256. struct b43legacy_wl *wl = wldev->wl;
  3257. b43legacydbg(wl, "Suspending...\n");
  3258. mutex_lock(&wl->mutex);
  3259. wldev->suspend_init_status = b43legacy_status(wldev);
  3260. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
  3261. b43legacy_wireless_core_stop(wldev);
  3262. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
  3263. b43legacy_wireless_core_exit(wldev);
  3264. mutex_unlock(&wl->mutex);
  3265. b43legacydbg(wl, "Device suspended.\n");
  3266. return 0;
  3267. }
  3268. static int b43legacy_resume(struct ssb_device *dev)
  3269. {
  3270. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3271. struct b43legacy_wl *wl = wldev->wl;
  3272. int err = 0;
  3273. b43legacydbg(wl, "Resuming...\n");
  3274. mutex_lock(&wl->mutex);
  3275. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
  3276. err = b43legacy_wireless_core_init(wldev);
  3277. if (err) {
  3278. b43legacyerr(wl, "Resume failed at core init\n");
  3279. goto out;
  3280. }
  3281. }
  3282. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
  3283. err = b43legacy_wireless_core_start(wldev);
  3284. if (err) {
  3285. b43legacy_wireless_core_exit(wldev);
  3286. b43legacyerr(wl, "Resume failed at core start\n");
  3287. goto out;
  3288. }
  3289. }
  3290. mutex_unlock(&wl->mutex);
  3291. b43legacydbg(wl, "Device resumed.\n");
  3292. out:
  3293. return err;
  3294. }
  3295. #else /* CONFIG_PM */
  3296. # define b43legacy_suspend NULL
  3297. # define b43legacy_resume NULL
  3298. #endif /* CONFIG_PM */
  3299. static struct ssb_driver b43legacy_ssb_driver = {
  3300. .name = KBUILD_MODNAME,
  3301. .id_table = b43legacy_ssb_tbl,
  3302. .probe = b43legacy_probe,
  3303. .remove = b43legacy_remove,
  3304. .suspend = b43legacy_suspend,
  3305. .resume = b43legacy_resume,
  3306. };
  3307. static void b43legacy_print_driverinfo(void)
  3308. {
  3309. const char *feat_pci = "", *feat_leds = "", *feat_rfkill = "",
  3310. *feat_pio = "", *feat_dma = "";
  3311. #ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
  3312. feat_pci = "P";
  3313. #endif
  3314. #ifdef CONFIG_B43LEGACY_LEDS
  3315. feat_leds = "L";
  3316. #endif
  3317. #ifdef CONFIG_B43LEGACY_RFKILL
  3318. feat_rfkill = "R";
  3319. #endif
  3320. #ifdef CONFIG_B43LEGACY_PIO
  3321. feat_pio = "I";
  3322. #endif
  3323. #ifdef CONFIG_B43LEGACY_DMA
  3324. feat_dma = "D";
  3325. #endif
  3326. printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
  3327. "[ Features: %s%s%s%s%s, Firmware-ID: "
  3328. B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
  3329. feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma);
  3330. }
  3331. static int __init b43legacy_init(void)
  3332. {
  3333. int err;
  3334. b43legacy_debugfs_init();
  3335. err = ssb_driver_register(&b43legacy_ssb_driver);
  3336. if (err)
  3337. goto err_dfs_exit;
  3338. b43legacy_print_driverinfo();
  3339. return err;
  3340. err_dfs_exit:
  3341. b43legacy_debugfs_exit();
  3342. return err;
  3343. }
  3344. static void __exit b43legacy_exit(void)
  3345. {
  3346. ssb_driver_unregister(&b43legacy_ssb_driver);
  3347. b43legacy_debugfs_exit();
  3348. }
  3349. module_init(b43legacy_init)
  3350. module_exit(b43legacy_exit)