qla_os.c 109 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. /*
  20. * Driver version
  21. */
  22. char qla2x00_version_str[40];
  23. static int apidev_major;
  24. /*
  25. * SRB allocation cache
  26. */
  27. static struct kmem_cache *srb_cachep;
  28. /*
  29. * CT6 CTX allocation cache
  30. */
  31. static struct kmem_cache *ctx_cachep;
  32. int ql2xlogintimeout = 20;
  33. module_param(ql2xlogintimeout, int, S_IRUGO);
  34. MODULE_PARM_DESC(ql2xlogintimeout,
  35. "Login timeout value in seconds.");
  36. int qlport_down_retry;
  37. module_param(qlport_down_retry, int, S_IRUGO);
  38. MODULE_PARM_DESC(qlport_down_retry,
  39. "Maximum number of command retries to a port that returns "
  40. "a PORT-DOWN status.");
  41. int ql2xplogiabsentdevice;
  42. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  43. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  44. "Option to enable PLOGI to devices that are not present after "
  45. "a Fabric scan. This is needed for several broken switches. "
  46. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  47. int ql2xloginretrycount = 0;
  48. module_param(ql2xloginretrycount, int, S_IRUGO);
  49. MODULE_PARM_DESC(ql2xloginretrycount,
  50. "Specify an alternate value for the NVRAM login retry count.");
  51. int ql2xallocfwdump = 1;
  52. module_param(ql2xallocfwdump, int, S_IRUGO);
  53. MODULE_PARM_DESC(ql2xallocfwdump,
  54. "Option to enable allocation of memory for a firmware dump "
  55. "during HBA initialization. Memory allocation requirements "
  56. "vary by ISP type. Default is 1 - allocate memory.");
  57. int ql2xextended_error_logging;
  58. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  59. MODULE_PARM_DESC(ql2xextended_error_logging,
  60. "Option to enable extended error logging, "
  61. "Default is 0 - no logging. 1 - log errors.");
  62. int ql2xshiftctondsd = 6;
  63. module_param(ql2xshiftctondsd, int, S_IRUGO);
  64. MODULE_PARM_DESC(ql2xshiftctondsd,
  65. "Set to control shifting of command type processing "
  66. "based on total number of SG elements.");
  67. static void qla2x00_free_device(scsi_qla_host_t *);
  68. int ql2xfdmienable=1;
  69. module_param(ql2xfdmienable, int, S_IRUGO);
  70. MODULE_PARM_DESC(ql2xfdmienable,
  71. "Enables FDMI registrations. "
  72. "0 - no FDMI. Default is 1 - perform FDMI.");
  73. #define MAX_Q_DEPTH 32
  74. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  75. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(ql2xmaxqdepth,
  77. "Maximum queue depth to report for target devices.");
  78. /* Do not change the value of this after module load */
  79. int ql2xenabledif = 1;
  80. module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(ql2xenabledif,
  82. " Enable T10-CRC-DIF "
  83. " Default is 0 - No DIF Support. 1 - Enable it");
  84. int ql2xenablehba_err_chk;
  85. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  86. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  87. " Enable T10-CRC-DIF Error isolation by HBA"
  88. " Default is 0 - Error isolation disabled, 1 - Enable it");
  89. int ql2xiidmaenable=1;
  90. module_param(ql2xiidmaenable, int, S_IRUGO);
  91. MODULE_PARM_DESC(ql2xiidmaenable,
  92. "Enables iIDMA settings "
  93. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  94. int ql2xmaxqueues = 1;
  95. module_param(ql2xmaxqueues, int, S_IRUGO);
  96. MODULE_PARM_DESC(ql2xmaxqueues,
  97. "Enables MQ settings "
  98. "Default is 1 for single queue. Set it to number "
  99. "of queues in MQ mode.");
  100. int ql2xmultique_tag;
  101. module_param(ql2xmultique_tag, int, S_IRUGO);
  102. MODULE_PARM_DESC(ql2xmultique_tag,
  103. "Enables CPU affinity settings for the driver "
  104. "Default is 0 for no affinity of request and response IO. "
  105. "Set it to 1 to turn on the cpu affinity.");
  106. int ql2xfwloadbin;
  107. module_param(ql2xfwloadbin, int, S_IRUGO);
  108. MODULE_PARM_DESC(ql2xfwloadbin,
  109. "Option to specify location from which to load ISP firmware:\n"
  110. " 2 -- load firmware via the request_firmware() (hotplug)\n"
  111. " interface.\n"
  112. " 1 -- load firmware from flash.\n"
  113. " 0 -- use default semantics.\n");
  114. int ql2xetsenable;
  115. module_param(ql2xetsenable, int, S_IRUGO);
  116. MODULE_PARM_DESC(ql2xetsenable,
  117. "Enables firmware ETS burst."
  118. "Default is 0 - skip ETS enablement.");
  119. int ql2xdbwr = 1;
  120. module_param(ql2xdbwr, int, S_IRUGO);
  121. MODULE_PARM_DESC(ql2xdbwr,
  122. "Option to specify scheme for request queue posting\n"
  123. " 0 -- Regular doorbell.\n"
  124. " 1 -- CAMRAM doorbell (faster).\n");
  125. int ql2xtargetreset = 1;
  126. module_param(ql2xtargetreset, int, S_IRUGO);
  127. MODULE_PARM_DESC(ql2xtargetreset,
  128. "Enable target reset."
  129. "Default is 1 - use hw defaults.");
  130. int ql2xgffidenable;
  131. module_param(ql2xgffidenable, int, S_IRUGO);
  132. MODULE_PARM_DESC(ql2xgffidenable,
  133. "Enables GFF_ID checks of port type. "
  134. "Default is 0 - Do not use GFF_ID information.");
  135. int ql2xasynctmfenable;
  136. module_param(ql2xasynctmfenable, int, S_IRUGO);
  137. MODULE_PARM_DESC(ql2xasynctmfenable,
  138. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  139. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  140. /*
  141. * SCSI host template entry points
  142. */
  143. static int qla2xxx_slave_configure(struct scsi_device * device);
  144. static int qla2xxx_slave_alloc(struct scsi_device *);
  145. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  146. static void qla2xxx_scan_start(struct Scsi_Host *);
  147. static void qla2xxx_slave_destroy(struct scsi_device *);
  148. static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  149. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  150. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  151. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  152. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  153. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  154. static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
  155. static int qla2x00_change_queue_type(struct scsi_device *, int);
  156. struct scsi_host_template qla2xxx_driver_template = {
  157. .module = THIS_MODULE,
  158. .name = QLA2XXX_DRIVER_NAME,
  159. .queuecommand = qla2xxx_queuecommand,
  160. .eh_abort_handler = qla2xxx_eh_abort,
  161. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  162. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  163. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  164. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  165. .slave_configure = qla2xxx_slave_configure,
  166. .slave_alloc = qla2xxx_slave_alloc,
  167. .slave_destroy = qla2xxx_slave_destroy,
  168. .scan_finished = qla2xxx_scan_finished,
  169. .scan_start = qla2xxx_scan_start,
  170. .change_queue_depth = qla2x00_change_queue_depth,
  171. .change_queue_type = qla2x00_change_queue_type,
  172. .this_id = -1,
  173. .cmd_per_lun = 3,
  174. .use_clustering = ENABLE_CLUSTERING,
  175. .sg_tablesize = SG_ALL,
  176. .max_sectors = 0xFFFF,
  177. .shost_attrs = qla2x00_host_attrs,
  178. };
  179. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  180. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  181. /* TODO Convert to inlines
  182. *
  183. * Timer routines
  184. */
  185. __inline__ void
  186. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  187. {
  188. init_timer(&vha->timer);
  189. vha->timer.expires = jiffies + interval * HZ;
  190. vha->timer.data = (unsigned long)vha;
  191. vha->timer.function = (void (*)(unsigned long))func;
  192. add_timer(&vha->timer);
  193. vha->timer_active = 1;
  194. }
  195. static inline void
  196. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  197. {
  198. /* Currently used for 82XX only. */
  199. if (vha->device_flags & DFLG_DEV_FAILED)
  200. return;
  201. mod_timer(&vha->timer, jiffies + interval * HZ);
  202. }
  203. static __inline__ void
  204. qla2x00_stop_timer(scsi_qla_host_t *vha)
  205. {
  206. del_timer_sync(&vha->timer);
  207. vha->timer_active = 0;
  208. }
  209. static int qla2x00_do_dpc(void *data);
  210. static void qla2x00_rst_aen(scsi_qla_host_t *);
  211. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  212. struct req_que **, struct rsp_que **);
  213. static void qla2x00_free_fw_dump(struct qla_hw_data *);
  214. static void qla2x00_mem_free(struct qla_hw_data *);
  215. static void qla2x00_sp_free_dma(srb_t *);
  216. /* -------------------------------------------------------------------------- */
  217. static int qla2x00_alloc_queues(struct qla_hw_data *ha)
  218. {
  219. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  220. GFP_KERNEL);
  221. if (!ha->req_q_map) {
  222. qla_printk(KERN_WARNING, ha,
  223. "Unable to allocate memory for request queue ptrs\n");
  224. goto fail_req_map;
  225. }
  226. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  227. GFP_KERNEL);
  228. if (!ha->rsp_q_map) {
  229. qla_printk(KERN_WARNING, ha,
  230. "Unable to allocate memory for response queue ptrs\n");
  231. goto fail_rsp_map;
  232. }
  233. set_bit(0, ha->rsp_qid_map);
  234. set_bit(0, ha->req_qid_map);
  235. return 1;
  236. fail_rsp_map:
  237. kfree(ha->req_q_map);
  238. ha->req_q_map = NULL;
  239. fail_req_map:
  240. return -ENOMEM;
  241. }
  242. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  243. {
  244. if (req && req->ring)
  245. dma_free_coherent(&ha->pdev->dev,
  246. (req->length + 1) * sizeof(request_t),
  247. req->ring, req->dma);
  248. kfree(req);
  249. req = NULL;
  250. }
  251. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  252. {
  253. if (rsp && rsp->ring)
  254. dma_free_coherent(&ha->pdev->dev,
  255. (rsp->length + 1) * sizeof(response_t),
  256. rsp->ring, rsp->dma);
  257. kfree(rsp);
  258. rsp = NULL;
  259. }
  260. static void qla2x00_free_queues(struct qla_hw_data *ha)
  261. {
  262. struct req_que *req;
  263. struct rsp_que *rsp;
  264. int cnt;
  265. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  266. req = ha->req_q_map[cnt];
  267. qla2x00_free_req_que(ha, req);
  268. }
  269. kfree(ha->req_q_map);
  270. ha->req_q_map = NULL;
  271. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  272. rsp = ha->rsp_q_map[cnt];
  273. qla2x00_free_rsp_que(ha, rsp);
  274. }
  275. kfree(ha->rsp_q_map);
  276. ha->rsp_q_map = NULL;
  277. }
  278. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  279. {
  280. uint16_t options = 0;
  281. int ques, req, ret;
  282. struct qla_hw_data *ha = vha->hw;
  283. if (!(ha->fw_attributes & BIT_6)) {
  284. qla_printk(KERN_INFO, ha,
  285. "Firmware is not multi-queue capable\n");
  286. goto fail;
  287. }
  288. if (ql2xmultique_tag) {
  289. /* create a request queue for IO */
  290. options |= BIT_7;
  291. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  292. QLA_DEFAULT_QUE_QOS);
  293. if (!req) {
  294. qla_printk(KERN_WARNING, ha,
  295. "Can't create request queue\n");
  296. goto fail;
  297. }
  298. ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
  299. vha->req = ha->req_q_map[req];
  300. options |= BIT_1;
  301. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  302. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  303. if (!ret) {
  304. qla_printk(KERN_WARNING, ha,
  305. "Response Queue create failed\n");
  306. goto fail2;
  307. }
  308. }
  309. ha->flags.cpu_affinity_enabled = 1;
  310. DEBUG2(qla_printk(KERN_INFO, ha,
  311. "CPU affinity mode enabled, no. of response"
  312. " queues:%d, no. of request queues:%d\n",
  313. ha->max_rsp_queues, ha->max_req_queues));
  314. }
  315. return 0;
  316. fail2:
  317. qla25xx_delete_queues(vha);
  318. destroy_workqueue(ha->wq);
  319. ha->wq = NULL;
  320. fail:
  321. ha->mqenable = 0;
  322. kfree(ha->req_q_map);
  323. kfree(ha->rsp_q_map);
  324. ha->max_req_queues = ha->max_rsp_queues = 1;
  325. return 1;
  326. }
  327. static char *
  328. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  329. {
  330. struct qla_hw_data *ha = vha->hw;
  331. static char *pci_bus_modes[] = {
  332. "33", "66", "100", "133",
  333. };
  334. uint16_t pci_bus;
  335. strcpy(str, "PCI");
  336. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  337. if (pci_bus) {
  338. strcat(str, "-X (");
  339. strcat(str, pci_bus_modes[pci_bus]);
  340. } else {
  341. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  342. strcat(str, " (");
  343. strcat(str, pci_bus_modes[pci_bus]);
  344. }
  345. strcat(str, " MHz)");
  346. return (str);
  347. }
  348. static char *
  349. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  350. {
  351. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  352. struct qla_hw_data *ha = vha->hw;
  353. uint32_t pci_bus;
  354. int pcie_reg;
  355. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  356. if (pcie_reg) {
  357. char lwstr[6];
  358. uint16_t pcie_lstat, lspeed, lwidth;
  359. pcie_reg += 0x12;
  360. pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
  361. lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
  362. lwidth = (pcie_lstat &
  363. (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
  364. strcpy(str, "PCIe (");
  365. if (lspeed == 1)
  366. strcat(str, "2.5GT/s ");
  367. else if (lspeed == 2)
  368. strcat(str, "5.0GT/s ");
  369. else
  370. strcat(str, "<unknown> ");
  371. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  372. strcat(str, lwstr);
  373. return str;
  374. }
  375. strcpy(str, "PCI");
  376. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  377. if (pci_bus == 0 || pci_bus == 8) {
  378. strcat(str, " (");
  379. strcat(str, pci_bus_modes[pci_bus >> 3]);
  380. } else {
  381. strcat(str, "-X ");
  382. if (pci_bus & BIT_2)
  383. strcat(str, "Mode 2");
  384. else
  385. strcat(str, "Mode 1");
  386. strcat(str, " (");
  387. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  388. }
  389. strcat(str, " MHz)");
  390. return str;
  391. }
  392. static char *
  393. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
  394. {
  395. char un_str[10];
  396. struct qla_hw_data *ha = vha->hw;
  397. sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
  398. ha->fw_minor_version,
  399. ha->fw_subminor_version);
  400. if (ha->fw_attributes & BIT_9) {
  401. strcat(str, "FLX");
  402. return (str);
  403. }
  404. switch (ha->fw_attributes & 0xFF) {
  405. case 0x7:
  406. strcat(str, "EF");
  407. break;
  408. case 0x17:
  409. strcat(str, "TP");
  410. break;
  411. case 0x37:
  412. strcat(str, "IP");
  413. break;
  414. case 0x77:
  415. strcat(str, "VI");
  416. break;
  417. default:
  418. sprintf(un_str, "(%x)", ha->fw_attributes);
  419. strcat(str, un_str);
  420. break;
  421. }
  422. if (ha->fw_attributes & 0x100)
  423. strcat(str, "X");
  424. return (str);
  425. }
  426. static char *
  427. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
  428. {
  429. struct qla_hw_data *ha = vha->hw;
  430. sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
  431. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  432. return str;
  433. }
  434. static inline srb_t *
  435. qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
  436. struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  437. {
  438. srb_t *sp;
  439. struct qla_hw_data *ha = vha->hw;
  440. sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
  441. if (!sp)
  442. return sp;
  443. atomic_set(&sp->ref_count, 1);
  444. sp->fcport = fcport;
  445. sp->cmd = cmd;
  446. sp->flags = 0;
  447. CMD_SP(cmd) = (void *)sp;
  448. cmd->scsi_done = done;
  449. sp->ctx = NULL;
  450. return sp;
  451. }
  452. static int
  453. qla2xxx_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  454. {
  455. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  456. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  457. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  458. struct qla_hw_data *ha = vha->hw;
  459. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  460. srb_t *sp;
  461. int rval;
  462. spin_unlock_irq(vha->host->host_lock);
  463. if (ha->flags.eeh_busy) {
  464. if (ha->flags.pci_channel_io_perm_failure)
  465. cmd->result = DID_NO_CONNECT << 16;
  466. else
  467. cmd->result = DID_REQUEUE << 16;
  468. goto qc24_fail_command;
  469. }
  470. rval = fc_remote_port_chkready(rport);
  471. if (rval) {
  472. cmd->result = rval;
  473. goto qc24_fail_command;
  474. }
  475. if (!vha->flags.difdix_supported &&
  476. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  477. DEBUG2(qla_printk(KERN_ERR, ha,
  478. "DIF Cap Not Reg, fail DIF capable cmd's:%x\n",
  479. cmd->cmnd[0]));
  480. cmd->result = DID_NO_CONNECT << 16;
  481. goto qc24_fail_command;
  482. }
  483. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  484. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  485. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  486. cmd->result = DID_NO_CONNECT << 16;
  487. goto qc24_fail_command;
  488. }
  489. goto qc24_target_busy;
  490. }
  491. sp = qla2x00_get_new_sp(base_vha, fcport, cmd, done);
  492. if (!sp)
  493. goto qc24_host_busy_lock;
  494. rval = ha->isp_ops->start_scsi(sp);
  495. if (rval != QLA_SUCCESS)
  496. goto qc24_host_busy_free_sp;
  497. spin_lock_irq(vha->host->host_lock);
  498. return 0;
  499. qc24_host_busy_free_sp:
  500. qla2x00_sp_free_dma(sp);
  501. mempool_free(sp, ha->srb_mempool);
  502. qc24_host_busy_lock:
  503. spin_lock_irq(vha->host->host_lock);
  504. return SCSI_MLQUEUE_HOST_BUSY;
  505. qc24_target_busy:
  506. spin_lock_irq(vha->host->host_lock);
  507. return SCSI_MLQUEUE_TARGET_BUSY;
  508. qc24_fail_command:
  509. spin_lock_irq(vha->host->host_lock);
  510. done(cmd);
  511. return 0;
  512. }
  513. static DEF_SCSI_QCMD(qla2xxx_queuecommand)
  514. /*
  515. * qla2x00_eh_wait_on_command
  516. * Waits for the command to be returned by the Firmware for some
  517. * max time.
  518. *
  519. * Input:
  520. * cmd = Scsi Command to wait on.
  521. *
  522. * Return:
  523. * Not Found : 0
  524. * Found : 1
  525. */
  526. static int
  527. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  528. {
  529. #define ABORT_POLLING_PERIOD 1000
  530. #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
  531. unsigned long wait_iter = ABORT_WAIT_ITER;
  532. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  533. struct qla_hw_data *ha = vha->hw;
  534. int ret = QLA_SUCCESS;
  535. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  536. DEBUG17(qla_printk(KERN_WARNING, ha, "return:eh_wait\n"));
  537. return ret;
  538. }
  539. while (CMD_SP(cmd) && wait_iter--) {
  540. msleep(ABORT_POLLING_PERIOD);
  541. }
  542. if (CMD_SP(cmd))
  543. ret = QLA_FUNCTION_FAILED;
  544. return ret;
  545. }
  546. /*
  547. * qla2x00_wait_for_hba_online
  548. * Wait till the HBA is online after going through
  549. * <= MAX_RETRIES_OF_ISP_ABORT or
  550. * finally HBA is disabled ie marked offline
  551. *
  552. * Input:
  553. * ha - pointer to host adapter structure
  554. *
  555. * Note:
  556. * Does context switching-Release SPIN_LOCK
  557. * (if any) before calling this routine.
  558. *
  559. * Return:
  560. * Success (Adapter is online) : 0
  561. * Failed (Adapter is offline/disabled) : 1
  562. */
  563. int
  564. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  565. {
  566. int return_status;
  567. unsigned long wait_online;
  568. struct qla_hw_data *ha = vha->hw;
  569. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  570. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  571. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  572. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  573. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  574. ha->dpc_active) && time_before(jiffies, wait_online)) {
  575. msleep(1000);
  576. }
  577. if (base_vha->flags.online)
  578. return_status = QLA_SUCCESS;
  579. else
  580. return_status = QLA_FUNCTION_FAILED;
  581. return (return_status);
  582. }
  583. /*
  584. * qla2x00_wait_for_reset_ready
  585. * Wait till the HBA is online after going through
  586. * <= MAX_RETRIES_OF_ISP_ABORT or
  587. * finally HBA is disabled ie marked offline or flash
  588. * operations are in progress.
  589. *
  590. * Input:
  591. * ha - pointer to host adapter structure
  592. *
  593. * Note:
  594. * Does context switching-Release SPIN_LOCK
  595. * (if any) before calling this routine.
  596. *
  597. * Return:
  598. * Success (Adapter is online/no flash ops) : 0
  599. * Failed (Adapter is offline/disabled/flash ops in progress) : 1
  600. */
  601. static int
  602. qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
  603. {
  604. int return_status;
  605. unsigned long wait_online;
  606. struct qla_hw_data *ha = vha->hw;
  607. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  608. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  609. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  610. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  611. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  612. ha->optrom_state != QLA_SWAITING ||
  613. ha->dpc_active) && time_before(jiffies, wait_online))
  614. msleep(1000);
  615. if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
  616. return_status = QLA_SUCCESS;
  617. else
  618. return_status = QLA_FUNCTION_FAILED;
  619. DEBUG2(printk("%s return_status=%d\n", __func__, return_status));
  620. return return_status;
  621. }
  622. int
  623. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  624. {
  625. int return_status;
  626. unsigned long wait_reset;
  627. struct qla_hw_data *ha = vha->hw;
  628. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  629. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  630. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  631. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  632. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  633. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  634. msleep(1000);
  635. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  636. ha->flags.chip_reset_done)
  637. break;
  638. }
  639. if (ha->flags.chip_reset_done)
  640. return_status = QLA_SUCCESS;
  641. else
  642. return_status = QLA_FUNCTION_FAILED;
  643. return return_status;
  644. }
  645. /*
  646. * qla2x00_wait_for_loop_ready
  647. * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
  648. * to be in LOOP_READY state.
  649. * Input:
  650. * ha - pointer to host adapter structure
  651. *
  652. * Note:
  653. * Does context switching-Release SPIN_LOCK
  654. * (if any) before calling this routine.
  655. *
  656. *
  657. * Return:
  658. * Success (LOOP_READY) : 0
  659. * Failed (LOOP_NOT_READY) : 1
  660. */
  661. static inline int
  662. qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
  663. {
  664. int return_status = QLA_SUCCESS;
  665. unsigned long loop_timeout ;
  666. struct qla_hw_data *ha = vha->hw;
  667. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  668. /* wait for 5 min at the max for loop to be ready */
  669. loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  670. while ((!atomic_read(&base_vha->loop_down_timer) &&
  671. atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
  672. atomic_read(&base_vha->loop_state) != LOOP_READY) {
  673. if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  674. return_status = QLA_FUNCTION_FAILED;
  675. break;
  676. }
  677. msleep(1000);
  678. if (time_after_eq(jiffies, loop_timeout)) {
  679. return_status = QLA_FUNCTION_FAILED;
  680. break;
  681. }
  682. }
  683. return (return_status);
  684. }
  685. static void
  686. sp_get(struct srb *sp)
  687. {
  688. atomic_inc(&sp->ref_count);
  689. }
  690. /**************************************************************************
  691. * qla2xxx_eh_abort
  692. *
  693. * Description:
  694. * The abort function will abort the specified command.
  695. *
  696. * Input:
  697. * cmd = Linux SCSI command packet to be aborted.
  698. *
  699. * Returns:
  700. * Either SUCCESS or FAILED.
  701. *
  702. * Note:
  703. * Only return FAILED if command not returned by firmware.
  704. **************************************************************************/
  705. static int
  706. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  707. {
  708. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  709. srb_t *sp;
  710. int ret = SUCCESS;
  711. unsigned int id, lun;
  712. unsigned long flags;
  713. int wait = 0;
  714. struct qla_hw_data *ha = vha->hw;
  715. fc_block_scsi_eh(cmd);
  716. if (!CMD_SP(cmd))
  717. return SUCCESS;
  718. id = cmd->device->id;
  719. lun = cmd->device->lun;
  720. spin_lock_irqsave(&ha->hardware_lock, flags);
  721. sp = (srb_t *) CMD_SP(cmd);
  722. if (!sp) {
  723. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  724. return SUCCESS;
  725. }
  726. DEBUG2(printk("%s(%ld): aborting sp %p from RISC.",
  727. __func__, vha->host_no, sp));
  728. /* Get a reference to the sp and drop the lock.*/
  729. sp_get(sp);
  730. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  731. if (ha->isp_ops->abort_command(sp)) {
  732. DEBUG2(printk("%s(%ld): abort_command "
  733. "mbx failed.\n", __func__, vha->host_no));
  734. ret = FAILED;
  735. } else {
  736. DEBUG3(printk("%s(%ld): abort_command "
  737. "mbx success.\n", __func__, vha->host_no));
  738. wait = 1;
  739. }
  740. qla2x00_sp_compl(ha, sp);
  741. /* Wait for the command to be returned. */
  742. if (wait) {
  743. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  744. qla_printk(KERN_ERR, ha,
  745. "scsi(%ld:%d:%d): Abort handler timed out -- %x.\n",
  746. vha->host_no, id, lun, ret);
  747. ret = FAILED;
  748. }
  749. }
  750. qla_printk(KERN_INFO, ha,
  751. "scsi(%ld:%d:%d): Abort command issued -- %d %x.\n",
  752. vha->host_no, id, lun, wait, ret);
  753. return ret;
  754. }
  755. int
  756. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  757. unsigned int l, enum nexus_wait_type type)
  758. {
  759. int cnt, match, status;
  760. unsigned long flags;
  761. struct qla_hw_data *ha = vha->hw;
  762. struct req_que *req;
  763. srb_t *sp;
  764. status = QLA_SUCCESS;
  765. spin_lock_irqsave(&ha->hardware_lock, flags);
  766. req = vha->req;
  767. for (cnt = 1; status == QLA_SUCCESS &&
  768. cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  769. sp = req->outstanding_cmds[cnt];
  770. if (!sp)
  771. continue;
  772. if ((sp->ctx) && !IS_PROT_IO(sp))
  773. continue;
  774. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  775. continue;
  776. match = 0;
  777. switch (type) {
  778. case WAIT_HOST:
  779. match = 1;
  780. break;
  781. case WAIT_TARGET:
  782. match = sp->cmd->device->id == t;
  783. break;
  784. case WAIT_LUN:
  785. match = (sp->cmd->device->id == t &&
  786. sp->cmd->device->lun == l);
  787. break;
  788. }
  789. if (!match)
  790. continue;
  791. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  792. status = qla2x00_eh_wait_on_command(sp->cmd);
  793. spin_lock_irqsave(&ha->hardware_lock, flags);
  794. }
  795. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  796. return status;
  797. }
  798. static char *reset_errors[] = {
  799. "HBA not online",
  800. "HBA not ready",
  801. "Task management failed",
  802. "Waiting for command completions",
  803. };
  804. static int
  805. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  806. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
  807. {
  808. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  809. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  810. int err;
  811. fc_block_scsi_eh(cmd);
  812. if (!fcport)
  813. return FAILED;
  814. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET ISSUED.\n",
  815. vha->host_no, cmd->device->id, cmd->device->lun, name);
  816. err = 0;
  817. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  818. goto eh_reset_failed;
  819. err = 1;
  820. if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS)
  821. goto eh_reset_failed;
  822. err = 2;
  823. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  824. != QLA_SUCCESS)
  825. goto eh_reset_failed;
  826. err = 3;
  827. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  828. cmd->device->lun, type) != QLA_SUCCESS)
  829. goto eh_reset_failed;
  830. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET SUCCEEDED.\n",
  831. vha->host_no, cmd->device->id, cmd->device->lun, name);
  832. return SUCCESS;
  833. eh_reset_failed:
  834. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET FAILED: %s.\n"
  835. , vha->host_no, cmd->device->id, cmd->device->lun, name,
  836. reset_errors[err]);
  837. return FAILED;
  838. }
  839. static int
  840. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  841. {
  842. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  843. struct qla_hw_data *ha = vha->hw;
  844. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  845. ha->isp_ops->lun_reset);
  846. }
  847. static int
  848. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  849. {
  850. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  851. struct qla_hw_data *ha = vha->hw;
  852. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  853. ha->isp_ops->target_reset);
  854. }
  855. /**************************************************************************
  856. * qla2xxx_eh_bus_reset
  857. *
  858. * Description:
  859. * The bus reset function will reset the bus and abort any executing
  860. * commands.
  861. *
  862. * Input:
  863. * cmd = Linux SCSI command packet of the command that cause the
  864. * bus reset.
  865. *
  866. * Returns:
  867. * SUCCESS/FAILURE (defined as macro in scsi.h).
  868. *
  869. **************************************************************************/
  870. static int
  871. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  872. {
  873. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  874. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  875. int ret = FAILED;
  876. unsigned int id, lun;
  877. fc_block_scsi_eh(cmd);
  878. id = cmd->device->id;
  879. lun = cmd->device->lun;
  880. if (!fcport)
  881. return ret;
  882. qla_printk(KERN_INFO, vha->hw,
  883. "scsi(%ld:%d:%d): BUS RESET ISSUED.\n", vha->host_no, id, lun);
  884. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  885. DEBUG2(printk("%s failed:board disabled\n",__func__));
  886. goto eh_bus_reset_done;
  887. }
  888. if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
  889. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  890. ret = SUCCESS;
  891. }
  892. if (ret == FAILED)
  893. goto eh_bus_reset_done;
  894. /* Flush outstanding commands. */
  895. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  896. QLA_SUCCESS)
  897. ret = FAILED;
  898. eh_bus_reset_done:
  899. qla_printk(KERN_INFO, vha->hw, "%s: reset %s\n", __func__,
  900. (ret == FAILED) ? "failed" : "succeded");
  901. return ret;
  902. }
  903. /**************************************************************************
  904. * qla2xxx_eh_host_reset
  905. *
  906. * Description:
  907. * The reset function will reset the Adapter.
  908. *
  909. * Input:
  910. * cmd = Linux SCSI command packet of the command that cause the
  911. * adapter reset.
  912. *
  913. * Returns:
  914. * Either SUCCESS or FAILED.
  915. *
  916. * Note:
  917. **************************************************************************/
  918. static int
  919. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  920. {
  921. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  922. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  923. struct qla_hw_data *ha = vha->hw;
  924. int ret = FAILED;
  925. unsigned int id, lun;
  926. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  927. fc_block_scsi_eh(cmd);
  928. id = cmd->device->id;
  929. lun = cmd->device->lun;
  930. if (!fcport)
  931. return ret;
  932. qla_printk(KERN_INFO, ha,
  933. "scsi(%ld:%d:%d): ADAPTER RESET ISSUED.\n", vha->host_no, id, lun);
  934. if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
  935. goto eh_host_reset_lock;
  936. /*
  937. * Fixme-may be dpc thread is active and processing
  938. * loop_resync,so wait a while for it to
  939. * be completed and then issue big hammer.Otherwise
  940. * it may cause I/O failure as big hammer marks the
  941. * devices as lost kicking of the port_down_timer
  942. * while dpc is stuck for the mailbox to complete.
  943. */
  944. qla2x00_wait_for_loop_ready(vha);
  945. if (vha != base_vha) {
  946. if (qla2x00_vp_abort_isp(vha))
  947. goto eh_host_reset_lock;
  948. } else {
  949. if (IS_QLA82XX(vha->hw)) {
  950. if (!qla82xx_fcoe_ctx_reset(vha)) {
  951. /* Ctx reset success */
  952. ret = SUCCESS;
  953. goto eh_host_reset_lock;
  954. }
  955. /* fall thru if ctx reset failed */
  956. }
  957. if (ha->wq)
  958. flush_workqueue(ha->wq);
  959. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  960. if (ha->isp_ops->abort_isp(base_vha)) {
  961. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  962. /* failed. schedule dpc to try */
  963. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  964. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  965. goto eh_host_reset_lock;
  966. }
  967. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  968. }
  969. /* Waiting for command to be returned to OS.*/
  970. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  971. QLA_SUCCESS)
  972. ret = SUCCESS;
  973. eh_host_reset_lock:
  974. qla_printk(KERN_INFO, ha, "%s: reset %s\n", __func__,
  975. (ret == FAILED) ? "failed" : "succeded");
  976. return ret;
  977. }
  978. /*
  979. * qla2x00_loop_reset
  980. * Issue loop reset.
  981. *
  982. * Input:
  983. * ha = adapter block pointer.
  984. *
  985. * Returns:
  986. * 0 = success
  987. */
  988. int
  989. qla2x00_loop_reset(scsi_qla_host_t *vha)
  990. {
  991. int ret;
  992. struct fc_port *fcport;
  993. struct qla_hw_data *ha = vha->hw;
  994. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  995. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  996. if (fcport->port_type != FCT_TARGET)
  997. continue;
  998. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  999. if (ret != QLA_SUCCESS) {
  1000. DEBUG2_3(printk("%s(%ld): bus_reset failed: "
  1001. "target_reset=%d d_id=%x.\n", __func__,
  1002. vha->host_no, ret, fcport->d_id.b24));
  1003. }
  1004. }
  1005. }
  1006. if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
  1007. ret = qla2x00_full_login_lip(vha);
  1008. if (ret != QLA_SUCCESS) {
  1009. DEBUG2_3(printk("%s(%ld): failed: "
  1010. "full_login_lip=%d.\n", __func__, vha->host_no,
  1011. ret));
  1012. }
  1013. atomic_set(&vha->loop_state, LOOP_DOWN);
  1014. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1015. qla2x00_mark_all_devices_lost(vha, 0);
  1016. qla2x00_wait_for_loop_ready(vha);
  1017. }
  1018. if (ha->flags.enable_lip_reset) {
  1019. ret = qla2x00_lip_reset(vha);
  1020. if (ret != QLA_SUCCESS) {
  1021. DEBUG2_3(printk("%s(%ld): failed: "
  1022. "lip_reset=%d.\n", __func__, vha->host_no, ret));
  1023. } else
  1024. qla2x00_wait_for_loop_ready(vha);
  1025. }
  1026. /* Issue marker command only when we are going to start the I/O */
  1027. vha->marker_needed = 1;
  1028. return QLA_SUCCESS;
  1029. }
  1030. void
  1031. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1032. {
  1033. int que, cnt;
  1034. unsigned long flags;
  1035. srb_t *sp;
  1036. struct srb_ctx *ctx;
  1037. struct qla_hw_data *ha = vha->hw;
  1038. struct req_que *req;
  1039. spin_lock_irqsave(&ha->hardware_lock, flags);
  1040. for (que = 0; que < ha->max_req_queues; que++) {
  1041. req = ha->req_q_map[que];
  1042. if (!req)
  1043. continue;
  1044. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  1045. sp = req->outstanding_cmds[cnt];
  1046. if (sp) {
  1047. req->outstanding_cmds[cnt] = NULL;
  1048. if (!sp->ctx ||
  1049. (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
  1050. IS_PROT_IO(sp)) {
  1051. sp->cmd->result = res;
  1052. qla2x00_sp_compl(ha, sp);
  1053. } else {
  1054. ctx = sp->ctx;
  1055. if (ctx->type == SRB_LOGIN_CMD ||
  1056. ctx->type == SRB_LOGOUT_CMD) {
  1057. ctx->u.iocb_cmd->free(sp);
  1058. } else {
  1059. struct fc_bsg_job *bsg_job =
  1060. ctx->u.bsg_job;
  1061. if (bsg_job->request->msgcode
  1062. == FC_BSG_HST_CT)
  1063. kfree(sp->fcport);
  1064. bsg_job->req->errors = 0;
  1065. bsg_job->reply->result = res;
  1066. bsg_job->job_done(bsg_job);
  1067. kfree(sp->ctx);
  1068. mempool_free(sp,
  1069. ha->srb_mempool);
  1070. }
  1071. }
  1072. }
  1073. }
  1074. }
  1075. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1076. }
  1077. static int
  1078. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1079. {
  1080. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1081. if (!rport || fc_remote_port_chkready(rport))
  1082. return -ENXIO;
  1083. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1084. return 0;
  1085. }
  1086. static int
  1087. qla2xxx_slave_configure(struct scsi_device *sdev)
  1088. {
  1089. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1090. struct req_que *req = vha->req;
  1091. if (sdev->tagged_supported)
  1092. scsi_activate_tcq(sdev, req->max_q_depth);
  1093. else
  1094. scsi_deactivate_tcq(sdev, req->max_q_depth);
  1095. return 0;
  1096. }
  1097. static void
  1098. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1099. {
  1100. sdev->hostdata = NULL;
  1101. }
  1102. static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
  1103. {
  1104. fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
  1105. if (!scsi_track_queue_full(sdev, qdepth))
  1106. return;
  1107. DEBUG2(qla_printk(KERN_INFO, fcport->vha->hw,
  1108. "scsi(%ld:%d:%d:%d): Queue depth adjusted-down to %d.\n",
  1109. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1110. sdev->queue_depth));
  1111. }
  1112. static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
  1113. {
  1114. fc_port_t *fcport = sdev->hostdata;
  1115. struct scsi_qla_host *vha = fcport->vha;
  1116. struct qla_hw_data *ha = vha->hw;
  1117. struct req_que *req = NULL;
  1118. req = vha->req;
  1119. if (!req)
  1120. return;
  1121. if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
  1122. return;
  1123. if (sdev->ordered_tags)
  1124. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
  1125. else
  1126. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
  1127. DEBUG2(qla_printk(KERN_INFO, ha,
  1128. "scsi(%ld:%d:%d:%d): Queue depth adjusted-up to %d.\n",
  1129. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1130. sdev->queue_depth));
  1131. }
  1132. static int
  1133. qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
  1134. {
  1135. switch (reason) {
  1136. case SCSI_QDEPTH_DEFAULT:
  1137. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1138. break;
  1139. case SCSI_QDEPTH_QFULL:
  1140. qla2x00_handle_queue_full(sdev, qdepth);
  1141. break;
  1142. case SCSI_QDEPTH_RAMP_UP:
  1143. qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
  1144. break;
  1145. default:
  1146. return -EOPNOTSUPP;
  1147. }
  1148. return sdev->queue_depth;
  1149. }
  1150. static int
  1151. qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
  1152. {
  1153. if (sdev->tagged_supported) {
  1154. scsi_set_tag_type(sdev, tag_type);
  1155. if (tag_type)
  1156. scsi_activate_tcq(sdev, sdev->queue_depth);
  1157. else
  1158. scsi_deactivate_tcq(sdev, sdev->queue_depth);
  1159. } else
  1160. tag_type = 0;
  1161. return tag_type;
  1162. }
  1163. /**
  1164. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1165. * @ha: HA context
  1166. *
  1167. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1168. * supported addressing method.
  1169. */
  1170. static void
  1171. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1172. {
  1173. /* Assume a 32bit DMA mask. */
  1174. ha->flags.enable_64bit_addressing = 0;
  1175. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1176. /* Any upper-dword bits set? */
  1177. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1178. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1179. /* Ok, a 64bit DMA mask is applicable. */
  1180. ha->flags.enable_64bit_addressing = 1;
  1181. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1182. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1183. return;
  1184. }
  1185. }
  1186. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1187. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1188. }
  1189. static void
  1190. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1191. {
  1192. unsigned long flags = 0;
  1193. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1194. spin_lock_irqsave(&ha->hardware_lock, flags);
  1195. ha->interrupts_on = 1;
  1196. /* enable risc and host interrupts */
  1197. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1198. RD_REG_WORD(&reg->ictrl);
  1199. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1200. }
  1201. static void
  1202. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1203. {
  1204. unsigned long flags = 0;
  1205. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1206. spin_lock_irqsave(&ha->hardware_lock, flags);
  1207. ha->interrupts_on = 0;
  1208. /* disable risc and host interrupts */
  1209. WRT_REG_WORD(&reg->ictrl, 0);
  1210. RD_REG_WORD(&reg->ictrl);
  1211. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1212. }
  1213. static void
  1214. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1215. {
  1216. unsigned long flags = 0;
  1217. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1218. spin_lock_irqsave(&ha->hardware_lock, flags);
  1219. ha->interrupts_on = 1;
  1220. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1221. RD_REG_DWORD(&reg->ictrl);
  1222. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1223. }
  1224. static void
  1225. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1226. {
  1227. unsigned long flags = 0;
  1228. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1229. if (IS_NOPOLLING_TYPE(ha))
  1230. return;
  1231. spin_lock_irqsave(&ha->hardware_lock, flags);
  1232. ha->interrupts_on = 0;
  1233. WRT_REG_DWORD(&reg->ictrl, 0);
  1234. RD_REG_DWORD(&reg->ictrl);
  1235. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1236. }
  1237. static struct isp_operations qla2100_isp_ops = {
  1238. .pci_config = qla2100_pci_config,
  1239. .reset_chip = qla2x00_reset_chip,
  1240. .chip_diag = qla2x00_chip_diag,
  1241. .config_rings = qla2x00_config_rings,
  1242. .reset_adapter = qla2x00_reset_adapter,
  1243. .nvram_config = qla2x00_nvram_config,
  1244. .update_fw_options = qla2x00_update_fw_options,
  1245. .load_risc = qla2x00_load_risc,
  1246. .pci_info_str = qla2x00_pci_info_str,
  1247. .fw_version_str = qla2x00_fw_version_str,
  1248. .intr_handler = qla2100_intr_handler,
  1249. .enable_intrs = qla2x00_enable_intrs,
  1250. .disable_intrs = qla2x00_disable_intrs,
  1251. .abort_command = qla2x00_abort_command,
  1252. .target_reset = qla2x00_abort_target,
  1253. .lun_reset = qla2x00_lun_reset,
  1254. .fabric_login = qla2x00_login_fabric,
  1255. .fabric_logout = qla2x00_fabric_logout,
  1256. .calc_req_entries = qla2x00_calc_iocbs_32,
  1257. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1258. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1259. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1260. .read_nvram = qla2x00_read_nvram_data,
  1261. .write_nvram = qla2x00_write_nvram_data,
  1262. .fw_dump = qla2100_fw_dump,
  1263. .beacon_on = NULL,
  1264. .beacon_off = NULL,
  1265. .beacon_blink = NULL,
  1266. .read_optrom = qla2x00_read_optrom_data,
  1267. .write_optrom = qla2x00_write_optrom_data,
  1268. .get_flash_version = qla2x00_get_flash_version,
  1269. .start_scsi = qla2x00_start_scsi,
  1270. .abort_isp = qla2x00_abort_isp,
  1271. };
  1272. static struct isp_operations qla2300_isp_ops = {
  1273. .pci_config = qla2300_pci_config,
  1274. .reset_chip = qla2x00_reset_chip,
  1275. .chip_diag = qla2x00_chip_diag,
  1276. .config_rings = qla2x00_config_rings,
  1277. .reset_adapter = qla2x00_reset_adapter,
  1278. .nvram_config = qla2x00_nvram_config,
  1279. .update_fw_options = qla2x00_update_fw_options,
  1280. .load_risc = qla2x00_load_risc,
  1281. .pci_info_str = qla2x00_pci_info_str,
  1282. .fw_version_str = qla2x00_fw_version_str,
  1283. .intr_handler = qla2300_intr_handler,
  1284. .enable_intrs = qla2x00_enable_intrs,
  1285. .disable_intrs = qla2x00_disable_intrs,
  1286. .abort_command = qla2x00_abort_command,
  1287. .target_reset = qla2x00_abort_target,
  1288. .lun_reset = qla2x00_lun_reset,
  1289. .fabric_login = qla2x00_login_fabric,
  1290. .fabric_logout = qla2x00_fabric_logout,
  1291. .calc_req_entries = qla2x00_calc_iocbs_32,
  1292. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1293. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1294. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1295. .read_nvram = qla2x00_read_nvram_data,
  1296. .write_nvram = qla2x00_write_nvram_data,
  1297. .fw_dump = qla2300_fw_dump,
  1298. .beacon_on = qla2x00_beacon_on,
  1299. .beacon_off = qla2x00_beacon_off,
  1300. .beacon_blink = qla2x00_beacon_blink,
  1301. .read_optrom = qla2x00_read_optrom_data,
  1302. .write_optrom = qla2x00_write_optrom_data,
  1303. .get_flash_version = qla2x00_get_flash_version,
  1304. .start_scsi = qla2x00_start_scsi,
  1305. .abort_isp = qla2x00_abort_isp,
  1306. };
  1307. static struct isp_operations qla24xx_isp_ops = {
  1308. .pci_config = qla24xx_pci_config,
  1309. .reset_chip = qla24xx_reset_chip,
  1310. .chip_diag = qla24xx_chip_diag,
  1311. .config_rings = qla24xx_config_rings,
  1312. .reset_adapter = qla24xx_reset_adapter,
  1313. .nvram_config = qla24xx_nvram_config,
  1314. .update_fw_options = qla24xx_update_fw_options,
  1315. .load_risc = qla24xx_load_risc,
  1316. .pci_info_str = qla24xx_pci_info_str,
  1317. .fw_version_str = qla24xx_fw_version_str,
  1318. .intr_handler = qla24xx_intr_handler,
  1319. .enable_intrs = qla24xx_enable_intrs,
  1320. .disable_intrs = qla24xx_disable_intrs,
  1321. .abort_command = qla24xx_abort_command,
  1322. .target_reset = qla24xx_abort_target,
  1323. .lun_reset = qla24xx_lun_reset,
  1324. .fabric_login = qla24xx_login_fabric,
  1325. .fabric_logout = qla24xx_fabric_logout,
  1326. .calc_req_entries = NULL,
  1327. .build_iocbs = NULL,
  1328. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1329. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1330. .read_nvram = qla24xx_read_nvram_data,
  1331. .write_nvram = qla24xx_write_nvram_data,
  1332. .fw_dump = qla24xx_fw_dump,
  1333. .beacon_on = qla24xx_beacon_on,
  1334. .beacon_off = qla24xx_beacon_off,
  1335. .beacon_blink = qla24xx_beacon_blink,
  1336. .read_optrom = qla24xx_read_optrom_data,
  1337. .write_optrom = qla24xx_write_optrom_data,
  1338. .get_flash_version = qla24xx_get_flash_version,
  1339. .start_scsi = qla24xx_start_scsi,
  1340. .abort_isp = qla2x00_abort_isp,
  1341. };
  1342. static struct isp_operations qla25xx_isp_ops = {
  1343. .pci_config = qla25xx_pci_config,
  1344. .reset_chip = qla24xx_reset_chip,
  1345. .chip_diag = qla24xx_chip_diag,
  1346. .config_rings = qla24xx_config_rings,
  1347. .reset_adapter = qla24xx_reset_adapter,
  1348. .nvram_config = qla24xx_nvram_config,
  1349. .update_fw_options = qla24xx_update_fw_options,
  1350. .load_risc = qla24xx_load_risc,
  1351. .pci_info_str = qla24xx_pci_info_str,
  1352. .fw_version_str = qla24xx_fw_version_str,
  1353. .intr_handler = qla24xx_intr_handler,
  1354. .enable_intrs = qla24xx_enable_intrs,
  1355. .disable_intrs = qla24xx_disable_intrs,
  1356. .abort_command = qla24xx_abort_command,
  1357. .target_reset = qla24xx_abort_target,
  1358. .lun_reset = qla24xx_lun_reset,
  1359. .fabric_login = qla24xx_login_fabric,
  1360. .fabric_logout = qla24xx_fabric_logout,
  1361. .calc_req_entries = NULL,
  1362. .build_iocbs = NULL,
  1363. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1364. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1365. .read_nvram = qla25xx_read_nvram_data,
  1366. .write_nvram = qla25xx_write_nvram_data,
  1367. .fw_dump = qla25xx_fw_dump,
  1368. .beacon_on = qla24xx_beacon_on,
  1369. .beacon_off = qla24xx_beacon_off,
  1370. .beacon_blink = qla24xx_beacon_blink,
  1371. .read_optrom = qla25xx_read_optrom_data,
  1372. .write_optrom = qla24xx_write_optrom_data,
  1373. .get_flash_version = qla24xx_get_flash_version,
  1374. .start_scsi = qla24xx_dif_start_scsi,
  1375. .abort_isp = qla2x00_abort_isp,
  1376. };
  1377. static struct isp_operations qla81xx_isp_ops = {
  1378. .pci_config = qla25xx_pci_config,
  1379. .reset_chip = qla24xx_reset_chip,
  1380. .chip_diag = qla24xx_chip_diag,
  1381. .config_rings = qla24xx_config_rings,
  1382. .reset_adapter = qla24xx_reset_adapter,
  1383. .nvram_config = qla81xx_nvram_config,
  1384. .update_fw_options = qla81xx_update_fw_options,
  1385. .load_risc = qla81xx_load_risc,
  1386. .pci_info_str = qla24xx_pci_info_str,
  1387. .fw_version_str = qla24xx_fw_version_str,
  1388. .intr_handler = qla24xx_intr_handler,
  1389. .enable_intrs = qla24xx_enable_intrs,
  1390. .disable_intrs = qla24xx_disable_intrs,
  1391. .abort_command = qla24xx_abort_command,
  1392. .target_reset = qla24xx_abort_target,
  1393. .lun_reset = qla24xx_lun_reset,
  1394. .fabric_login = qla24xx_login_fabric,
  1395. .fabric_logout = qla24xx_fabric_logout,
  1396. .calc_req_entries = NULL,
  1397. .build_iocbs = NULL,
  1398. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1399. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1400. .read_nvram = NULL,
  1401. .write_nvram = NULL,
  1402. .fw_dump = qla81xx_fw_dump,
  1403. .beacon_on = qla24xx_beacon_on,
  1404. .beacon_off = qla24xx_beacon_off,
  1405. .beacon_blink = qla24xx_beacon_blink,
  1406. .read_optrom = qla25xx_read_optrom_data,
  1407. .write_optrom = qla24xx_write_optrom_data,
  1408. .get_flash_version = qla24xx_get_flash_version,
  1409. .start_scsi = qla24xx_dif_start_scsi,
  1410. .abort_isp = qla2x00_abort_isp,
  1411. };
  1412. static struct isp_operations qla82xx_isp_ops = {
  1413. .pci_config = qla82xx_pci_config,
  1414. .reset_chip = qla82xx_reset_chip,
  1415. .chip_diag = qla24xx_chip_diag,
  1416. .config_rings = qla82xx_config_rings,
  1417. .reset_adapter = qla24xx_reset_adapter,
  1418. .nvram_config = qla81xx_nvram_config,
  1419. .update_fw_options = qla24xx_update_fw_options,
  1420. .load_risc = qla82xx_load_risc,
  1421. .pci_info_str = qla82xx_pci_info_str,
  1422. .fw_version_str = qla24xx_fw_version_str,
  1423. .intr_handler = qla82xx_intr_handler,
  1424. .enable_intrs = qla82xx_enable_intrs,
  1425. .disable_intrs = qla82xx_disable_intrs,
  1426. .abort_command = qla24xx_abort_command,
  1427. .target_reset = qla24xx_abort_target,
  1428. .lun_reset = qla24xx_lun_reset,
  1429. .fabric_login = qla24xx_login_fabric,
  1430. .fabric_logout = qla24xx_fabric_logout,
  1431. .calc_req_entries = NULL,
  1432. .build_iocbs = NULL,
  1433. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1434. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1435. .read_nvram = qla24xx_read_nvram_data,
  1436. .write_nvram = qla24xx_write_nvram_data,
  1437. .fw_dump = qla24xx_fw_dump,
  1438. .beacon_on = qla24xx_beacon_on,
  1439. .beacon_off = qla24xx_beacon_off,
  1440. .beacon_blink = qla24xx_beacon_blink,
  1441. .read_optrom = qla82xx_read_optrom_data,
  1442. .write_optrom = qla82xx_write_optrom_data,
  1443. .get_flash_version = qla24xx_get_flash_version,
  1444. .start_scsi = qla82xx_start_scsi,
  1445. .abort_isp = qla82xx_abort_isp,
  1446. };
  1447. static inline void
  1448. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1449. {
  1450. ha->device_type = DT_EXTENDED_IDS;
  1451. switch (ha->pdev->device) {
  1452. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1453. ha->device_type |= DT_ISP2100;
  1454. ha->device_type &= ~DT_EXTENDED_IDS;
  1455. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1456. break;
  1457. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1458. ha->device_type |= DT_ISP2200;
  1459. ha->device_type &= ~DT_EXTENDED_IDS;
  1460. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1461. break;
  1462. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1463. ha->device_type |= DT_ISP2300;
  1464. ha->device_type |= DT_ZIO_SUPPORTED;
  1465. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1466. break;
  1467. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1468. ha->device_type |= DT_ISP2312;
  1469. ha->device_type |= DT_ZIO_SUPPORTED;
  1470. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1471. break;
  1472. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1473. ha->device_type |= DT_ISP2322;
  1474. ha->device_type |= DT_ZIO_SUPPORTED;
  1475. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1476. ha->pdev->subsystem_device == 0x0170)
  1477. ha->device_type |= DT_OEM_001;
  1478. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1479. break;
  1480. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1481. ha->device_type |= DT_ISP6312;
  1482. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1483. break;
  1484. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1485. ha->device_type |= DT_ISP6322;
  1486. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1487. break;
  1488. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1489. ha->device_type |= DT_ISP2422;
  1490. ha->device_type |= DT_ZIO_SUPPORTED;
  1491. ha->device_type |= DT_FWI2;
  1492. ha->device_type |= DT_IIDMA;
  1493. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1494. break;
  1495. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1496. ha->device_type |= DT_ISP2432;
  1497. ha->device_type |= DT_ZIO_SUPPORTED;
  1498. ha->device_type |= DT_FWI2;
  1499. ha->device_type |= DT_IIDMA;
  1500. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1501. break;
  1502. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1503. ha->device_type |= DT_ISP8432;
  1504. ha->device_type |= DT_ZIO_SUPPORTED;
  1505. ha->device_type |= DT_FWI2;
  1506. ha->device_type |= DT_IIDMA;
  1507. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1508. break;
  1509. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  1510. ha->device_type |= DT_ISP5422;
  1511. ha->device_type |= DT_FWI2;
  1512. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1513. break;
  1514. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  1515. ha->device_type |= DT_ISP5432;
  1516. ha->device_type |= DT_FWI2;
  1517. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1518. break;
  1519. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  1520. ha->device_type |= DT_ISP2532;
  1521. ha->device_type |= DT_ZIO_SUPPORTED;
  1522. ha->device_type |= DT_FWI2;
  1523. ha->device_type |= DT_IIDMA;
  1524. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1525. break;
  1526. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  1527. ha->device_type |= DT_ISP8001;
  1528. ha->device_type |= DT_ZIO_SUPPORTED;
  1529. ha->device_type |= DT_FWI2;
  1530. ha->device_type |= DT_IIDMA;
  1531. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1532. break;
  1533. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  1534. ha->device_type |= DT_ISP8021;
  1535. ha->device_type |= DT_ZIO_SUPPORTED;
  1536. ha->device_type |= DT_FWI2;
  1537. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1538. /* Initialize 82XX ISP flags */
  1539. qla82xx_init_flags(ha);
  1540. break;
  1541. }
  1542. if (IS_QLA82XX(ha))
  1543. ha->port_no = !(ha->portnum & 1);
  1544. else
  1545. /* Get adapter physical port no from interrupt pin register. */
  1546. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  1547. if (ha->port_no & 1)
  1548. ha->flags.port0 = 1;
  1549. else
  1550. ha->flags.port0 = 0;
  1551. }
  1552. static int
  1553. qla2x00_iospace_config(struct qla_hw_data *ha)
  1554. {
  1555. resource_size_t pio;
  1556. uint16_t msix;
  1557. int cpus;
  1558. if (IS_QLA82XX(ha))
  1559. return qla82xx_iospace_config(ha);
  1560. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1561. QLA2XXX_DRIVER_NAME)) {
  1562. qla_printk(KERN_WARNING, ha,
  1563. "Failed to reserve PIO/MMIO regions (%s)\n",
  1564. pci_name(ha->pdev));
  1565. goto iospace_error_exit;
  1566. }
  1567. if (!(ha->bars & 1))
  1568. goto skip_pio;
  1569. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1570. pio = pci_resource_start(ha->pdev, 0);
  1571. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1572. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1573. qla_printk(KERN_WARNING, ha,
  1574. "Invalid PCI I/O region size (%s)...\n",
  1575. pci_name(ha->pdev));
  1576. pio = 0;
  1577. }
  1578. } else {
  1579. qla_printk(KERN_WARNING, ha,
  1580. "region #0 not a PIO resource (%s)...\n",
  1581. pci_name(ha->pdev));
  1582. pio = 0;
  1583. }
  1584. ha->pio_address = pio;
  1585. skip_pio:
  1586. /* Use MMIO operations for all accesses. */
  1587. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1588. qla_printk(KERN_ERR, ha,
  1589. "region #1 not an MMIO resource (%s), aborting\n",
  1590. pci_name(ha->pdev));
  1591. goto iospace_error_exit;
  1592. }
  1593. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1594. qla_printk(KERN_ERR, ha,
  1595. "Invalid PCI mem region size (%s), aborting\n",
  1596. pci_name(ha->pdev));
  1597. goto iospace_error_exit;
  1598. }
  1599. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1600. if (!ha->iobase) {
  1601. qla_printk(KERN_ERR, ha,
  1602. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  1603. goto iospace_error_exit;
  1604. }
  1605. /* Determine queue resources */
  1606. ha->max_req_queues = ha->max_rsp_queues = 1;
  1607. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1608. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1609. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1610. goto mqiobase_exit;
  1611. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1612. pci_resource_len(ha->pdev, 3));
  1613. if (ha->mqiobase) {
  1614. /* Read MSIX vector size of the board */
  1615. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1616. ha->msix_count = msix;
  1617. /* Max queues are bounded by available msix vectors */
  1618. /* queue 0 uses two msix vectors */
  1619. if (ql2xmultique_tag) {
  1620. cpus = num_online_cpus();
  1621. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1622. (cpus + 1) : (ha->msix_count - 1);
  1623. ha->max_req_queues = 2;
  1624. } else if (ql2xmaxqueues > 1) {
  1625. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1626. QLA_MQ_SIZE : ql2xmaxqueues;
  1627. DEBUG2(qla_printk(KERN_INFO, ha, "QoS mode set, max no"
  1628. " of request queues:%d\n", ha->max_req_queues));
  1629. }
  1630. qla_printk(KERN_INFO, ha,
  1631. "MSI-X vector count: %d\n", msix);
  1632. } else
  1633. qla_printk(KERN_INFO, ha, "BAR 3 not enabled\n");
  1634. mqiobase_exit:
  1635. ha->msix_count = ha->max_rsp_queues + 1;
  1636. return (0);
  1637. iospace_error_exit:
  1638. return (-ENOMEM);
  1639. }
  1640. static void
  1641. qla2xxx_scan_start(struct Scsi_Host *shost)
  1642. {
  1643. scsi_qla_host_t *vha = shost_priv(shost);
  1644. if (vha->hw->flags.running_gold_fw)
  1645. return;
  1646. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1647. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1648. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  1649. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  1650. }
  1651. static int
  1652. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  1653. {
  1654. scsi_qla_host_t *vha = shost_priv(shost);
  1655. if (!vha->host)
  1656. return 1;
  1657. if (time > vha->hw->loop_reset_delay * HZ)
  1658. return 1;
  1659. return atomic_read(&vha->loop_state) == LOOP_READY;
  1660. }
  1661. /*
  1662. * PCI driver interface
  1663. */
  1664. static int __devinit
  1665. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1666. {
  1667. int ret = -ENODEV;
  1668. struct Scsi_Host *host;
  1669. scsi_qla_host_t *base_vha = NULL;
  1670. struct qla_hw_data *ha;
  1671. char pci_info[30];
  1672. char fw_str[30];
  1673. struct scsi_host_template *sht;
  1674. int bars, max_id, mem_only = 0;
  1675. uint16_t req_length = 0, rsp_length = 0;
  1676. struct req_que *req = NULL;
  1677. struct rsp_que *rsp = NULL;
  1678. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  1679. sht = &qla2xxx_driver_template;
  1680. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  1681. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  1682. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  1683. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  1684. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  1685. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  1686. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  1687. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
  1688. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1689. mem_only = 1;
  1690. }
  1691. if (mem_only) {
  1692. if (pci_enable_device_mem(pdev))
  1693. goto probe_out;
  1694. } else {
  1695. if (pci_enable_device(pdev))
  1696. goto probe_out;
  1697. }
  1698. /* This may fail but that's ok */
  1699. pci_enable_pcie_error_reporting(pdev);
  1700. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  1701. if (!ha) {
  1702. DEBUG(printk("Unable to allocate memory for ha\n"));
  1703. goto probe_out;
  1704. }
  1705. ha->pdev = pdev;
  1706. /* Clear our data area */
  1707. ha->bars = bars;
  1708. ha->mem_only = mem_only;
  1709. spin_lock_init(&ha->hardware_lock);
  1710. spin_lock_init(&ha->vport_slock);
  1711. /* Set ISP-type information. */
  1712. qla2x00_set_isp_flags(ha);
  1713. /* Set EEH reset type to fundamental if required by hba */
  1714. if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
  1715. pdev->needs_freset = 1;
  1716. }
  1717. /* Configure PCI I/O space */
  1718. ret = qla2x00_iospace_config(ha);
  1719. if (ret)
  1720. goto probe_hw_failed;
  1721. qla_printk(KERN_INFO, ha,
  1722. "Found an ISP%04X, irq %d, iobase 0x%p\n", pdev->device, pdev->irq,
  1723. ha->iobase);
  1724. ha->prev_topology = 0;
  1725. ha->init_cb_size = sizeof(init_cb_t);
  1726. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  1727. ha->optrom_size = OPTROM_SIZE_2300;
  1728. /* Assign ISP specific operations. */
  1729. max_id = MAX_TARGETS_2200;
  1730. if (IS_QLA2100(ha)) {
  1731. max_id = MAX_TARGETS_2100;
  1732. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  1733. req_length = REQUEST_ENTRY_CNT_2100;
  1734. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1735. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1736. ha->gid_list_info_size = 4;
  1737. ha->flash_conf_off = ~0;
  1738. ha->flash_data_off = ~0;
  1739. ha->nvram_conf_off = ~0;
  1740. ha->nvram_data_off = ~0;
  1741. ha->isp_ops = &qla2100_isp_ops;
  1742. } else if (IS_QLA2200(ha)) {
  1743. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1744. req_length = REQUEST_ENTRY_CNT_2200;
  1745. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1746. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1747. ha->gid_list_info_size = 4;
  1748. ha->flash_conf_off = ~0;
  1749. ha->flash_data_off = ~0;
  1750. ha->nvram_conf_off = ~0;
  1751. ha->nvram_data_off = ~0;
  1752. ha->isp_ops = &qla2100_isp_ops;
  1753. } else if (IS_QLA23XX(ha)) {
  1754. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1755. req_length = REQUEST_ENTRY_CNT_2200;
  1756. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1757. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1758. ha->gid_list_info_size = 6;
  1759. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1760. ha->optrom_size = OPTROM_SIZE_2322;
  1761. ha->flash_conf_off = ~0;
  1762. ha->flash_data_off = ~0;
  1763. ha->nvram_conf_off = ~0;
  1764. ha->nvram_data_off = ~0;
  1765. ha->isp_ops = &qla2300_isp_ops;
  1766. } else if (IS_QLA24XX_TYPE(ha)) {
  1767. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1768. req_length = REQUEST_ENTRY_CNT_24XX;
  1769. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1770. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1771. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1772. ha->gid_list_info_size = 8;
  1773. ha->optrom_size = OPTROM_SIZE_24XX;
  1774. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  1775. ha->isp_ops = &qla24xx_isp_ops;
  1776. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1777. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1778. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1779. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1780. } else if (IS_QLA25XX(ha)) {
  1781. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1782. req_length = REQUEST_ENTRY_CNT_24XX;
  1783. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1784. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1785. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1786. ha->gid_list_info_size = 8;
  1787. ha->optrom_size = OPTROM_SIZE_25XX;
  1788. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1789. ha->isp_ops = &qla25xx_isp_ops;
  1790. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1791. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1792. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1793. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1794. } else if (IS_QLA81XX(ha)) {
  1795. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1796. req_length = REQUEST_ENTRY_CNT_24XX;
  1797. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1798. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1799. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1800. ha->gid_list_info_size = 8;
  1801. ha->optrom_size = OPTROM_SIZE_81XX;
  1802. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1803. ha->isp_ops = &qla81xx_isp_ops;
  1804. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  1805. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  1806. ha->nvram_conf_off = ~0;
  1807. ha->nvram_data_off = ~0;
  1808. } else if (IS_QLA82XX(ha)) {
  1809. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1810. req_length = REQUEST_ENTRY_CNT_82XX;
  1811. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  1812. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1813. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1814. ha->gid_list_info_size = 8;
  1815. ha->optrom_size = OPTROM_SIZE_82XX;
  1816. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1817. ha->isp_ops = &qla82xx_isp_ops;
  1818. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1819. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1820. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1821. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1822. }
  1823. mutex_init(&ha->vport_lock);
  1824. init_completion(&ha->mbx_cmd_comp);
  1825. complete(&ha->mbx_cmd_comp);
  1826. init_completion(&ha->mbx_intr_comp);
  1827. init_completion(&ha->dcbx_comp);
  1828. set_bit(0, (unsigned long *) ha->vp_idx_map);
  1829. qla2x00_config_dma_addressing(ha);
  1830. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  1831. if (!ret) {
  1832. qla_printk(KERN_WARNING, ha,
  1833. "[ERROR] Failed to allocate memory for adapter\n");
  1834. goto probe_hw_failed;
  1835. }
  1836. req->max_q_depth = MAX_Q_DEPTH;
  1837. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  1838. req->max_q_depth = ql2xmaxqdepth;
  1839. base_vha = qla2x00_create_host(sht, ha);
  1840. if (!base_vha) {
  1841. qla_printk(KERN_WARNING, ha,
  1842. "[ERROR] Failed to allocate memory for scsi_host\n");
  1843. ret = -ENOMEM;
  1844. qla2x00_mem_free(ha);
  1845. qla2x00_free_req_que(ha, req);
  1846. qla2x00_free_rsp_que(ha, rsp);
  1847. goto probe_hw_failed;
  1848. }
  1849. pci_set_drvdata(pdev, base_vha);
  1850. host = base_vha->host;
  1851. base_vha->req = req;
  1852. host->can_queue = req->length + 128;
  1853. if (IS_QLA2XXX_MIDTYPE(ha))
  1854. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  1855. else
  1856. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  1857. base_vha->vp_idx;
  1858. /* Set the SG table size based on ISP type */
  1859. if (!IS_FWI2_CAPABLE(ha)) {
  1860. if (IS_QLA2100(ha))
  1861. host->sg_tablesize = 32;
  1862. } else {
  1863. if (!IS_QLA82XX(ha))
  1864. host->sg_tablesize = QLA_SG_ALL;
  1865. }
  1866. host->max_id = max_id;
  1867. host->this_id = 255;
  1868. host->cmd_per_lun = 3;
  1869. host->unique_id = host->host_no;
  1870. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
  1871. host->max_cmd_len = 32;
  1872. else
  1873. host->max_cmd_len = MAX_CMDSZ;
  1874. host->max_channel = MAX_BUSES - 1;
  1875. host->max_lun = MAX_LUNS;
  1876. host->transportt = qla2xxx_transport_template;
  1877. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  1878. /* Set up the irqs */
  1879. ret = qla2x00_request_irqs(ha, rsp);
  1880. if (ret)
  1881. goto probe_init_failed;
  1882. pci_save_state(pdev);
  1883. /* Alloc arrays of request and response ring ptrs */
  1884. que_init:
  1885. if (!qla2x00_alloc_queues(ha)) {
  1886. qla_printk(KERN_WARNING, ha,
  1887. "[ERROR] Failed to allocate memory for queue"
  1888. " pointers\n");
  1889. goto probe_init_failed;
  1890. }
  1891. ha->rsp_q_map[0] = rsp;
  1892. ha->req_q_map[0] = req;
  1893. rsp->req = req;
  1894. req->rsp = rsp;
  1895. set_bit(0, ha->req_qid_map);
  1896. set_bit(0, ha->rsp_qid_map);
  1897. /* FWI2-capable only. */
  1898. req->req_q_in = &ha->iobase->isp24.req_q_in;
  1899. req->req_q_out = &ha->iobase->isp24.req_q_out;
  1900. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  1901. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  1902. if (ha->mqenable) {
  1903. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  1904. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  1905. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  1906. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  1907. }
  1908. if (IS_QLA82XX(ha)) {
  1909. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  1910. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  1911. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  1912. }
  1913. if (qla2x00_initialize_adapter(base_vha)) {
  1914. qla_printk(KERN_WARNING, ha,
  1915. "Failed to initialize adapter\n");
  1916. DEBUG2(printk("scsi(%ld): Failed to initialize adapter - "
  1917. "Adapter flags %x.\n",
  1918. base_vha->host_no, base_vha->device_flags));
  1919. if (IS_QLA82XX(ha)) {
  1920. qla82xx_idc_lock(ha);
  1921. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  1922. QLA82XX_DEV_FAILED);
  1923. qla82xx_idc_unlock(ha);
  1924. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  1925. }
  1926. ret = -ENODEV;
  1927. goto probe_failed;
  1928. }
  1929. if (ha->mqenable) {
  1930. if (qla25xx_setup_mode(base_vha)) {
  1931. qla_printk(KERN_WARNING, ha,
  1932. "Can't create queues, falling back to single"
  1933. " queue mode\n");
  1934. goto que_init;
  1935. }
  1936. }
  1937. if (ha->flags.running_gold_fw)
  1938. goto skip_dpc;
  1939. /*
  1940. * Startup the kernel thread for this host adapter
  1941. */
  1942. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  1943. "%s_dpc", base_vha->host_str);
  1944. if (IS_ERR(ha->dpc_thread)) {
  1945. qla_printk(KERN_WARNING, ha,
  1946. "Unable to start DPC thread!\n");
  1947. ret = PTR_ERR(ha->dpc_thread);
  1948. goto probe_failed;
  1949. }
  1950. skip_dpc:
  1951. list_add_tail(&base_vha->list, &ha->vp_list);
  1952. base_vha->host->irq = ha->pdev->irq;
  1953. /* Initialized the timer */
  1954. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  1955. DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
  1956. base_vha->host_no, ha));
  1957. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
  1958. if (ha->fw_attributes & BIT_4) {
  1959. base_vha->flags.difdix_supported = 1;
  1960. DEBUG18(qla_printk(KERN_INFO, ha,
  1961. "Registering for DIF/DIX type 1 and 3"
  1962. " protection.\n"));
  1963. scsi_host_set_prot(host,
  1964. SHOST_DIF_TYPE1_PROTECTION
  1965. | SHOST_DIF_TYPE2_PROTECTION
  1966. | SHOST_DIF_TYPE3_PROTECTION
  1967. | SHOST_DIX_TYPE1_PROTECTION
  1968. | SHOST_DIX_TYPE2_PROTECTION
  1969. | SHOST_DIX_TYPE3_PROTECTION);
  1970. scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
  1971. } else
  1972. base_vha->flags.difdix_supported = 0;
  1973. }
  1974. ha->isp_ops->enable_intrs(ha);
  1975. ret = scsi_add_host(host, &pdev->dev);
  1976. if (ret)
  1977. goto probe_failed;
  1978. base_vha->flags.init_done = 1;
  1979. base_vha->flags.online = 1;
  1980. scsi_scan_host(host);
  1981. qla2x00_alloc_sysfs_attr(base_vha);
  1982. qla2x00_init_host_attr(base_vha);
  1983. qla2x00_dfs_setup(base_vha);
  1984. qla_printk(KERN_INFO, ha, "\n"
  1985. " QLogic Fibre Channel HBA Driver: %s\n"
  1986. " QLogic %s - %s\n"
  1987. " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n",
  1988. qla2x00_version_str, ha->model_number,
  1989. ha->model_desc ? ha->model_desc : "", pdev->device,
  1990. ha->isp_ops->pci_info_str(base_vha, pci_info), pci_name(pdev),
  1991. ha->flags.enable_64bit_addressing ? '+' : '-', base_vha->host_no,
  1992. ha->isp_ops->fw_version_str(base_vha, fw_str));
  1993. return 0;
  1994. probe_init_failed:
  1995. qla2x00_free_req_que(ha, req);
  1996. qla2x00_free_rsp_que(ha, rsp);
  1997. ha->max_req_queues = ha->max_rsp_queues = 0;
  1998. probe_failed:
  1999. if (base_vha->timer_active)
  2000. qla2x00_stop_timer(base_vha);
  2001. base_vha->flags.online = 0;
  2002. if (ha->dpc_thread) {
  2003. struct task_struct *t = ha->dpc_thread;
  2004. ha->dpc_thread = NULL;
  2005. kthread_stop(t);
  2006. }
  2007. qla2x00_free_device(base_vha);
  2008. scsi_host_put(base_vha->host);
  2009. probe_hw_failed:
  2010. if (IS_QLA82XX(ha)) {
  2011. qla82xx_idc_lock(ha);
  2012. qla82xx_clear_drv_active(ha);
  2013. qla82xx_idc_unlock(ha);
  2014. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2015. if (!ql2xdbwr)
  2016. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2017. } else {
  2018. if (ha->iobase)
  2019. iounmap(ha->iobase);
  2020. }
  2021. pci_release_selected_regions(ha->pdev, ha->bars);
  2022. kfree(ha);
  2023. ha = NULL;
  2024. probe_out:
  2025. pci_disable_device(pdev);
  2026. return ret;
  2027. }
  2028. static void
  2029. qla2x00_shutdown(struct pci_dev *pdev)
  2030. {
  2031. scsi_qla_host_t *vha;
  2032. struct qla_hw_data *ha;
  2033. vha = pci_get_drvdata(pdev);
  2034. ha = vha->hw;
  2035. /* Turn-off FCE trace */
  2036. if (ha->flags.fce_enabled) {
  2037. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2038. ha->flags.fce_enabled = 0;
  2039. }
  2040. /* Turn-off EFT trace */
  2041. if (ha->eft)
  2042. qla2x00_disable_eft_trace(vha);
  2043. /* Stop currently executing firmware. */
  2044. qla2x00_try_to_stop_firmware(vha);
  2045. /* Turn adapter off line */
  2046. vha->flags.online = 0;
  2047. /* turn-off interrupts on the card */
  2048. if (ha->interrupts_on) {
  2049. vha->flags.init_done = 0;
  2050. ha->isp_ops->disable_intrs(ha);
  2051. }
  2052. qla2x00_free_irqs(vha);
  2053. qla2x00_free_fw_dump(ha);
  2054. }
  2055. static void
  2056. qla2x00_remove_one(struct pci_dev *pdev)
  2057. {
  2058. scsi_qla_host_t *base_vha, *vha;
  2059. struct qla_hw_data *ha;
  2060. unsigned long flags;
  2061. base_vha = pci_get_drvdata(pdev);
  2062. ha = base_vha->hw;
  2063. spin_lock_irqsave(&ha->vport_slock, flags);
  2064. list_for_each_entry(vha, &ha->vp_list, list) {
  2065. atomic_inc(&vha->vref_count);
  2066. if (vha->fc_vport) {
  2067. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2068. fc_vport_terminate(vha->fc_vport);
  2069. spin_lock_irqsave(&ha->vport_slock, flags);
  2070. }
  2071. atomic_dec(&vha->vref_count);
  2072. }
  2073. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2074. set_bit(UNLOADING, &base_vha->dpc_flags);
  2075. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2076. qla2x00_dfs_remove(base_vha);
  2077. qla84xx_put_chip(base_vha);
  2078. /* Disable timer */
  2079. if (base_vha->timer_active)
  2080. qla2x00_stop_timer(base_vha);
  2081. base_vha->flags.online = 0;
  2082. /* Flush the work queue and remove it */
  2083. if (ha->wq) {
  2084. flush_workqueue(ha->wq);
  2085. destroy_workqueue(ha->wq);
  2086. ha->wq = NULL;
  2087. }
  2088. /* Kill the kernel thread for this host */
  2089. if (ha->dpc_thread) {
  2090. struct task_struct *t = ha->dpc_thread;
  2091. /*
  2092. * qla2xxx_wake_dpc checks for ->dpc_thread
  2093. * so we need to zero it out.
  2094. */
  2095. ha->dpc_thread = NULL;
  2096. kthread_stop(t);
  2097. }
  2098. qla2x00_free_sysfs_attr(base_vha);
  2099. fc_remove_host(base_vha->host);
  2100. scsi_remove_host(base_vha->host);
  2101. qla2x00_free_device(base_vha);
  2102. scsi_host_put(base_vha->host);
  2103. if (IS_QLA82XX(ha)) {
  2104. qla82xx_idc_lock(ha);
  2105. qla82xx_clear_drv_active(ha);
  2106. qla82xx_idc_unlock(ha);
  2107. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2108. if (!ql2xdbwr)
  2109. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2110. } else {
  2111. if (ha->iobase)
  2112. iounmap(ha->iobase);
  2113. if (ha->mqiobase)
  2114. iounmap(ha->mqiobase);
  2115. }
  2116. pci_release_selected_regions(ha->pdev, ha->bars);
  2117. kfree(ha);
  2118. ha = NULL;
  2119. pci_disable_pcie_error_reporting(pdev);
  2120. pci_disable_device(pdev);
  2121. pci_set_drvdata(pdev, NULL);
  2122. }
  2123. static void
  2124. qla2x00_free_device(scsi_qla_host_t *vha)
  2125. {
  2126. struct qla_hw_data *ha = vha->hw;
  2127. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2128. /* Disable timer */
  2129. if (vha->timer_active)
  2130. qla2x00_stop_timer(vha);
  2131. /* Kill the kernel thread for this host */
  2132. if (ha->dpc_thread) {
  2133. struct task_struct *t = ha->dpc_thread;
  2134. /*
  2135. * qla2xxx_wake_dpc checks for ->dpc_thread
  2136. * so we need to zero it out.
  2137. */
  2138. ha->dpc_thread = NULL;
  2139. kthread_stop(t);
  2140. }
  2141. qla25xx_delete_queues(vha);
  2142. if (ha->flags.fce_enabled)
  2143. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2144. if (ha->eft)
  2145. qla2x00_disable_eft_trace(vha);
  2146. /* Stop currently executing firmware. */
  2147. qla2x00_try_to_stop_firmware(vha);
  2148. vha->flags.online = 0;
  2149. /* turn-off interrupts on the card */
  2150. if (ha->interrupts_on) {
  2151. vha->flags.init_done = 0;
  2152. ha->isp_ops->disable_intrs(ha);
  2153. }
  2154. qla2x00_free_irqs(vha);
  2155. qla2x00_free_fcports(vha);
  2156. qla2x00_mem_free(ha);
  2157. qla2x00_free_queues(ha);
  2158. }
  2159. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2160. {
  2161. fc_port_t *fcport, *tfcport;
  2162. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2163. list_del(&fcport->list);
  2164. kfree(fcport);
  2165. fcport = NULL;
  2166. }
  2167. }
  2168. static inline void
  2169. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2170. int defer)
  2171. {
  2172. struct fc_rport *rport;
  2173. scsi_qla_host_t *base_vha;
  2174. unsigned long flags;
  2175. if (!fcport->rport)
  2176. return;
  2177. rport = fcport->rport;
  2178. if (defer) {
  2179. base_vha = pci_get_drvdata(vha->hw->pdev);
  2180. spin_lock_irqsave(vha->host->host_lock, flags);
  2181. fcport->drport = rport;
  2182. spin_unlock_irqrestore(vha->host->host_lock, flags);
  2183. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2184. qla2xxx_wake_dpc(base_vha);
  2185. } else
  2186. fc_remote_port_delete(rport);
  2187. }
  2188. /*
  2189. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2190. *
  2191. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2192. *
  2193. * Return: None.
  2194. *
  2195. * Context:
  2196. */
  2197. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2198. int do_login, int defer)
  2199. {
  2200. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2201. vha->vp_idx == fcport->vp_idx) {
  2202. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2203. qla2x00_schedule_rport_del(vha, fcport, defer);
  2204. }
  2205. /*
  2206. * We may need to retry the login, so don't change the state of the
  2207. * port but do the retries.
  2208. */
  2209. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2210. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2211. if (!do_login)
  2212. return;
  2213. if (fcport->login_retry == 0) {
  2214. fcport->login_retry = vha->hw->login_retry_count;
  2215. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2216. DEBUG(printk("scsi(%ld): Port login retry: "
  2217. "%02x%02x%02x%02x%02x%02x%02x%02x, "
  2218. "id = 0x%04x retry cnt=%d\n",
  2219. vha->host_no,
  2220. fcport->port_name[0],
  2221. fcport->port_name[1],
  2222. fcport->port_name[2],
  2223. fcport->port_name[3],
  2224. fcport->port_name[4],
  2225. fcport->port_name[5],
  2226. fcport->port_name[6],
  2227. fcport->port_name[7],
  2228. fcport->loop_id,
  2229. fcport->login_retry));
  2230. }
  2231. }
  2232. /*
  2233. * qla2x00_mark_all_devices_lost
  2234. * Updates fcport state when device goes offline.
  2235. *
  2236. * Input:
  2237. * ha = adapter block pointer.
  2238. * fcport = port structure pointer.
  2239. *
  2240. * Return:
  2241. * None.
  2242. *
  2243. * Context:
  2244. */
  2245. void
  2246. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  2247. {
  2248. fc_port_t *fcport;
  2249. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2250. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
  2251. continue;
  2252. /*
  2253. * No point in marking the device as lost, if the device is
  2254. * already DEAD.
  2255. */
  2256. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  2257. continue;
  2258. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2259. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2260. if (defer)
  2261. qla2x00_schedule_rport_del(vha, fcport, defer);
  2262. else if (vha->vp_idx == fcport->vp_idx)
  2263. qla2x00_schedule_rport_del(vha, fcport, defer);
  2264. }
  2265. }
  2266. }
  2267. /*
  2268. * qla2x00_mem_alloc
  2269. * Allocates adapter memory.
  2270. *
  2271. * Returns:
  2272. * 0 = success.
  2273. * !0 = failure.
  2274. */
  2275. static int
  2276. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  2277. struct req_que **req, struct rsp_que **rsp)
  2278. {
  2279. char name[16];
  2280. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  2281. &ha->init_cb_dma, GFP_KERNEL);
  2282. if (!ha->init_cb)
  2283. goto fail;
  2284. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
  2285. &ha->gid_list_dma, GFP_KERNEL);
  2286. if (!ha->gid_list)
  2287. goto fail_free_init_cb;
  2288. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  2289. if (!ha->srb_mempool)
  2290. goto fail_free_gid_list;
  2291. if (IS_QLA82XX(ha)) {
  2292. /* Allocate cache for CT6 Ctx. */
  2293. if (!ctx_cachep) {
  2294. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  2295. sizeof(struct ct6_dsd), 0,
  2296. SLAB_HWCACHE_ALIGN, NULL);
  2297. if (!ctx_cachep)
  2298. goto fail_free_gid_list;
  2299. }
  2300. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  2301. ctx_cachep);
  2302. if (!ha->ctx_mempool)
  2303. goto fail_free_srb_mempool;
  2304. }
  2305. /* Get memory for cached NVRAM */
  2306. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  2307. if (!ha->nvram)
  2308. goto fail_free_ctx_mempool;
  2309. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  2310. ha->pdev->device);
  2311. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2312. DMA_POOL_SIZE, 8, 0);
  2313. if (!ha->s_dma_pool)
  2314. goto fail_free_nvram;
  2315. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2316. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2317. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  2318. if (!ha->dl_dma_pool) {
  2319. qla_printk(KERN_WARNING, ha,
  2320. "Memory Allocation failed - dl_dma_pool\n");
  2321. goto fail_s_dma_pool;
  2322. }
  2323. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2324. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  2325. if (!ha->fcp_cmnd_dma_pool) {
  2326. qla_printk(KERN_WARNING, ha,
  2327. "Memory Allocation failed - fcp_cmnd_dma_pool\n");
  2328. goto fail_dl_dma_pool;
  2329. }
  2330. }
  2331. /* Allocate memory for SNS commands */
  2332. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2333. /* Get consistent memory allocated for SNS commands */
  2334. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  2335. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  2336. if (!ha->sns_cmd)
  2337. goto fail_dma_pool;
  2338. } else {
  2339. /* Get consistent memory allocated for MS IOCB */
  2340. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2341. &ha->ms_iocb_dma);
  2342. if (!ha->ms_iocb)
  2343. goto fail_dma_pool;
  2344. /* Get consistent memory allocated for CT SNS commands */
  2345. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  2346. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  2347. if (!ha->ct_sns)
  2348. goto fail_free_ms_iocb;
  2349. }
  2350. /* Allocate memory for request ring */
  2351. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  2352. if (!*req) {
  2353. DEBUG(printk("Unable to allocate memory for req\n"));
  2354. goto fail_req;
  2355. }
  2356. (*req)->length = req_len;
  2357. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2358. ((*req)->length + 1) * sizeof(request_t),
  2359. &(*req)->dma, GFP_KERNEL);
  2360. if (!(*req)->ring) {
  2361. DEBUG(printk("Unable to allocate memory for req_ring\n"));
  2362. goto fail_req_ring;
  2363. }
  2364. /* Allocate memory for response ring */
  2365. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  2366. if (!*rsp) {
  2367. qla_printk(KERN_WARNING, ha,
  2368. "Unable to allocate memory for rsp\n");
  2369. goto fail_rsp;
  2370. }
  2371. (*rsp)->hw = ha;
  2372. (*rsp)->length = rsp_len;
  2373. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2374. ((*rsp)->length + 1) * sizeof(response_t),
  2375. &(*rsp)->dma, GFP_KERNEL);
  2376. if (!(*rsp)->ring) {
  2377. qla_printk(KERN_WARNING, ha,
  2378. "Unable to allocate memory for rsp_ring\n");
  2379. goto fail_rsp_ring;
  2380. }
  2381. (*req)->rsp = *rsp;
  2382. (*rsp)->req = *req;
  2383. /* Allocate memory for NVRAM data for vports */
  2384. if (ha->nvram_npiv_size) {
  2385. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  2386. ha->nvram_npiv_size, GFP_KERNEL);
  2387. if (!ha->npiv_info) {
  2388. qla_printk(KERN_WARNING, ha,
  2389. "Unable to allocate memory for npiv info\n");
  2390. goto fail_npiv_info;
  2391. }
  2392. } else
  2393. ha->npiv_info = NULL;
  2394. /* Get consistent memory allocated for EX-INIT-CB. */
  2395. if (IS_QLA8XXX_TYPE(ha)) {
  2396. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2397. &ha->ex_init_cb_dma);
  2398. if (!ha->ex_init_cb)
  2399. goto fail_ex_init_cb;
  2400. }
  2401. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  2402. /* Get consistent memory allocated for Async Port-Database. */
  2403. if (!IS_FWI2_CAPABLE(ha)) {
  2404. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2405. &ha->async_pd_dma);
  2406. if (!ha->async_pd)
  2407. goto fail_async_pd;
  2408. }
  2409. INIT_LIST_HEAD(&ha->vp_list);
  2410. return 1;
  2411. fail_async_pd:
  2412. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  2413. fail_ex_init_cb:
  2414. kfree(ha->npiv_info);
  2415. fail_npiv_info:
  2416. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  2417. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  2418. (*rsp)->ring = NULL;
  2419. (*rsp)->dma = 0;
  2420. fail_rsp_ring:
  2421. kfree(*rsp);
  2422. fail_rsp:
  2423. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  2424. sizeof(request_t), (*req)->ring, (*req)->dma);
  2425. (*req)->ring = NULL;
  2426. (*req)->dma = 0;
  2427. fail_req_ring:
  2428. kfree(*req);
  2429. fail_req:
  2430. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2431. ha->ct_sns, ha->ct_sns_dma);
  2432. ha->ct_sns = NULL;
  2433. ha->ct_sns_dma = 0;
  2434. fail_free_ms_iocb:
  2435. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2436. ha->ms_iocb = NULL;
  2437. ha->ms_iocb_dma = 0;
  2438. fail_dma_pool:
  2439. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2440. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2441. ha->fcp_cmnd_dma_pool = NULL;
  2442. }
  2443. fail_dl_dma_pool:
  2444. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2445. dma_pool_destroy(ha->dl_dma_pool);
  2446. ha->dl_dma_pool = NULL;
  2447. }
  2448. fail_s_dma_pool:
  2449. dma_pool_destroy(ha->s_dma_pool);
  2450. ha->s_dma_pool = NULL;
  2451. fail_free_nvram:
  2452. kfree(ha->nvram);
  2453. ha->nvram = NULL;
  2454. fail_free_ctx_mempool:
  2455. mempool_destroy(ha->ctx_mempool);
  2456. ha->ctx_mempool = NULL;
  2457. fail_free_srb_mempool:
  2458. mempool_destroy(ha->srb_mempool);
  2459. ha->srb_mempool = NULL;
  2460. fail_free_gid_list:
  2461. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2462. ha->gid_list_dma);
  2463. ha->gid_list = NULL;
  2464. ha->gid_list_dma = 0;
  2465. fail_free_init_cb:
  2466. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  2467. ha->init_cb_dma);
  2468. ha->init_cb = NULL;
  2469. ha->init_cb_dma = 0;
  2470. fail:
  2471. DEBUG(printk("%s: Memory allocation failure\n", __func__));
  2472. return -ENOMEM;
  2473. }
  2474. /*
  2475. * qla2x00_free_fw_dump
  2476. * Frees fw dump stuff.
  2477. *
  2478. * Input:
  2479. * ha = adapter block pointer.
  2480. */
  2481. static void
  2482. qla2x00_free_fw_dump(struct qla_hw_data *ha)
  2483. {
  2484. if (ha->fce)
  2485. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  2486. ha->fce_dma);
  2487. if (ha->fw_dump) {
  2488. if (ha->eft)
  2489. dma_free_coherent(&ha->pdev->dev,
  2490. ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
  2491. vfree(ha->fw_dump);
  2492. }
  2493. ha->fce = NULL;
  2494. ha->fce_dma = 0;
  2495. ha->eft = NULL;
  2496. ha->eft_dma = 0;
  2497. ha->fw_dump = NULL;
  2498. ha->fw_dumped = 0;
  2499. ha->fw_dump_reading = 0;
  2500. }
  2501. /*
  2502. * qla2x00_mem_free
  2503. * Frees all adapter allocated memory.
  2504. *
  2505. * Input:
  2506. * ha = adapter block pointer.
  2507. */
  2508. static void
  2509. qla2x00_mem_free(struct qla_hw_data *ha)
  2510. {
  2511. qla2x00_free_fw_dump(ha);
  2512. if (ha->srb_mempool)
  2513. mempool_destroy(ha->srb_mempool);
  2514. if (ha->dcbx_tlv)
  2515. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  2516. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  2517. if (ha->xgmac_data)
  2518. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  2519. ha->xgmac_data, ha->xgmac_data_dma);
  2520. if (ha->sns_cmd)
  2521. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  2522. ha->sns_cmd, ha->sns_cmd_dma);
  2523. if (ha->ct_sns)
  2524. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2525. ha->ct_sns, ha->ct_sns_dma);
  2526. if (ha->sfp_data)
  2527. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  2528. if (ha->edc_data)
  2529. dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
  2530. if (ha->ms_iocb)
  2531. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2532. if (ha->ex_init_cb)
  2533. dma_pool_free(ha->s_dma_pool,
  2534. ha->ex_init_cb, ha->ex_init_cb_dma);
  2535. if (ha->async_pd)
  2536. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  2537. if (ha->s_dma_pool)
  2538. dma_pool_destroy(ha->s_dma_pool);
  2539. if (ha->gid_list)
  2540. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2541. ha->gid_list_dma);
  2542. if (IS_QLA82XX(ha)) {
  2543. if (!list_empty(&ha->gbl_dsd_list)) {
  2544. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  2545. /* clean up allocated prev pool */
  2546. list_for_each_entry_safe(dsd_ptr,
  2547. tdsd_ptr, &ha->gbl_dsd_list, list) {
  2548. dma_pool_free(ha->dl_dma_pool,
  2549. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  2550. list_del(&dsd_ptr->list);
  2551. kfree(dsd_ptr);
  2552. }
  2553. }
  2554. }
  2555. if (ha->dl_dma_pool)
  2556. dma_pool_destroy(ha->dl_dma_pool);
  2557. if (ha->fcp_cmnd_dma_pool)
  2558. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2559. if (ha->ctx_mempool)
  2560. mempool_destroy(ha->ctx_mempool);
  2561. if (ha->init_cb)
  2562. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  2563. ha->init_cb, ha->init_cb_dma);
  2564. vfree(ha->optrom_buffer);
  2565. kfree(ha->nvram);
  2566. kfree(ha->npiv_info);
  2567. ha->srb_mempool = NULL;
  2568. ha->ctx_mempool = NULL;
  2569. ha->sns_cmd = NULL;
  2570. ha->sns_cmd_dma = 0;
  2571. ha->ct_sns = NULL;
  2572. ha->ct_sns_dma = 0;
  2573. ha->ms_iocb = NULL;
  2574. ha->ms_iocb_dma = 0;
  2575. ha->init_cb = NULL;
  2576. ha->init_cb_dma = 0;
  2577. ha->ex_init_cb = NULL;
  2578. ha->ex_init_cb_dma = 0;
  2579. ha->async_pd = NULL;
  2580. ha->async_pd_dma = 0;
  2581. ha->s_dma_pool = NULL;
  2582. ha->dl_dma_pool = NULL;
  2583. ha->fcp_cmnd_dma_pool = NULL;
  2584. ha->gid_list = NULL;
  2585. ha->gid_list_dma = 0;
  2586. }
  2587. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  2588. struct qla_hw_data *ha)
  2589. {
  2590. struct Scsi_Host *host;
  2591. struct scsi_qla_host *vha = NULL;
  2592. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  2593. if (host == NULL) {
  2594. printk(KERN_WARNING
  2595. "qla2xxx: Couldn't allocate host from scsi layer!\n");
  2596. goto fail;
  2597. }
  2598. /* Clear our data area */
  2599. vha = shost_priv(host);
  2600. memset(vha, 0, sizeof(scsi_qla_host_t));
  2601. vha->host = host;
  2602. vha->host_no = host->host_no;
  2603. vha->hw = ha;
  2604. INIT_LIST_HEAD(&vha->vp_fcports);
  2605. INIT_LIST_HEAD(&vha->work_list);
  2606. INIT_LIST_HEAD(&vha->list);
  2607. spin_lock_init(&vha->work_lock);
  2608. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  2609. return vha;
  2610. fail:
  2611. return vha;
  2612. }
  2613. static struct qla_work_evt *
  2614. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  2615. {
  2616. struct qla_work_evt *e;
  2617. uint8_t bail;
  2618. QLA_VHA_MARK_BUSY(vha, bail);
  2619. if (bail)
  2620. return NULL;
  2621. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  2622. if (!e) {
  2623. QLA_VHA_MARK_NOT_BUSY(vha);
  2624. return NULL;
  2625. }
  2626. INIT_LIST_HEAD(&e->list);
  2627. e->type = type;
  2628. e->flags = QLA_EVT_FLAG_FREE;
  2629. return e;
  2630. }
  2631. static int
  2632. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  2633. {
  2634. unsigned long flags;
  2635. spin_lock_irqsave(&vha->work_lock, flags);
  2636. list_add_tail(&e->list, &vha->work_list);
  2637. spin_unlock_irqrestore(&vha->work_lock, flags);
  2638. qla2xxx_wake_dpc(vha);
  2639. return QLA_SUCCESS;
  2640. }
  2641. int
  2642. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  2643. u32 data)
  2644. {
  2645. struct qla_work_evt *e;
  2646. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  2647. if (!e)
  2648. return QLA_FUNCTION_FAILED;
  2649. e->u.aen.code = code;
  2650. e->u.aen.data = data;
  2651. return qla2x00_post_work(vha, e);
  2652. }
  2653. int
  2654. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  2655. {
  2656. struct qla_work_evt *e;
  2657. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  2658. if (!e)
  2659. return QLA_FUNCTION_FAILED;
  2660. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2661. return qla2x00_post_work(vha, e);
  2662. }
  2663. #define qla2x00_post_async_work(name, type) \
  2664. int qla2x00_post_async_##name##_work( \
  2665. struct scsi_qla_host *vha, \
  2666. fc_port_t *fcport, uint16_t *data) \
  2667. { \
  2668. struct qla_work_evt *e; \
  2669. \
  2670. e = qla2x00_alloc_work(vha, type); \
  2671. if (!e) \
  2672. return QLA_FUNCTION_FAILED; \
  2673. \
  2674. e->u.logio.fcport = fcport; \
  2675. if (data) { \
  2676. e->u.logio.data[0] = data[0]; \
  2677. e->u.logio.data[1] = data[1]; \
  2678. } \
  2679. return qla2x00_post_work(vha, e); \
  2680. }
  2681. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  2682. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  2683. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  2684. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  2685. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  2686. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  2687. int
  2688. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  2689. {
  2690. struct qla_work_evt *e;
  2691. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  2692. if (!e)
  2693. return QLA_FUNCTION_FAILED;
  2694. e->u.uevent.code = code;
  2695. return qla2x00_post_work(vha, e);
  2696. }
  2697. static void
  2698. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  2699. {
  2700. char event_string[40];
  2701. char *envp[] = { event_string, NULL };
  2702. switch (code) {
  2703. case QLA_UEVENT_CODE_FW_DUMP:
  2704. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  2705. vha->host_no);
  2706. break;
  2707. default:
  2708. /* do nothing */
  2709. break;
  2710. }
  2711. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  2712. }
  2713. void
  2714. qla2x00_do_work(struct scsi_qla_host *vha)
  2715. {
  2716. struct qla_work_evt *e, *tmp;
  2717. unsigned long flags;
  2718. LIST_HEAD(work);
  2719. spin_lock_irqsave(&vha->work_lock, flags);
  2720. list_splice_init(&vha->work_list, &work);
  2721. spin_unlock_irqrestore(&vha->work_lock, flags);
  2722. list_for_each_entry_safe(e, tmp, &work, list) {
  2723. list_del_init(&e->list);
  2724. switch (e->type) {
  2725. case QLA_EVT_AEN:
  2726. fc_host_post_event(vha->host, fc_get_event_number(),
  2727. e->u.aen.code, e->u.aen.data);
  2728. break;
  2729. case QLA_EVT_IDC_ACK:
  2730. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  2731. break;
  2732. case QLA_EVT_ASYNC_LOGIN:
  2733. qla2x00_async_login(vha, e->u.logio.fcport,
  2734. e->u.logio.data);
  2735. break;
  2736. case QLA_EVT_ASYNC_LOGIN_DONE:
  2737. qla2x00_async_login_done(vha, e->u.logio.fcport,
  2738. e->u.logio.data);
  2739. break;
  2740. case QLA_EVT_ASYNC_LOGOUT:
  2741. qla2x00_async_logout(vha, e->u.logio.fcport);
  2742. break;
  2743. case QLA_EVT_ASYNC_LOGOUT_DONE:
  2744. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  2745. e->u.logio.data);
  2746. break;
  2747. case QLA_EVT_ASYNC_ADISC:
  2748. qla2x00_async_adisc(vha, e->u.logio.fcport,
  2749. e->u.logio.data);
  2750. break;
  2751. case QLA_EVT_ASYNC_ADISC_DONE:
  2752. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  2753. e->u.logio.data);
  2754. break;
  2755. case QLA_EVT_UEVENT:
  2756. qla2x00_uevent_emit(vha, e->u.uevent.code);
  2757. break;
  2758. }
  2759. if (e->flags & QLA_EVT_FLAG_FREE)
  2760. kfree(e);
  2761. /* For each work completed decrement vha ref count */
  2762. QLA_VHA_MARK_NOT_BUSY(vha);
  2763. }
  2764. }
  2765. /* Relogins all the fcports of a vport
  2766. * Context: dpc thread
  2767. */
  2768. void qla2x00_relogin(struct scsi_qla_host *vha)
  2769. {
  2770. fc_port_t *fcport;
  2771. int status;
  2772. uint16_t next_loopid = 0;
  2773. struct qla_hw_data *ha = vha->hw;
  2774. uint16_t data[2];
  2775. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2776. /*
  2777. * If the port is not ONLINE then try to login
  2778. * to it if we haven't run out of retries.
  2779. */
  2780. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  2781. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  2782. fcport->login_retry--;
  2783. if (fcport->flags & FCF_FABRIC_DEVICE) {
  2784. if (fcport->flags & FCF_FCP2_DEVICE)
  2785. ha->isp_ops->fabric_logout(vha,
  2786. fcport->loop_id,
  2787. fcport->d_id.b.domain,
  2788. fcport->d_id.b.area,
  2789. fcport->d_id.b.al_pa);
  2790. if (IS_ALOGIO_CAPABLE(ha)) {
  2791. fcport->flags |= FCF_ASYNC_SENT;
  2792. data[0] = 0;
  2793. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  2794. status = qla2x00_post_async_login_work(
  2795. vha, fcport, data);
  2796. if (status == QLA_SUCCESS)
  2797. continue;
  2798. /* Attempt a retry. */
  2799. status = 1;
  2800. } else
  2801. status = qla2x00_fabric_login(vha,
  2802. fcport, &next_loopid);
  2803. } else
  2804. status = qla2x00_local_device_login(vha,
  2805. fcport);
  2806. if (status == QLA_SUCCESS) {
  2807. fcport->old_loop_id = fcport->loop_id;
  2808. DEBUG(printk("scsi(%ld): port login OK: logged "
  2809. "in ID 0x%x\n", vha->host_no, fcport->loop_id));
  2810. qla2x00_update_fcport(vha, fcport);
  2811. } else if (status == 1) {
  2812. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2813. /* retry the login again */
  2814. DEBUG(printk("scsi(%ld): Retrying"
  2815. " %d login again loop_id 0x%x\n",
  2816. vha->host_no, fcport->login_retry,
  2817. fcport->loop_id));
  2818. } else {
  2819. fcport->login_retry = 0;
  2820. }
  2821. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  2822. fcport->loop_id = FC_NO_LOOP_ID;
  2823. }
  2824. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2825. break;
  2826. }
  2827. }
  2828. /**************************************************************************
  2829. * qla2x00_do_dpc
  2830. * This kernel thread is a task that is schedule by the interrupt handler
  2831. * to perform the background processing for interrupts.
  2832. *
  2833. * Notes:
  2834. * This task always run in the context of a kernel thread. It
  2835. * is kick-off by the driver's detect code and starts up
  2836. * up one per adapter. It immediately goes to sleep and waits for
  2837. * some fibre event. When either the interrupt handler or
  2838. * the timer routine detects a event it will one of the task
  2839. * bits then wake us up.
  2840. **************************************************************************/
  2841. static int
  2842. qla2x00_do_dpc(void *data)
  2843. {
  2844. int rval;
  2845. scsi_qla_host_t *base_vha;
  2846. struct qla_hw_data *ha;
  2847. ha = (struct qla_hw_data *)data;
  2848. base_vha = pci_get_drvdata(ha->pdev);
  2849. set_user_nice(current, -20);
  2850. set_current_state(TASK_INTERRUPTIBLE);
  2851. while (!kthread_should_stop()) {
  2852. DEBUG3(printk("qla2x00: DPC handler sleeping\n"));
  2853. schedule();
  2854. __set_current_state(TASK_RUNNING);
  2855. DEBUG3(printk("qla2x00: DPC handler waking up\n"));
  2856. /* Initialization not yet finished. Don't do anything yet. */
  2857. if (!base_vha->flags.init_done)
  2858. continue;
  2859. if (ha->flags.eeh_busy) {
  2860. DEBUG17(qla_printk(KERN_WARNING, ha,
  2861. "qla2x00_do_dpc: dpc_flags: %lx\n",
  2862. base_vha->dpc_flags));
  2863. continue;
  2864. }
  2865. DEBUG3(printk("scsi(%ld): DPC handler\n", base_vha->host_no));
  2866. ha->dpc_active = 1;
  2867. if (ha->flags.mbox_busy) {
  2868. ha->dpc_active = 0;
  2869. continue;
  2870. }
  2871. qla2x00_do_work(base_vha);
  2872. if (IS_QLA82XX(ha)) {
  2873. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  2874. &base_vha->dpc_flags)) {
  2875. qla82xx_idc_lock(ha);
  2876. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2877. QLA82XX_DEV_FAILED);
  2878. qla82xx_idc_unlock(ha);
  2879. qla_printk(KERN_INFO, ha,
  2880. "HW State: FAILED\n");
  2881. qla82xx_device_state_handler(base_vha);
  2882. continue;
  2883. }
  2884. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  2885. &base_vha->dpc_flags)) {
  2886. DEBUG(printk(KERN_INFO
  2887. "scsi(%ld): dpc: sched "
  2888. "qla82xx_fcoe_ctx_reset ha = %p\n",
  2889. base_vha->host_no, ha));
  2890. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2891. &base_vha->dpc_flags))) {
  2892. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  2893. /* FCoE-ctx reset failed.
  2894. * Escalate to chip-reset
  2895. */
  2896. set_bit(ISP_ABORT_NEEDED,
  2897. &base_vha->dpc_flags);
  2898. }
  2899. clear_bit(ABORT_ISP_ACTIVE,
  2900. &base_vha->dpc_flags);
  2901. }
  2902. DEBUG(printk("scsi(%ld): dpc:"
  2903. " qla82xx_fcoe_ctx_reset end\n",
  2904. base_vha->host_no));
  2905. }
  2906. }
  2907. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  2908. &base_vha->dpc_flags)) {
  2909. DEBUG(printk("scsi(%ld): dpc: sched "
  2910. "qla2x00_abort_isp ha = %p\n",
  2911. base_vha->host_no, ha));
  2912. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2913. &base_vha->dpc_flags))) {
  2914. if (ha->isp_ops->abort_isp(base_vha)) {
  2915. /* failed. retry later */
  2916. set_bit(ISP_ABORT_NEEDED,
  2917. &base_vha->dpc_flags);
  2918. }
  2919. clear_bit(ABORT_ISP_ACTIVE,
  2920. &base_vha->dpc_flags);
  2921. }
  2922. DEBUG(printk("scsi(%ld): dpc: qla2x00_abort_isp end\n",
  2923. base_vha->host_no));
  2924. }
  2925. if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
  2926. qla2x00_update_fcports(base_vha);
  2927. clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2928. }
  2929. if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
  2930. DEBUG(printk(KERN_INFO "scsi(%ld): dpc: sched "
  2931. "qla2x00_quiesce_needed ha = %p\n",
  2932. base_vha->host_no, ha));
  2933. qla82xx_device_state_handler(base_vha);
  2934. clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
  2935. if (!ha->flags.quiesce_owner) {
  2936. qla2x00_perform_loop_resync(base_vha);
  2937. qla82xx_idc_lock(ha);
  2938. qla82xx_clear_qsnt_ready(base_vha);
  2939. qla82xx_idc_unlock(ha);
  2940. }
  2941. }
  2942. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  2943. &base_vha->dpc_flags) &&
  2944. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  2945. DEBUG(printk("scsi(%ld): qla2x00_reset_marker()\n",
  2946. base_vha->host_no));
  2947. qla2x00_rst_aen(base_vha);
  2948. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  2949. }
  2950. /* Retry each device up to login retry count */
  2951. if ((test_and_clear_bit(RELOGIN_NEEDED,
  2952. &base_vha->dpc_flags)) &&
  2953. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  2954. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  2955. DEBUG(printk("scsi(%ld): qla2x00_port_login()\n",
  2956. base_vha->host_no));
  2957. qla2x00_relogin(base_vha);
  2958. DEBUG(printk("scsi(%ld): qla2x00_port_login - end\n",
  2959. base_vha->host_no));
  2960. }
  2961. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  2962. &base_vha->dpc_flags)) {
  2963. DEBUG(printk("scsi(%ld): qla2x00_loop_resync()\n",
  2964. base_vha->host_no));
  2965. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  2966. &base_vha->dpc_flags))) {
  2967. rval = qla2x00_loop_resync(base_vha);
  2968. clear_bit(LOOP_RESYNC_ACTIVE,
  2969. &base_vha->dpc_flags);
  2970. }
  2971. DEBUG(printk("scsi(%ld): qla2x00_loop_resync - end\n",
  2972. base_vha->host_no));
  2973. }
  2974. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  2975. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  2976. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  2977. qla2xxx_flash_npiv_conf(base_vha);
  2978. }
  2979. if (!ha->interrupts_on)
  2980. ha->isp_ops->enable_intrs(ha);
  2981. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  2982. &base_vha->dpc_flags))
  2983. ha->isp_ops->beacon_blink(base_vha);
  2984. qla2x00_do_dpc_all_vps(base_vha);
  2985. ha->dpc_active = 0;
  2986. set_current_state(TASK_INTERRUPTIBLE);
  2987. } /* End of while(1) */
  2988. __set_current_state(TASK_RUNNING);
  2989. DEBUG(printk("scsi(%ld): DPC handler exiting\n", base_vha->host_no));
  2990. /*
  2991. * Make sure that nobody tries to wake us up again.
  2992. */
  2993. ha->dpc_active = 0;
  2994. /* Cleanup any residual CTX SRBs. */
  2995. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2996. return 0;
  2997. }
  2998. void
  2999. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  3000. {
  3001. struct qla_hw_data *ha = vha->hw;
  3002. struct task_struct *t = ha->dpc_thread;
  3003. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  3004. wake_up_process(t);
  3005. }
  3006. /*
  3007. * qla2x00_rst_aen
  3008. * Processes asynchronous reset.
  3009. *
  3010. * Input:
  3011. * ha = adapter block pointer.
  3012. */
  3013. static void
  3014. qla2x00_rst_aen(scsi_qla_host_t *vha)
  3015. {
  3016. if (vha->flags.online && !vha->flags.reset_active &&
  3017. !atomic_read(&vha->loop_down_timer) &&
  3018. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  3019. do {
  3020. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3021. /*
  3022. * Issue marker command only when we are going to start
  3023. * the I/O.
  3024. */
  3025. vha->marker_needed = 1;
  3026. } while (!atomic_read(&vha->loop_down_timer) &&
  3027. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  3028. }
  3029. }
  3030. static void
  3031. qla2x00_sp_free_dma(srb_t *sp)
  3032. {
  3033. struct scsi_cmnd *cmd = sp->cmd;
  3034. struct qla_hw_data *ha = sp->fcport->vha->hw;
  3035. if (sp->flags & SRB_DMA_VALID) {
  3036. scsi_dma_unmap(cmd);
  3037. sp->flags &= ~SRB_DMA_VALID;
  3038. }
  3039. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  3040. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  3041. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  3042. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  3043. }
  3044. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  3045. /* List assured to be having elements */
  3046. qla2x00_clean_dsd_pool(ha, sp);
  3047. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  3048. }
  3049. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  3050. dma_pool_free(ha->dl_dma_pool, sp->ctx,
  3051. ((struct crc_context *)sp->ctx)->crc_ctx_dma);
  3052. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  3053. }
  3054. CMD_SP(cmd) = NULL;
  3055. }
  3056. static void
  3057. qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
  3058. {
  3059. struct scsi_cmnd *cmd = sp->cmd;
  3060. qla2x00_sp_free_dma(sp);
  3061. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  3062. struct ct6_dsd *ctx = sp->ctx;
  3063. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
  3064. ctx->fcp_cmnd_dma);
  3065. list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
  3066. ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
  3067. ha->gbl_dsd_avail += ctx->dsd_use_cnt;
  3068. mempool_free(sp->ctx, ha->ctx_mempool);
  3069. sp->ctx = NULL;
  3070. }
  3071. mempool_free(sp, ha->srb_mempool);
  3072. cmd->scsi_done(cmd);
  3073. }
  3074. void
  3075. qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
  3076. {
  3077. if (atomic_read(&sp->ref_count) == 0) {
  3078. DEBUG2(qla_printk(KERN_WARNING, ha,
  3079. "SP reference-count to ZERO -- sp=%p\n", sp));
  3080. DEBUG2(BUG());
  3081. return;
  3082. }
  3083. if (!atomic_dec_and_test(&sp->ref_count))
  3084. return;
  3085. qla2x00_sp_final_compl(ha, sp);
  3086. }
  3087. /**************************************************************************
  3088. * qla2x00_timer
  3089. *
  3090. * Description:
  3091. * One second timer
  3092. *
  3093. * Context: Interrupt
  3094. ***************************************************************************/
  3095. void
  3096. qla2x00_timer(scsi_qla_host_t *vha)
  3097. {
  3098. unsigned long cpu_flags = 0;
  3099. int start_dpc = 0;
  3100. int index;
  3101. srb_t *sp;
  3102. uint16_t w;
  3103. struct qla_hw_data *ha = vha->hw;
  3104. struct req_que *req;
  3105. if (ha->flags.eeh_busy) {
  3106. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3107. return;
  3108. }
  3109. /* Hardware read to raise pending EEH errors during mailbox waits. */
  3110. if (!pci_channel_offline(ha->pdev))
  3111. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  3112. if (IS_QLA82XX(ha)) {
  3113. if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
  3114. start_dpc++;
  3115. qla82xx_watchdog(vha);
  3116. }
  3117. /* Loop down handler. */
  3118. if (atomic_read(&vha->loop_down_timer) > 0 &&
  3119. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
  3120. && vha->flags.online) {
  3121. if (atomic_read(&vha->loop_down_timer) ==
  3122. vha->loop_down_abort_time) {
  3123. DEBUG(printk("scsi(%ld): Loop Down - aborting the "
  3124. "queues before time expire\n",
  3125. vha->host_no));
  3126. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  3127. atomic_set(&vha->loop_state, LOOP_DEAD);
  3128. /*
  3129. * Schedule an ISP abort to return any FCP2-device
  3130. * commands.
  3131. */
  3132. /* NPIV - scan physical port only */
  3133. if (!vha->vp_idx) {
  3134. spin_lock_irqsave(&ha->hardware_lock,
  3135. cpu_flags);
  3136. req = ha->req_q_map[0];
  3137. for (index = 1;
  3138. index < MAX_OUTSTANDING_COMMANDS;
  3139. index++) {
  3140. fc_port_t *sfcp;
  3141. sp = req->outstanding_cmds[index];
  3142. if (!sp)
  3143. continue;
  3144. if (sp->ctx && !IS_PROT_IO(sp))
  3145. continue;
  3146. sfcp = sp->fcport;
  3147. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  3148. continue;
  3149. set_bit(ISP_ABORT_NEEDED,
  3150. &vha->dpc_flags);
  3151. break;
  3152. }
  3153. spin_unlock_irqrestore(&ha->hardware_lock,
  3154. cpu_flags);
  3155. }
  3156. start_dpc++;
  3157. }
  3158. /* if the loop has been down for 4 minutes, reinit adapter */
  3159. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  3160. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  3161. DEBUG(printk("scsi(%ld): Loop down - "
  3162. "aborting ISP.\n",
  3163. vha->host_no));
  3164. qla_printk(KERN_WARNING, ha,
  3165. "Loop down - aborting ISP.\n");
  3166. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3167. }
  3168. }
  3169. DEBUG3(printk("scsi(%ld): Loop Down - seconds remaining %d\n",
  3170. vha->host_no,
  3171. atomic_read(&vha->loop_down_timer)));
  3172. }
  3173. /* Check if beacon LED needs to be blinked */
  3174. if (ha->beacon_blink_led == 1) {
  3175. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  3176. start_dpc++;
  3177. }
  3178. /* Process any deferred work. */
  3179. if (!list_empty(&vha->work_list))
  3180. start_dpc++;
  3181. /* Schedule the DPC routine if needed */
  3182. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  3183. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  3184. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  3185. start_dpc ||
  3186. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  3187. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  3188. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  3189. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  3190. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  3191. test_bit(RELOGIN_NEEDED, &vha->dpc_flags)))
  3192. qla2xxx_wake_dpc(vha);
  3193. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3194. }
  3195. /* Firmware interface routines. */
  3196. #define FW_BLOBS 8
  3197. #define FW_ISP21XX 0
  3198. #define FW_ISP22XX 1
  3199. #define FW_ISP2300 2
  3200. #define FW_ISP2322 3
  3201. #define FW_ISP24XX 4
  3202. #define FW_ISP25XX 5
  3203. #define FW_ISP81XX 6
  3204. #define FW_ISP82XX 7
  3205. #define FW_FILE_ISP21XX "ql2100_fw.bin"
  3206. #define FW_FILE_ISP22XX "ql2200_fw.bin"
  3207. #define FW_FILE_ISP2300 "ql2300_fw.bin"
  3208. #define FW_FILE_ISP2322 "ql2322_fw.bin"
  3209. #define FW_FILE_ISP24XX "ql2400_fw.bin"
  3210. #define FW_FILE_ISP25XX "ql2500_fw.bin"
  3211. #define FW_FILE_ISP81XX "ql8100_fw.bin"
  3212. #define FW_FILE_ISP82XX "ql8200_fw.bin"
  3213. static DEFINE_MUTEX(qla_fw_lock);
  3214. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  3215. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  3216. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  3217. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  3218. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  3219. { .name = FW_FILE_ISP24XX, },
  3220. { .name = FW_FILE_ISP25XX, },
  3221. { .name = FW_FILE_ISP81XX, },
  3222. { .name = FW_FILE_ISP82XX, },
  3223. };
  3224. struct fw_blob *
  3225. qla2x00_request_firmware(scsi_qla_host_t *vha)
  3226. {
  3227. struct qla_hw_data *ha = vha->hw;
  3228. struct fw_blob *blob;
  3229. blob = NULL;
  3230. if (IS_QLA2100(ha)) {
  3231. blob = &qla_fw_blobs[FW_ISP21XX];
  3232. } else if (IS_QLA2200(ha)) {
  3233. blob = &qla_fw_blobs[FW_ISP22XX];
  3234. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3235. blob = &qla_fw_blobs[FW_ISP2300];
  3236. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  3237. blob = &qla_fw_blobs[FW_ISP2322];
  3238. } else if (IS_QLA24XX_TYPE(ha)) {
  3239. blob = &qla_fw_blobs[FW_ISP24XX];
  3240. } else if (IS_QLA25XX(ha)) {
  3241. blob = &qla_fw_blobs[FW_ISP25XX];
  3242. } else if (IS_QLA81XX(ha)) {
  3243. blob = &qla_fw_blobs[FW_ISP81XX];
  3244. } else if (IS_QLA82XX(ha)) {
  3245. blob = &qla_fw_blobs[FW_ISP82XX];
  3246. }
  3247. mutex_lock(&qla_fw_lock);
  3248. if (blob->fw)
  3249. goto out;
  3250. if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  3251. DEBUG2(printk("scsi(%ld): Failed to load firmware image "
  3252. "(%s).\n", vha->host_no, blob->name));
  3253. blob->fw = NULL;
  3254. blob = NULL;
  3255. goto out;
  3256. }
  3257. out:
  3258. mutex_unlock(&qla_fw_lock);
  3259. return blob;
  3260. }
  3261. static void
  3262. qla2x00_release_firmware(void)
  3263. {
  3264. int idx;
  3265. mutex_lock(&qla_fw_lock);
  3266. for (idx = 0; idx < FW_BLOBS; idx++)
  3267. if (qla_fw_blobs[idx].fw)
  3268. release_firmware(qla_fw_blobs[idx].fw);
  3269. mutex_unlock(&qla_fw_lock);
  3270. }
  3271. static pci_ers_result_t
  3272. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  3273. {
  3274. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  3275. struct qla_hw_data *ha = vha->hw;
  3276. DEBUG2(qla_printk(KERN_WARNING, ha, "error_detected:state %x\n",
  3277. state));
  3278. switch (state) {
  3279. case pci_channel_io_normal:
  3280. ha->flags.eeh_busy = 0;
  3281. return PCI_ERS_RESULT_CAN_RECOVER;
  3282. case pci_channel_io_frozen:
  3283. ha->flags.eeh_busy = 1;
  3284. /* For ISP82XX complete any pending mailbox cmd */
  3285. if (IS_QLA82XX(ha)) {
  3286. ha->flags.fw_hung = 1;
  3287. if (ha->flags.mbox_busy) {
  3288. ha->flags.mbox_int = 1;
  3289. DEBUG2(qla_printk(KERN_ERR, ha,
  3290. "Due to pci channel io frozen, doing premature "
  3291. "completion of mbx command\n"));
  3292. complete(&ha->mbx_intr_comp);
  3293. }
  3294. }
  3295. qla2x00_free_irqs(vha);
  3296. pci_disable_device(pdev);
  3297. /* Return back all IOs */
  3298. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3299. return PCI_ERS_RESULT_NEED_RESET;
  3300. case pci_channel_io_perm_failure:
  3301. ha->flags.pci_channel_io_perm_failure = 1;
  3302. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  3303. return PCI_ERS_RESULT_DISCONNECT;
  3304. }
  3305. return PCI_ERS_RESULT_NEED_RESET;
  3306. }
  3307. static pci_ers_result_t
  3308. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  3309. {
  3310. int risc_paused = 0;
  3311. uint32_t stat;
  3312. unsigned long flags;
  3313. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3314. struct qla_hw_data *ha = base_vha->hw;
  3315. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3316. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  3317. if (IS_QLA82XX(ha))
  3318. return PCI_ERS_RESULT_RECOVERED;
  3319. spin_lock_irqsave(&ha->hardware_lock, flags);
  3320. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  3321. stat = RD_REG_DWORD(&reg->hccr);
  3322. if (stat & HCCR_RISC_PAUSE)
  3323. risc_paused = 1;
  3324. } else if (IS_QLA23XX(ha)) {
  3325. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  3326. if (stat & HSR_RISC_PAUSED)
  3327. risc_paused = 1;
  3328. } else if (IS_FWI2_CAPABLE(ha)) {
  3329. stat = RD_REG_DWORD(&reg24->host_status);
  3330. if (stat & HSRX_RISC_PAUSED)
  3331. risc_paused = 1;
  3332. }
  3333. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3334. if (risc_paused) {
  3335. qla_printk(KERN_INFO, ha, "RISC paused -- mmio_enabled, "
  3336. "Dumping firmware!\n");
  3337. ha->isp_ops->fw_dump(base_vha, 0);
  3338. return PCI_ERS_RESULT_NEED_RESET;
  3339. } else
  3340. return PCI_ERS_RESULT_RECOVERED;
  3341. }
  3342. uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  3343. {
  3344. uint32_t rval = QLA_FUNCTION_FAILED;
  3345. uint32_t drv_active = 0;
  3346. struct qla_hw_data *ha = base_vha->hw;
  3347. int fn;
  3348. struct pci_dev *other_pdev = NULL;
  3349. DEBUG17(qla_printk(KERN_INFO, ha,
  3350. "scsi(%ld): In qla82xx_error_recovery\n", base_vha->host_no));
  3351. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3352. if (base_vha->flags.online) {
  3353. /* Abort all outstanding commands,
  3354. * so as to be requeued later */
  3355. qla2x00_abort_isp_cleanup(base_vha);
  3356. }
  3357. fn = PCI_FUNC(ha->pdev->devfn);
  3358. while (fn > 0) {
  3359. fn--;
  3360. DEBUG17(qla_printk(KERN_INFO, ha,
  3361. "Finding pci device at function = 0x%x\n", fn));
  3362. other_pdev =
  3363. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  3364. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  3365. fn));
  3366. if (!other_pdev)
  3367. continue;
  3368. if (atomic_read(&other_pdev->enable_cnt)) {
  3369. DEBUG17(qla_printk(KERN_INFO, ha,
  3370. "Found PCI func availabe and enabled at 0x%x\n",
  3371. fn));
  3372. pci_dev_put(other_pdev);
  3373. break;
  3374. }
  3375. pci_dev_put(other_pdev);
  3376. }
  3377. if (!fn) {
  3378. /* Reset owner */
  3379. DEBUG17(qla_printk(KERN_INFO, ha,
  3380. "This devfn is reset owner = 0x%x\n", ha->pdev->devfn));
  3381. qla82xx_idc_lock(ha);
  3382. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3383. QLA82XX_DEV_INITIALIZING);
  3384. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  3385. QLA82XX_IDC_VERSION);
  3386. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  3387. DEBUG17(qla_printk(KERN_INFO, ha,
  3388. "drv_active = 0x%x\n", drv_active));
  3389. qla82xx_idc_unlock(ha);
  3390. /* Reset if device is not already reset
  3391. * drv_active would be 0 if a reset has already been done
  3392. */
  3393. if (drv_active)
  3394. rval = qla82xx_start_firmware(base_vha);
  3395. else
  3396. rval = QLA_SUCCESS;
  3397. qla82xx_idc_lock(ha);
  3398. if (rval != QLA_SUCCESS) {
  3399. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  3400. qla82xx_clear_drv_active(ha);
  3401. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3402. QLA82XX_DEV_FAILED);
  3403. } else {
  3404. qla_printk(KERN_INFO, ha, "HW State: READY\n");
  3405. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3406. QLA82XX_DEV_READY);
  3407. qla82xx_idc_unlock(ha);
  3408. ha->flags.fw_hung = 0;
  3409. rval = qla82xx_restart_isp(base_vha);
  3410. qla82xx_idc_lock(ha);
  3411. /* Clear driver state register */
  3412. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  3413. qla82xx_set_drv_active(base_vha);
  3414. }
  3415. qla82xx_idc_unlock(ha);
  3416. } else {
  3417. DEBUG17(qla_printk(KERN_INFO, ha,
  3418. "This devfn is not reset owner = 0x%x\n", ha->pdev->devfn));
  3419. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  3420. QLA82XX_DEV_READY)) {
  3421. ha->flags.fw_hung = 0;
  3422. rval = qla82xx_restart_isp(base_vha);
  3423. qla82xx_idc_lock(ha);
  3424. qla82xx_set_drv_active(base_vha);
  3425. qla82xx_idc_unlock(ha);
  3426. }
  3427. }
  3428. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3429. return rval;
  3430. }
  3431. static pci_ers_result_t
  3432. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  3433. {
  3434. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  3435. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3436. struct qla_hw_data *ha = base_vha->hw;
  3437. struct rsp_que *rsp;
  3438. int rc, retries = 10;
  3439. DEBUG17(qla_printk(KERN_WARNING, ha, "slot_reset\n"));
  3440. /* Workaround: qla2xxx driver which access hardware earlier
  3441. * needs error state to be pci_channel_io_online.
  3442. * Otherwise mailbox command timesout.
  3443. */
  3444. pdev->error_state = pci_channel_io_normal;
  3445. pci_restore_state(pdev);
  3446. /* pci_restore_state() clears the saved_state flag of the device
  3447. * save restored state which resets saved_state flag
  3448. */
  3449. pci_save_state(pdev);
  3450. if (ha->mem_only)
  3451. rc = pci_enable_device_mem(pdev);
  3452. else
  3453. rc = pci_enable_device(pdev);
  3454. if (rc) {
  3455. qla_printk(KERN_WARNING, ha,
  3456. "Can't re-enable PCI device after reset.\n");
  3457. goto exit_slot_reset;
  3458. }
  3459. rsp = ha->rsp_q_map[0];
  3460. if (qla2x00_request_irqs(ha, rsp))
  3461. goto exit_slot_reset;
  3462. if (ha->isp_ops->pci_config(base_vha))
  3463. goto exit_slot_reset;
  3464. if (IS_QLA82XX(ha)) {
  3465. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  3466. ret = PCI_ERS_RESULT_RECOVERED;
  3467. goto exit_slot_reset;
  3468. } else
  3469. goto exit_slot_reset;
  3470. }
  3471. while (ha->flags.mbox_busy && retries--)
  3472. msleep(1000);
  3473. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3474. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  3475. ret = PCI_ERS_RESULT_RECOVERED;
  3476. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3477. exit_slot_reset:
  3478. DEBUG17(qla_printk(KERN_WARNING, ha,
  3479. "slot_reset-return:ret=%x\n", ret));
  3480. return ret;
  3481. }
  3482. static void
  3483. qla2xxx_pci_resume(struct pci_dev *pdev)
  3484. {
  3485. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3486. struct qla_hw_data *ha = base_vha->hw;
  3487. int ret;
  3488. DEBUG17(qla_printk(KERN_WARNING, ha, "pci_resume\n"));
  3489. ret = qla2x00_wait_for_hba_online(base_vha);
  3490. if (ret != QLA_SUCCESS) {
  3491. qla_printk(KERN_ERR, ha,
  3492. "the device failed to resume I/O "
  3493. "from slot/link_reset");
  3494. }
  3495. pci_cleanup_aer_uncorrect_error_status(pdev);
  3496. ha->flags.eeh_busy = 0;
  3497. }
  3498. static struct pci_error_handlers qla2xxx_err_handler = {
  3499. .error_detected = qla2xxx_pci_error_detected,
  3500. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  3501. .slot_reset = qla2xxx_pci_slot_reset,
  3502. .resume = qla2xxx_pci_resume,
  3503. };
  3504. static struct pci_device_id qla2xxx_pci_tbl[] = {
  3505. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  3506. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  3507. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  3508. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  3509. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  3510. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  3511. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  3512. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  3513. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  3514. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  3515. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  3516. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  3517. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  3518. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  3519. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  3520. { 0 },
  3521. };
  3522. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  3523. static struct pci_driver qla2xxx_pci_driver = {
  3524. .name = QLA2XXX_DRIVER_NAME,
  3525. .driver = {
  3526. .owner = THIS_MODULE,
  3527. },
  3528. .id_table = qla2xxx_pci_tbl,
  3529. .probe = qla2x00_probe_one,
  3530. .remove = qla2x00_remove_one,
  3531. .shutdown = qla2x00_shutdown,
  3532. .err_handler = &qla2xxx_err_handler,
  3533. };
  3534. static struct file_operations apidev_fops = {
  3535. .owner = THIS_MODULE,
  3536. .llseek = noop_llseek,
  3537. };
  3538. /**
  3539. * qla2x00_module_init - Module initialization.
  3540. **/
  3541. static int __init
  3542. qla2x00_module_init(void)
  3543. {
  3544. int ret = 0;
  3545. /* Allocate cache for SRBs. */
  3546. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  3547. SLAB_HWCACHE_ALIGN, NULL);
  3548. if (srb_cachep == NULL) {
  3549. printk(KERN_ERR
  3550. "qla2xxx: Unable to allocate SRB cache...Failing load!\n");
  3551. return -ENOMEM;
  3552. }
  3553. /* Derive version string. */
  3554. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  3555. if (ql2xextended_error_logging)
  3556. strcat(qla2x00_version_str, "-debug");
  3557. qla2xxx_transport_template =
  3558. fc_attach_transport(&qla2xxx_transport_functions);
  3559. if (!qla2xxx_transport_template) {
  3560. kmem_cache_destroy(srb_cachep);
  3561. return -ENODEV;
  3562. }
  3563. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  3564. if (apidev_major < 0) {
  3565. printk(KERN_WARNING "qla2xxx: Unable to register char device "
  3566. "%s\n", QLA2XXX_APIDEV);
  3567. }
  3568. qla2xxx_transport_vport_template =
  3569. fc_attach_transport(&qla2xxx_transport_vport_functions);
  3570. if (!qla2xxx_transport_vport_template) {
  3571. kmem_cache_destroy(srb_cachep);
  3572. fc_release_transport(qla2xxx_transport_template);
  3573. return -ENODEV;
  3574. }
  3575. printk(KERN_INFO "QLogic Fibre Channel HBA Driver: %s\n",
  3576. qla2x00_version_str);
  3577. ret = pci_register_driver(&qla2xxx_pci_driver);
  3578. if (ret) {
  3579. kmem_cache_destroy(srb_cachep);
  3580. fc_release_transport(qla2xxx_transport_template);
  3581. fc_release_transport(qla2xxx_transport_vport_template);
  3582. }
  3583. return ret;
  3584. }
  3585. /**
  3586. * qla2x00_module_exit - Module cleanup.
  3587. **/
  3588. static void __exit
  3589. qla2x00_module_exit(void)
  3590. {
  3591. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  3592. pci_unregister_driver(&qla2xxx_pci_driver);
  3593. qla2x00_release_firmware();
  3594. kmem_cache_destroy(srb_cachep);
  3595. if (ctx_cachep)
  3596. kmem_cache_destroy(ctx_cachep);
  3597. fc_release_transport(qla2xxx_transport_template);
  3598. fc_release_transport(qla2xxx_transport_vport_template);
  3599. }
  3600. module_init(qla2x00_module_init);
  3601. module_exit(qla2x00_module_exit);
  3602. MODULE_AUTHOR("QLogic Corporation");
  3603. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  3604. MODULE_LICENSE("GPL");
  3605. MODULE_VERSION(QLA2XXX_VERSION);
  3606. MODULE_FIRMWARE(FW_FILE_ISP21XX);
  3607. MODULE_FIRMWARE(FW_FILE_ISP22XX);
  3608. MODULE_FIRMWARE(FW_FILE_ISP2300);
  3609. MODULE_FIRMWARE(FW_FILE_ISP2322);
  3610. MODULE_FIRMWARE(FW_FILE_ISP24XX);
  3611. MODULE_FIRMWARE(FW_FILE_ISP25XX);