netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR (0xffffffff)
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  50. uint32_t ctx, uint32_t ringid);
  51. #if 0
  52. static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  53. unsigned long off, int *data)
  54. {
  55. void __iomem *addr = pci_base_offset(adapter, off);
  56. writel(*data, addr);
  57. }
  58. #endif /* 0 */
  59. static void crb_addr_transform_setup(void)
  60. {
  61. crb_addr_transform(XDMA);
  62. crb_addr_transform(TIMR);
  63. crb_addr_transform(SRE);
  64. crb_addr_transform(SQN3);
  65. crb_addr_transform(SQN2);
  66. crb_addr_transform(SQN1);
  67. crb_addr_transform(SQN0);
  68. crb_addr_transform(SQS3);
  69. crb_addr_transform(SQS2);
  70. crb_addr_transform(SQS1);
  71. crb_addr_transform(SQS0);
  72. crb_addr_transform(RPMX7);
  73. crb_addr_transform(RPMX6);
  74. crb_addr_transform(RPMX5);
  75. crb_addr_transform(RPMX4);
  76. crb_addr_transform(RPMX3);
  77. crb_addr_transform(RPMX2);
  78. crb_addr_transform(RPMX1);
  79. crb_addr_transform(RPMX0);
  80. crb_addr_transform(ROMUSB);
  81. crb_addr_transform(SN);
  82. crb_addr_transform(QMN);
  83. crb_addr_transform(QMS);
  84. crb_addr_transform(PGNI);
  85. crb_addr_transform(PGND);
  86. crb_addr_transform(PGN3);
  87. crb_addr_transform(PGN2);
  88. crb_addr_transform(PGN1);
  89. crb_addr_transform(PGN0);
  90. crb_addr_transform(PGSI);
  91. crb_addr_transform(PGSD);
  92. crb_addr_transform(PGS3);
  93. crb_addr_transform(PGS2);
  94. crb_addr_transform(PGS1);
  95. crb_addr_transform(PGS0);
  96. crb_addr_transform(PS);
  97. crb_addr_transform(PH);
  98. crb_addr_transform(NIU);
  99. crb_addr_transform(I2Q);
  100. crb_addr_transform(EG);
  101. crb_addr_transform(MN);
  102. crb_addr_transform(MS);
  103. crb_addr_transform(CAS2);
  104. crb_addr_transform(CAS1);
  105. crb_addr_transform(CAS0);
  106. crb_addr_transform(CAM);
  107. crb_addr_transform(C2C1);
  108. crb_addr_transform(C2C0);
  109. crb_addr_transform(SMB);
  110. crb_addr_transform(OCM0);
  111. crb_addr_transform(I2C0);
  112. }
  113. int netxen_init_firmware(struct netxen_adapter *adapter)
  114. {
  115. u32 state = 0, loops = 0, err = 0;
  116. /* Window 1 call */
  117. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  118. if (state == PHAN_INITIALIZE_ACK)
  119. return 0;
  120. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  121. msleep(1);
  122. /* Window 1 call */
  123. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  124. loops++;
  125. }
  126. if (loops >= 2000) {
  127. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  128. state);
  129. err = -EIO;
  130. return err;
  131. }
  132. /* Window 1 call */
  133. adapter->pci_write_normalize(adapter,
  134. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  135. adapter->pci_write_normalize(adapter,
  136. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  137. adapter->pci_write_normalize(adapter,
  138. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  139. adapter->pci_write_normalize(adapter,
  140. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  141. return err;
  142. }
  143. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  144. {
  145. struct netxen_recv_context *recv_ctx;
  146. struct nx_host_rds_ring *rds_ring;
  147. struct netxen_rx_buffer *rx_buf;
  148. int i, ctxid, ring;
  149. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  150. recv_ctx = &adapter->recv_ctx[ctxid];
  151. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  152. rds_ring = &recv_ctx->rds_rings[ring];
  153. for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
  154. rx_buf = &(rds_ring->rx_buf_arr[i]);
  155. if (rx_buf->state == NETXEN_BUFFER_FREE)
  156. continue;
  157. pci_unmap_single(adapter->pdev,
  158. rx_buf->dma,
  159. rds_ring->dma_size,
  160. PCI_DMA_FROMDEVICE);
  161. if (rx_buf->skb != NULL)
  162. dev_kfree_skb_any(rx_buf->skb);
  163. }
  164. }
  165. }
  166. }
  167. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  168. {
  169. struct netxen_cmd_buffer *cmd_buf;
  170. struct netxen_skb_frag *buffrag;
  171. int i, j;
  172. cmd_buf = adapter->cmd_buf_arr;
  173. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  174. buffrag = cmd_buf->frag_array;
  175. if (buffrag->dma) {
  176. pci_unmap_single(adapter->pdev, buffrag->dma,
  177. buffrag->length, PCI_DMA_TODEVICE);
  178. buffrag->dma = 0ULL;
  179. }
  180. for (j = 0; j < cmd_buf->frag_count; j++) {
  181. buffrag++;
  182. if (buffrag->dma) {
  183. pci_unmap_page(adapter->pdev, buffrag->dma,
  184. buffrag->length,
  185. PCI_DMA_TODEVICE);
  186. buffrag->dma = 0ULL;
  187. }
  188. }
  189. /* Free the skb we received in netxen_nic_xmit_frame */
  190. if (cmd_buf->skb) {
  191. dev_kfree_skb_any(cmd_buf->skb);
  192. cmd_buf->skb = NULL;
  193. }
  194. cmd_buf++;
  195. }
  196. }
  197. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  198. {
  199. struct netxen_recv_context *recv_ctx;
  200. struct nx_host_rds_ring *rds_ring;
  201. int ctx, ring;
  202. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  203. recv_ctx = &adapter->recv_ctx[ctx];
  204. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  205. rds_ring = &recv_ctx->rds_rings[ring];
  206. if (rds_ring->rx_buf_arr) {
  207. vfree(rds_ring->rx_buf_arr);
  208. rds_ring->rx_buf_arr = NULL;
  209. }
  210. }
  211. }
  212. if (adapter->cmd_buf_arr)
  213. vfree(adapter->cmd_buf_arr);
  214. return;
  215. }
  216. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  217. {
  218. struct netxen_recv_context *recv_ctx;
  219. struct nx_host_rds_ring *rds_ring;
  220. struct netxen_rx_buffer *rx_buf;
  221. int ctx, ring, i, num_rx_bufs;
  222. struct netxen_cmd_buffer *cmd_buf_arr;
  223. struct net_device *netdev = adapter->netdev;
  224. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  225. if (cmd_buf_arr == NULL) {
  226. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  227. netdev->name);
  228. return -ENOMEM;
  229. }
  230. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  231. adapter->cmd_buf_arr = cmd_buf_arr;
  232. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  233. recv_ctx = &adapter->recv_ctx[ctx];
  234. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  235. rds_ring = &recv_ctx->rds_rings[ring];
  236. switch (RCV_DESC_TYPE(ring)) {
  237. case RCV_DESC_NORMAL:
  238. rds_ring->max_rx_desc_count =
  239. adapter->max_rx_desc_count;
  240. rds_ring->flags = RCV_DESC_NORMAL;
  241. if (adapter->ahw.cut_through) {
  242. rds_ring->dma_size =
  243. NX_CT_DEFAULT_RX_BUF_LEN;
  244. rds_ring->skb_size =
  245. NX_CT_DEFAULT_RX_BUF_LEN;
  246. } else {
  247. rds_ring->dma_size = RX_DMA_MAP_LEN;
  248. rds_ring->skb_size =
  249. MAX_RX_BUFFER_LENGTH;
  250. }
  251. break;
  252. case RCV_DESC_JUMBO:
  253. rds_ring->max_rx_desc_count =
  254. adapter->max_jumbo_rx_desc_count;
  255. rds_ring->flags = RCV_DESC_JUMBO;
  256. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  257. rds_ring->dma_size =
  258. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  259. else
  260. rds_ring->dma_size =
  261. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  262. rds_ring->skb_size =
  263. rds_ring->dma_size + NET_IP_ALIGN;
  264. break;
  265. case RCV_RING_LRO:
  266. rds_ring->max_rx_desc_count =
  267. adapter->max_lro_rx_desc_count;
  268. rds_ring->flags = RCV_DESC_LRO;
  269. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  270. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  271. break;
  272. }
  273. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  274. vmalloc(RCV_BUFFSIZE);
  275. if (rds_ring->rx_buf_arr == NULL) {
  276. printk(KERN_ERR "%s: Failed to allocate "
  277. "rx buffer ring %d\n",
  278. netdev->name, ring);
  279. /* free whatever was already allocated */
  280. goto err_out;
  281. }
  282. memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
  283. INIT_LIST_HEAD(&rds_ring->free_list);
  284. rds_ring->begin_alloc = 0;
  285. /*
  286. * Now go through all of them, set reference handles
  287. * and put them in the queues.
  288. */
  289. num_rx_bufs = rds_ring->max_rx_desc_count;
  290. rx_buf = rds_ring->rx_buf_arr;
  291. for (i = 0; i < num_rx_bufs; i++) {
  292. list_add_tail(&rx_buf->list,
  293. &rds_ring->free_list);
  294. rx_buf->ref_handle = i;
  295. rx_buf->state = NETXEN_BUFFER_FREE;
  296. rx_buf++;
  297. }
  298. }
  299. }
  300. return 0;
  301. err_out:
  302. netxen_free_sw_resources(adapter);
  303. return -ENOMEM;
  304. }
  305. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  306. {
  307. switch (adapter->ahw.board_type) {
  308. case NETXEN_NIC_GBE:
  309. adapter->enable_phy_interrupts =
  310. netxen_niu_gbe_enable_phy_interrupts;
  311. adapter->disable_phy_interrupts =
  312. netxen_niu_gbe_disable_phy_interrupts;
  313. adapter->macaddr_set = netxen_niu_macaddr_set;
  314. adapter->set_mtu = netxen_nic_set_mtu_gb;
  315. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  316. adapter->phy_read = netxen_niu_gbe_phy_read;
  317. adapter->phy_write = netxen_niu_gbe_phy_write;
  318. adapter->init_port = netxen_niu_gbe_init_port;
  319. adapter->stop_port = netxen_niu_disable_gbe_port;
  320. break;
  321. case NETXEN_NIC_XGBE:
  322. adapter->enable_phy_interrupts =
  323. netxen_niu_xgbe_enable_phy_interrupts;
  324. adapter->disable_phy_interrupts =
  325. netxen_niu_xgbe_disable_phy_interrupts;
  326. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  327. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  328. adapter->init_port = netxen_niu_xg_init_port;
  329. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  330. adapter->stop_port = netxen_niu_disable_xg_port;
  331. break;
  332. default:
  333. break;
  334. }
  335. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  336. adapter->set_mtu = nx_fw_cmd_set_mtu;
  337. adapter->set_promisc = netxen_p3_nic_set_promisc;
  338. }
  339. }
  340. /*
  341. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  342. * address to external PCI CRB address.
  343. */
  344. static u32 netxen_decode_crb_addr(u32 addr)
  345. {
  346. int i;
  347. u32 base_addr, offset, pci_base;
  348. crb_addr_transform_setup();
  349. pci_base = NETXEN_ADDR_ERROR;
  350. base_addr = addr & 0xfff00000;
  351. offset = addr & 0x000fffff;
  352. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  353. if (crb_addr_xform[i] == base_addr) {
  354. pci_base = i << 20;
  355. break;
  356. }
  357. }
  358. if (pci_base == NETXEN_ADDR_ERROR)
  359. return pci_base;
  360. else
  361. return (pci_base + offset);
  362. }
  363. static long rom_max_timeout = 100;
  364. static long rom_lock_timeout = 10000;
  365. #if 0
  366. static long rom_write_timeout = 700;
  367. #endif
  368. static int rom_lock(struct netxen_adapter *adapter)
  369. {
  370. int iter;
  371. u32 done = 0;
  372. int timeout = 0;
  373. while (!done) {
  374. /* acquire semaphore2 from PCI HW block */
  375. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  376. &done);
  377. if (done == 1)
  378. break;
  379. if (timeout >= rom_lock_timeout)
  380. return -EIO;
  381. timeout++;
  382. /*
  383. * Yield CPU
  384. */
  385. if (!in_atomic())
  386. schedule();
  387. else {
  388. for (iter = 0; iter < 20; iter++)
  389. cpu_relax(); /*This a nop instr on i386 */
  390. }
  391. }
  392. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  393. return 0;
  394. }
  395. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  396. {
  397. long timeout = 0;
  398. long done = 0;
  399. cond_resched();
  400. while (done == 0) {
  401. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  402. done &= 2;
  403. timeout++;
  404. if (timeout >= rom_max_timeout) {
  405. printk("Timeout reached waiting for rom done");
  406. return -EIO;
  407. }
  408. }
  409. return 0;
  410. }
  411. #if 0
  412. static int netxen_rom_wren(struct netxen_adapter *adapter)
  413. {
  414. /* Set write enable latch in ROM status register */
  415. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  416. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  417. M25P_INSTR_WREN);
  418. if (netxen_wait_rom_done(adapter)) {
  419. return -1;
  420. }
  421. return 0;
  422. }
  423. static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  424. unsigned int addr)
  425. {
  426. unsigned int data = 0xdeaddead;
  427. data = netxen_nic_reg_read(adapter, addr);
  428. return data;
  429. }
  430. static int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  431. {
  432. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  433. M25P_INSTR_RDSR);
  434. if (netxen_wait_rom_done(adapter)) {
  435. return -1;
  436. }
  437. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  438. }
  439. #endif
  440. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  441. {
  442. u32 val;
  443. /* release semaphore2 */
  444. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  445. }
  446. #if 0
  447. static int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  448. {
  449. long timeout = 0;
  450. long wip = 1;
  451. int val;
  452. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  453. while (wip != 0) {
  454. val = netxen_do_rom_rdsr(adapter);
  455. wip = val & 1;
  456. timeout++;
  457. if (timeout > rom_max_timeout) {
  458. return -1;
  459. }
  460. }
  461. return 0;
  462. }
  463. static int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  464. int data)
  465. {
  466. if (netxen_rom_wren(adapter)) {
  467. return -1;
  468. }
  469. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  470. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  471. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  472. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  473. M25P_INSTR_PP);
  474. if (netxen_wait_rom_done(adapter)) {
  475. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  476. return -1;
  477. }
  478. return netxen_rom_wip_poll(adapter);
  479. }
  480. #endif
  481. static int do_rom_fast_read(struct netxen_adapter *adapter,
  482. int addr, int *valp)
  483. {
  484. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  485. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  486. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  487. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  488. if (netxen_wait_rom_done(adapter)) {
  489. printk("Error waiting for rom done\n");
  490. return -EIO;
  491. }
  492. /* reset abyte_cnt and dummy_byte_cnt */
  493. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  494. udelay(10);
  495. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  496. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  497. return 0;
  498. }
  499. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  500. u8 *bytes, size_t size)
  501. {
  502. int addridx;
  503. int ret = 0;
  504. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  505. int v;
  506. ret = do_rom_fast_read(adapter, addridx, &v);
  507. if (ret != 0)
  508. break;
  509. *(__le32 *)bytes = cpu_to_le32(v);
  510. bytes += 4;
  511. }
  512. return ret;
  513. }
  514. int
  515. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  516. u8 *bytes, size_t size)
  517. {
  518. int ret;
  519. ret = rom_lock(adapter);
  520. if (ret < 0)
  521. return ret;
  522. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  523. netxen_rom_unlock(adapter);
  524. return ret;
  525. }
  526. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  527. {
  528. int ret;
  529. if (rom_lock(adapter) != 0)
  530. return -EIO;
  531. ret = do_rom_fast_read(adapter, addr, valp);
  532. netxen_rom_unlock(adapter);
  533. return ret;
  534. }
  535. #if 0
  536. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  537. {
  538. int ret = 0;
  539. if (rom_lock(adapter) != 0) {
  540. return -1;
  541. }
  542. ret = do_rom_fast_write(adapter, addr, data);
  543. netxen_rom_unlock(adapter);
  544. return ret;
  545. }
  546. static int do_rom_fast_write_words(struct netxen_adapter *adapter,
  547. int addr, u8 *bytes, size_t size)
  548. {
  549. int addridx = addr;
  550. int ret = 0;
  551. while (addridx < (addr + size)) {
  552. int last_attempt = 0;
  553. int timeout = 0;
  554. int data;
  555. data = le32_to_cpu((*(__le32*)bytes));
  556. ret = do_rom_fast_write(adapter, addridx, data);
  557. if (ret < 0)
  558. return ret;
  559. while(1) {
  560. int data1;
  561. ret = do_rom_fast_read(adapter, addridx, &data1);
  562. if (ret < 0)
  563. return ret;
  564. if (data1 == data)
  565. break;
  566. if (timeout++ >= rom_write_timeout) {
  567. if (last_attempt++ < 4) {
  568. ret = do_rom_fast_write(adapter,
  569. addridx, data);
  570. if (ret < 0)
  571. return ret;
  572. }
  573. else {
  574. printk(KERN_INFO "Data write did not "
  575. "succeed at address 0x%x\n", addridx);
  576. break;
  577. }
  578. }
  579. }
  580. bytes += 4;
  581. addridx += 4;
  582. }
  583. return ret;
  584. }
  585. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  586. u8 *bytes, size_t size)
  587. {
  588. int ret = 0;
  589. ret = rom_lock(adapter);
  590. if (ret < 0)
  591. return ret;
  592. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  593. netxen_rom_unlock(adapter);
  594. return ret;
  595. }
  596. static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  597. {
  598. int ret;
  599. ret = netxen_rom_wren(adapter);
  600. if (ret < 0)
  601. return ret;
  602. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  603. netxen_crb_writelit_adapter(adapter,
  604. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  605. ret = netxen_wait_rom_done(adapter);
  606. if (ret < 0)
  607. return ret;
  608. return netxen_rom_wip_poll(adapter);
  609. }
  610. static int netxen_rom_rdsr(struct netxen_adapter *adapter)
  611. {
  612. int ret;
  613. ret = rom_lock(adapter);
  614. if (ret < 0)
  615. return ret;
  616. ret = netxen_do_rom_rdsr(adapter);
  617. netxen_rom_unlock(adapter);
  618. return ret;
  619. }
  620. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  621. {
  622. int ret = FLASH_SUCCESS;
  623. int val;
  624. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  625. if (!buffer)
  626. return -ENOMEM;
  627. /* unlock sector 63 */
  628. val = netxen_rom_rdsr(adapter);
  629. val = val & 0xe3;
  630. ret = netxen_rom_wrsr(adapter, val);
  631. if (ret != FLASH_SUCCESS)
  632. goto out_kfree;
  633. ret = netxen_rom_wip_poll(adapter);
  634. if (ret != FLASH_SUCCESS)
  635. goto out_kfree;
  636. /* copy sector 0 to sector 63 */
  637. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  638. buffer, NETXEN_FLASH_SECTOR_SIZE);
  639. if (ret != FLASH_SUCCESS)
  640. goto out_kfree;
  641. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  642. buffer, NETXEN_FLASH_SECTOR_SIZE);
  643. if (ret != FLASH_SUCCESS)
  644. goto out_kfree;
  645. /* lock sector 63 */
  646. val = netxen_rom_rdsr(adapter);
  647. if (!(val & 0x8)) {
  648. val |= (0x1 << 2);
  649. /* lock sector 63 */
  650. if (netxen_rom_wrsr(adapter, val) == 0) {
  651. ret = netxen_rom_wip_poll(adapter);
  652. if (ret != FLASH_SUCCESS)
  653. goto out_kfree;
  654. /* lock SR writes */
  655. ret = netxen_rom_wip_poll(adapter);
  656. if (ret != FLASH_SUCCESS)
  657. goto out_kfree;
  658. }
  659. }
  660. out_kfree:
  661. kfree(buffer);
  662. return ret;
  663. }
  664. static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  665. {
  666. netxen_rom_wren(adapter);
  667. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  668. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  669. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  670. M25P_INSTR_SE);
  671. if (netxen_wait_rom_done(adapter)) {
  672. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  673. return -1;
  674. }
  675. return netxen_rom_wip_poll(adapter);
  676. }
  677. static void check_erased_flash(struct netxen_adapter *adapter, int addr)
  678. {
  679. int i;
  680. int val;
  681. int count = 0, erased_errors = 0;
  682. int range;
  683. range = (addr == NETXEN_USER_START) ?
  684. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  685. for (i = addr; i < range; i += 4) {
  686. netxen_rom_fast_read(adapter, i, &val);
  687. if (val != 0xffffffff)
  688. erased_errors++;
  689. count++;
  690. }
  691. if (erased_errors)
  692. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  693. "for sector address: %x\n", erased_errors, count, addr);
  694. }
  695. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  696. {
  697. int ret = 0;
  698. if (rom_lock(adapter) != 0) {
  699. return -1;
  700. }
  701. ret = netxen_do_rom_se(adapter, addr);
  702. netxen_rom_unlock(adapter);
  703. msleep(30);
  704. check_erased_flash(adapter, addr);
  705. return ret;
  706. }
  707. static int netxen_flash_erase_sections(struct netxen_adapter *adapter,
  708. int start, int end)
  709. {
  710. int ret = FLASH_SUCCESS;
  711. int i;
  712. for (i = start; i < end; i++) {
  713. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  714. if (ret)
  715. break;
  716. ret = netxen_rom_wip_poll(adapter);
  717. if (ret < 0)
  718. return ret;
  719. }
  720. return ret;
  721. }
  722. int
  723. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  724. {
  725. int ret = FLASH_SUCCESS;
  726. int start, end;
  727. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  728. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  729. ret = netxen_flash_erase_sections(adapter, start, end);
  730. return ret;
  731. }
  732. int
  733. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  734. {
  735. int ret = FLASH_SUCCESS;
  736. int start, end;
  737. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  738. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  739. ret = netxen_flash_erase_sections(adapter, start, end);
  740. return ret;
  741. }
  742. void netxen_halt_pegs(struct netxen_adapter *adapter)
  743. {
  744. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  745. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  746. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  747. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  748. }
  749. int netxen_flash_unlock(struct netxen_adapter *adapter)
  750. {
  751. int ret = 0;
  752. ret = netxen_rom_wrsr(adapter, 0);
  753. if (ret < 0)
  754. return ret;
  755. ret = netxen_rom_wren(adapter);
  756. if (ret < 0)
  757. return ret;
  758. return ret;
  759. }
  760. #endif /* 0 */
  761. #define NETXEN_BOARDTYPE 0x4008
  762. #define NETXEN_BOARDNUM 0x400c
  763. #define NETXEN_CHIPNUM 0x4010
  764. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  765. {
  766. int addr, val;
  767. int i, n, init_delay = 0;
  768. struct crb_addr_pair *buf;
  769. unsigned offset;
  770. u32 off;
  771. /* resetall */
  772. rom_lock(adapter);
  773. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  774. 0xffffffff);
  775. netxen_rom_unlock(adapter);
  776. if (verbose) {
  777. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  778. printk("P2 ROM board type: 0x%08x\n", val);
  779. else
  780. printk("Could not read board type\n");
  781. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  782. printk("P2 ROM board num: 0x%08x\n", val);
  783. else
  784. printk("Could not read board number\n");
  785. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  786. printk("P2 ROM chip num: 0x%08x\n", val);
  787. else
  788. printk("Could not read chip number\n");
  789. }
  790. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  791. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  792. (n != 0xcafecafe) ||
  793. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  794. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  795. "n: %08x\n", netxen_nic_driver_name, n);
  796. return -EIO;
  797. }
  798. offset = n & 0xffffU;
  799. n = (n >> 16) & 0xffffU;
  800. } else {
  801. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  802. !(n & 0x80000000)) {
  803. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  804. "n: %08x\n", netxen_nic_driver_name, n);
  805. return -EIO;
  806. }
  807. offset = 1;
  808. n &= ~0x80000000;
  809. }
  810. if (n < 1024) {
  811. if (verbose)
  812. printk(KERN_DEBUG "%s: %d CRB init values found"
  813. " in ROM.\n", netxen_nic_driver_name, n);
  814. } else {
  815. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  816. " initialized.\n", __func__, n);
  817. return -EIO;
  818. }
  819. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  820. if (buf == NULL) {
  821. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  822. netxen_nic_driver_name);
  823. return -ENOMEM;
  824. }
  825. for (i = 0; i < n; i++) {
  826. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  827. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0)
  828. return -EIO;
  829. buf[i].addr = addr;
  830. buf[i].data = val;
  831. if (verbose)
  832. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  833. netxen_nic_driver_name,
  834. (u32)netxen_decode_crb_addr(addr), val);
  835. }
  836. for (i = 0; i < n; i++) {
  837. off = netxen_decode_crb_addr(buf[i].addr);
  838. if (off == NETXEN_ADDR_ERROR) {
  839. printk(KERN_ERR"CRB init value out of range %x\n",
  840. buf[i].addr);
  841. continue;
  842. }
  843. off += NETXEN_PCI_CRBSPACE;
  844. /* skipping cold reboot MAGIC */
  845. if (off == NETXEN_CAM_RAM(0x1fc))
  846. continue;
  847. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  848. /* do not reset PCI */
  849. if (off == (ROMUSB_GLB + 0xbc))
  850. continue;
  851. if (off == (ROMUSB_GLB + 0xa8))
  852. continue;
  853. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  854. continue;
  855. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  856. continue;
  857. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  858. continue;
  859. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  860. buf[i].data = 0x1020;
  861. /* skip the function enable register */
  862. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  863. continue;
  864. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  865. continue;
  866. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  867. continue;
  868. }
  869. if (off == NETXEN_ADDR_ERROR) {
  870. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  871. netxen_nic_driver_name, buf[i].addr);
  872. continue;
  873. }
  874. init_delay = 1;
  875. /* After writing this register, HW needs time for CRB */
  876. /* to quiet down (else crb_window returns 0xffffffff) */
  877. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  878. init_delay = 1000;
  879. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  880. /* hold xdma in reset also */
  881. buf[i].data = NETXEN_NIC_XDMA_RESET;
  882. buf[i].data = 0x8000ff;
  883. }
  884. }
  885. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  886. msleep(init_delay);
  887. }
  888. kfree(buf);
  889. /* disable_peg_cache_all */
  890. /* unreset_net_cache */
  891. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  892. adapter->hw_read_wx(adapter,
  893. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  894. netxen_crb_writelit_adapter(adapter,
  895. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  896. }
  897. /* p2dn replyCount */
  898. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  899. /* disable_peg_cache 0 */
  900. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  901. /* disable_peg_cache 1 */
  902. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  903. /* peg_clr_all */
  904. /* peg_clr 0 */
  905. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  906. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  907. /* peg_clr 1 */
  908. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  909. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  910. /* peg_clr 2 */
  911. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  912. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  913. /* peg_clr 3 */
  914. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  915. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  916. return 0;
  917. }
  918. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  919. {
  920. uint64_t addr;
  921. uint32_t hi;
  922. uint32_t lo;
  923. adapter->dummy_dma.addr =
  924. pci_alloc_consistent(adapter->pdev,
  925. NETXEN_HOST_DUMMY_DMA_SIZE,
  926. &adapter->dummy_dma.phys_addr);
  927. if (adapter->dummy_dma.addr == NULL) {
  928. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  929. __func__);
  930. return -ENOMEM;
  931. }
  932. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  933. hi = (addr >> 32) & 0xffffffff;
  934. lo = addr & 0xffffffff;
  935. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  936. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  937. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  938. uint32_t temp = 0;
  939. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  940. }
  941. return 0;
  942. }
  943. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  944. {
  945. int i = 100;
  946. if (!adapter->dummy_dma.addr)
  947. return;
  948. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  949. do {
  950. if (dma_watchdog_shutdown_request(adapter) == 1)
  951. break;
  952. msleep(50);
  953. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  954. break;
  955. } while (--i);
  956. }
  957. if (i) {
  958. pci_free_consistent(adapter->pdev,
  959. NETXEN_HOST_DUMMY_DMA_SIZE,
  960. adapter->dummy_dma.addr,
  961. adapter->dummy_dma.phys_addr);
  962. adapter->dummy_dma.addr = NULL;
  963. } else {
  964. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  965. adapter->netdev->name);
  966. }
  967. }
  968. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  969. {
  970. u32 val = 0;
  971. int retries = 60;
  972. if (!pegtune_val) {
  973. do {
  974. val = adapter->pci_read_normalize(adapter,
  975. CRB_CMDPEG_STATE);
  976. if (val == PHAN_INITIALIZE_COMPLETE ||
  977. val == PHAN_INITIALIZE_ACK)
  978. return 0;
  979. msleep(500);
  980. } while (--retries);
  981. if (!retries) {
  982. pegtune_val = adapter->pci_read_normalize(adapter,
  983. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  984. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  985. "pegtune_val=%x\n", pegtune_val);
  986. return -1;
  987. }
  988. }
  989. return 0;
  990. }
  991. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  992. {
  993. u32 val = 0;
  994. int retries = 2000;
  995. do {
  996. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  997. if (val == PHAN_PEG_RCV_INITIALIZED)
  998. return 0;
  999. msleep(10);
  1000. } while (--retries);
  1001. if (!retries) {
  1002. printk(KERN_ERR "Receive Peg initialization not "
  1003. "complete, state: 0x%x.\n", val);
  1004. return -EIO;
  1005. }
  1006. return 0;
  1007. }
  1008. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1009. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1010. {
  1011. struct netxen_rx_buffer *buffer;
  1012. struct sk_buff *skb;
  1013. buffer = &rds_ring->rx_buf_arr[index];
  1014. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1015. PCI_DMA_FROMDEVICE);
  1016. skb = buffer->skb;
  1017. if (!skb)
  1018. goto no_skb;
  1019. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1020. adapter->stats.csummed++;
  1021. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1022. } else
  1023. skb->ip_summed = CHECKSUM_NONE;
  1024. skb->dev = adapter->netdev;
  1025. buffer->skb = NULL;
  1026. no_skb:
  1027. buffer->state = NETXEN_BUFFER_FREE;
  1028. buffer->lro_current_frags = 0;
  1029. buffer->lro_expected_frags = 0;
  1030. list_add_tail(&buffer->list, &rds_ring->free_list);
  1031. return skb;
  1032. }
  1033. /*
  1034. * netxen_process_rcv() send the received packet to the protocol stack.
  1035. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  1036. * invoke the routine to send more rx buffers to the Phantom...
  1037. */
  1038. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  1039. struct status_desc *desc, struct status_desc *frag_desc)
  1040. {
  1041. struct net_device *netdev = adapter->netdev;
  1042. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  1043. int index = netxen_get_sts_refhandle(sts_data);
  1044. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1045. struct netxen_rx_buffer *buffer;
  1046. struct sk_buff *skb;
  1047. u32 length = netxen_get_sts_totallength(sts_data);
  1048. u32 desc_ctx;
  1049. u16 pkt_offset = 0, cksum;
  1050. struct nx_host_rds_ring *rds_ring;
  1051. desc_ctx = netxen_get_sts_type(sts_data);
  1052. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  1053. printk("%s: %s Bad Rcv descriptor ring\n",
  1054. netxen_nic_driver_name, netdev->name);
  1055. return;
  1056. }
  1057. rds_ring = &recv_ctx->rds_rings[desc_ctx];
  1058. if (unlikely(index > rds_ring->max_rx_desc_count)) {
  1059. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  1060. index, rds_ring->max_rx_desc_count);
  1061. return;
  1062. }
  1063. buffer = &rds_ring->rx_buf_arr[index];
  1064. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1065. buffer->lro_current_frags++;
  1066. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  1067. buffer->lro_expected_frags =
  1068. netxen_get_sts_desc_lro_cnt(desc);
  1069. buffer->lro_length = length;
  1070. }
  1071. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  1072. if (buffer->lro_expected_frags != 0) {
  1073. printk("LRO: (refhandle:%x) recv frag. "
  1074. "wait for last. flags: %x expected:%d "
  1075. "have:%d\n", index,
  1076. netxen_get_sts_desc_lro_last_frag(desc),
  1077. buffer->lro_expected_frags,
  1078. buffer->lro_current_frags);
  1079. }
  1080. return;
  1081. }
  1082. }
  1083. cksum = netxen_get_sts_status(sts_data);
  1084. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1085. if (!skb)
  1086. return;
  1087. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1088. /* True length was only available on the last pkt */
  1089. skb_put(skb, buffer->lro_length);
  1090. } else {
  1091. if (length > rds_ring->skb_size)
  1092. skb_put(skb, rds_ring->skb_size);
  1093. else
  1094. skb_put(skb, length);
  1095. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  1096. if (pkt_offset)
  1097. skb_pull(skb, pkt_offset);
  1098. }
  1099. skb->protocol = eth_type_trans(skb, netdev);
  1100. /*
  1101. * rx buffer chaining is disabled, walk and free
  1102. * any spurious rx buffer chain.
  1103. */
  1104. if (frag_desc) {
  1105. u16 i, nr_frags = desc->nr_frags;
  1106. dev_kfree_skb_any(skb);
  1107. for (i = 0; i < nr_frags; i++) {
  1108. index = le16_to_cpu(frag_desc->frag_handles[i]);
  1109. skb = netxen_process_rxbuf(adapter,
  1110. rds_ring, index, cksum);
  1111. if (skb)
  1112. dev_kfree_skb_any(skb);
  1113. }
  1114. adapter->stats.rxdropped++;
  1115. } else {
  1116. netif_receive_skb(skb);
  1117. adapter->stats.no_rcv++;
  1118. adapter->stats.rxbytes += length;
  1119. }
  1120. }
  1121. /* Process Receive status ring */
  1122. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1123. {
  1124. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1125. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1126. struct status_desc *desc, *frag_desc;
  1127. u32 consumer = recv_ctx->status_rx_consumer;
  1128. int count = 0, ring;
  1129. u64 sts_data;
  1130. u16 opcode;
  1131. while (count < max) {
  1132. desc = &desc_head[consumer];
  1133. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1134. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1135. netxen_get_sts_owner(desc));
  1136. break;
  1137. }
  1138. sts_data = le64_to_cpu(desc->status_desc_data);
  1139. opcode = netxen_get_sts_opcode(sts_data);
  1140. frag_desc = NULL;
  1141. if (opcode == NETXEN_NIC_RXPKT_DESC) {
  1142. if (desc->nr_frags) {
  1143. consumer = get_next_index(consumer,
  1144. adapter->max_rx_desc_count);
  1145. frag_desc = &desc_head[consumer];
  1146. netxen_set_sts_owner(frag_desc,
  1147. STATUS_OWNER_PHANTOM);
  1148. }
  1149. }
  1150. netxen_process_rcv(adapter, ctxid, desc, frag_desc);
  1151. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1152. consumer = get_next_index(consumer,
  1153. adapter->max_rx_desc_count);
  1154. count++;
  1155. }
  1156. for (ring = 0; ring < adapter->max_rds_rings; ring++)
  1157. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1158. /* update the consumer index in phantom */
  1159. if (count) {
  1160. recv_ctx->status_rx_consumer = consumer;
  1161. /* Window = 1 */
  1162. adapter->pci_write_normalize(adapter,
  1163. recv_ctx->crb_sts_consumer, consumer);
  1164. }
  1165. return count;
  1166. }
  1167. /* Process Command status ring */
  1168. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1169. {
  1170. u32 last_consumer, consumer;
  1171. int count = 0, i;
  1172. struct netxen_cmd_buffer *buffer;
  1173. struct pci_dev *pdev = adapter->pdev;
  1174. struct net_device *netdev = adapter->netdev;
  1175. struct netxen_skb_frag *frag;
  1176. int done = 0;
  1177. last_consumer = adapter->last_cmd_consumer;
  1178. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1179. while (last_consumer != consumer) {
  1180. buffer = &adapter->cmd_buf_arr[last_consumer];
  1181. if (buffer->skb) {
  1182. frag = &buffer->frag_array[0];
  1183. pci_unmap_single(pdev, frag->dma, frag->length,
  1184. PCI_DMA_TODEVICE);
  1185. frag->dma = 0ULL;
  1186. for (i = 1; i < buffer->frag_count; i++) {
  1187. frag++; /* Get the next frag */
  1188. pci_unmap_page(pdev, frag->dma, frag->length,
  1189. PCI_DMA_TODEVICE);
  1190. frag->dma = 0ULL;
  1191. }
  1192. adapter->stats.xmitfinished++;
  1193. dev_kfree_skb_any(buffer->skb);
  1194. buffer->skb = NULL;
  1195. }
  1196. last_consumer = get_next_index(last_consumer,
  1197. adapter->max_tx_desc_count);
  1198. if (++count >= MAX_STATUS_HANDLE)
  1199. break;
  1200. }
  1201. if (count) {
  1202. adapter->last_cmd_consumer = last_consumer;
  1203. smp_mb();
  1204. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  1205. netif_tx_lock(netdev);
  1206. netif_wake_queue(netdev);
  1207. smp_mb();
  1208. netif_tx_unlock(netdev);
  1209. }
  1210. }
  1211. /*
  1212. * If everything is freed up to consumer then check if the ring is full
  1213. * If the ring is full then check if more needs to be freed and
  1214. * schedule the call back again.
  1215. *
  1216. * This happens when there are 2 CPUs. One could be freeing and the
  1217. * other filling it. If the ring is full when we get out of here and
  1218. * the card has already interrupted the host then the host can miss the
  1219. * interrupt.
  1220. *
  1221. * There is still a possible race condition and the host could miss an
  1222. * interrupt. The card has to take care of this.
  1223. */
  1224. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1225. done = (last_consumer == consumer);
  1226. return (done);
  1227. }
  1228. /*
  1229. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1230. */
  1231. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1232. {
  1233. struct pci_dev *pdev = adapter->pdev;
  1234. struct sk_buff *skb;
  1235. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1236. struct nx_host_rds_ring *rds_ring = NULL;
  1237. uint producer;
  1238. struct rcv_desc *pdesc;
  1239. struct netxen_rx_buffer *buffer;
  1240. int count = 0;
  1241. int index = 0;
  1242. netxen_ctx_msg msg = 0;
  1243. dma_addr_t dma;
  1244. struct list_head *head;
  1245. rds_ring = &recv_ctx->rds_rings[ringid];
  1246. producer = rds_ring->producer;
  1247. index = rds_ring->begin_alloc;
  1248. head = &rds_ring->free_list;
  1249. /* We can start writing rx descriptors into the phantom memory. */
  1250. while (!list_empty(head)) {
  1251. skb = dev_alloc_skb(rds_ring->skb_size);
  1252. if (unlikely(!skb)) {
  1253. rds_ring->begin_alloc = index;
  1254. break;
  1255. }
  1256. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1257. list_del(&buffer->list);
  1258. count++; /* now there should be no failure */
  1259. pdesc = &rds_ring->desc_head[producer];
  1260. if (!adapter->ahw.cut_through)
  1261. skb_reserve(skb, 2);
  1262. /* This will be setup when we receive the
  1263. * buffer after it has been filled FSL TBD TBD
  1264. * skb->dev = netdev;
  1265. */
  1266. dma = pci_map_single(pdev, skb->data, rds_ring->dma_size,
  1267. PCI_DMA_FROMDEVICE);
  1268. pdesc->addr_buffer = cpu_to_le64(dma);
  1269. buffer->skb = skb;
  1270. buffer->state = NETXEN_BUFFER_BUSY;
  1271. buffer->dma = dma;
  1272. /* make a rcv descriptor */
  1273. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1274. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1275. DPRINTK(INFO, "done writing descripter\n");
  1276. producer =
  1277. get_next_index(producer, rds_ring->max_rx_desc_count);
  1278. index = get_next_index(index, rds_ring->max_rx_desc_count);
  1279. }
  1280. /* if we did allocate buffers, then write the count to Phantom */
  1281. if (count) {
  1282. rds_ring->begin_alloc = index;
  1283. rds_ring->producer = producer;
  1284. /* Window = 1 */
  1285. adapter->pci_write_normalize(adapter,
  1286. rds_ring->crb_rcv_producer,
  1287. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1288. if (adapter->fw_major < 4) {
  1289. /*
  1290. * Write a doorbell msg to tell phanmon of change in
  1291. * receive ring producer
  1292. * Only for firmware version < 4.0.0
  1293. */
  1294. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1295. netxen_set_msg_privid(msg);
  1296. netxen_set_msg_count(msg,
  1297. ((producer -
  1298. 1) & (rds_ring->
  1299. max_rx_desc_count - 1)));
  1300. netxen_set_msg_ctxid(msg, adapter->portnum);
  1301. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1302. writel(msg,
  1303. DB_NORMALIZE(adapter,
  1304. NETXEN_RCV_PRODUCER_OFFSET));
  1305. }
  1306. }
  1307. }
  1308. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1309. uint32_t ctx, uint32_t ringid)
  1310. {
  1311. struct pci_dev *pdev = adapter->pdev;
  1312. struct sk_buff *skb;
  1313. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1314. struct nx_host_rds_ring *rds_ring = NULL;
  1315. u32 producer;
  1316. struct rcv_desc *pdesc;
  1317. struct netxen_rx_buffer *buffer;
  1318. int count = 0;
  1319. int index = 0;
  1320. struct list_head *head;
  1321. rds_ring = &recv_ctx->rds_rings[ringid];
  1322. producer = rds_ring->producer;
  1323. index = rds_ring->begin_alloc;
  1324. head = &rds_ring->free_list;
  1325. /* We can start writing rx descriptors into the phantom memory. */
  1326. while (!list_empty(head)) {
  1327. skb = dev_alloc_skb(rds_ring->skb_size);
  1328. if (unlikely(!skb)) {
  1329. rds_ring->begin_alloc = index;
  1330. break;
  1331. }
  1332. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1333. list_del(&buffer->list);
  1334. count++; /* now there should be no failure */
  1335. pdesc = &rds_ring->desc_head[producer];
  1336. if (!adapter->ahw.cut_through)
  1337. skb_reserve(skb, 2);
  1338. buffer->skb = skb;
  1339. buffer->state = NETXEN_BUFFER_BUSY;
  1340. buffer->dma = pci_map_single(pdev, skb->data,
  1341. rds_ring->dma_size,
  1342. PCI_DMA_FROMDEVICE);
  1343. /* make a rcv descriptor */
  1344. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1345. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1346. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1347. producer =
  1348. get_next_index(producer, rds_ring->max_rx_desc_count);
  1349. index = get_next_index(index, rds_ring->max_rx_desc_count);
  1350. buffer = &rds_ring->rx_buf_arr[index];
  1351. }
  1352. /* if we did allocate buffers, then write the count to Phantom */
  1353. if (count) {
  1354. rds_ring->begin_alloc = index;
  1355. rds_ring->producer = producer;
  1356. /* Window = 1 */
  1357. adapter->pci_write_normalize(adapter,
  1358. rds_ring->crb_rcv_producer,
  1359. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1360. wmb();
  1361. }
  1362. }
  1363. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1364. {
  1365. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1366. return;
  1367. }