s3c2410_wdt.c 13 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26. #include <linux/module.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/types.h>
  29. #include <linux/timer.h>
  30. #include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */
  31. #include <linux/watchdog.h>
  32. #include <linux/init.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/clk.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <linux/cpufreq.h>
  39. #include <linux/slab.h>
  40. #include <linux/err.h>
  41. #include <mach/map.h>
  42. #undef S3C_VA_WATCHDOG
  43. #define S3C_VA_WATCHDOG (0)
  44. #include <plat/regs-watchdog.h>
  45. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  46. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  47. static int nowayout = WATCHDOG_NOWAYOUT;
  48. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  49. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  50. static int soft_noboot;
  51. static int debug;
  52. module_param(tmr_margin, int, 0);
  53. module_param(tmr_atboot, int, 0);
  54. module_param(nowayout, int, 0);
  55. module_param(soft_noboot, int, 0);
  56. module_param(debug, int, 0);
  57. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  58. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  59. MODULE_PARM_DESC(tmr_atboot,
  60. "Watchdog is started at boot time if set to 1, default="
  61. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  62. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  63. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  64. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  65. "0 to reboot (default 0)");
  66. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
  67. static struct device *wdt_dev; /* platform device attached to */
  68. static struct resource *wdt_mem;
  69. static struct resource *wdt_irq;
  70. static struct clk *wdt_clock;
  71. static void __iomem *wdt_base;
  72. static unsigned int wdt_count;
  73. static DEFINE_SPINLOCK(wdt_lock);
  74. /* watchdog control routines */
  75. #define DBG(fmt, ...) \
  76. do { \
  77. if (debug) \
  78. pr_info(fmt, ##__VA_ARGS__); \
  79. } while (0)
  80. /* functions */
  81. static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
  82. {
  83. spin_lock(&wdt_lock);
  84. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  85. spin_unlock(&wdt_lock);
  86. return 0;
  87. }
  88. static void __s3c2410wdt_stop(void)
  89. {
  90. unsigned long wtcon;
  91. wtcon = readl(wdt_base + S3C2410_WTCON);
  92. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  93. writel(wtcon, wdt_base + S3C2410_WTCON);
  94. }
  95. static int s3c2410wdt_stop(struct watchdog_device *wdd)
  96. {
  97. spin_lock(&wdt_lock);
  98. __s3c2410wdt_stop();
  99. spin_unlock(&wdt_lock);
  100. return 0;
  101. }
  102. static int s3c2410wdt_start(struct watchdog_device *wdd)
  103. {
  104. unsigned long wtcon;
  105. spin_lock(&wdt_lock);
  106. __s3c2410wdt_stop();
  107. wtcon = readl(wdt_base + S3C2410_WTCON);
  108. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  109. if (soft_noboot) {
  110. wtcon |= S3C2410_WTCON_INTEN;
  111. wtcon &= ~S3C2410_WTCON_RSTEN;
  112. } else {
  113. wtcon &= ~S3C2410_WTCON_INTEN;
  114. wtcon |= S3C2410_WTCON_RSTEN;
  115. }
  116. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  117. __func__, wdt_count, wtcon);
  118. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  119. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  120. writel(wtcon, wdt_base + S3C2410_WTCON);
  121. spin_unlock(&wdt_lock);
  122. return 0;
  123. }
  124. static inline int s3c2410wdt_is_running(void)
  125. {
  126. return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
  127. }
  128. static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
  129. {
  130. unsigned long freq = clk_get_rate(wdt_clock);
  131. unsigned int count;
  132. unsigned int divisor = 1;
  133. unsigned long wtcon;
  134. if (timeout < 1)
  135. return -EINVAL;
  136. freq /= 128;
  137. count = timeout * freq;
  138. DBG("%s: count=%d, timeout=%d, freq=%lu\n",
  139. __func__, count, timeout, freq);
  140. /* if the count is bigger than the watchdog register,
  141. then work out what we need to do (and if) we can
  142. actually make this value
  143. */
  144. if (count >= 0x10000) {
  145. for (divisor = 1; divisor <= 0x100; divisor++) {
  146. if ((count / divisor) < 0x10000)
  147. break;
  148. }
  149. if ((count / divisor) >= 0x10000) {
  150. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  151. return -EINVAL;
  152. }
  153. }
  154. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  155. __func__, timeout, divisor, count, count/divisor);
  156. count /= divisor;
  157. wdt_count = count;
  158. /* update the pre-scaler */
  159. wtcon = readl(wdt_base + S3C2410_WTCON);
  160. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  161. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  162. writel(count, wdt_base + S3C2410_WTDAT);
  163. writel(wtcon, wdt_base + S3C2410_WTCON);
  164. return 0;
  165. }
  166. #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
  167. static const struct watchdog_info s3c2410_wdt_ident = {
  168. .options = OPTIONS,
  169. .firmware_version = 0,
  170. .identity = "S3C2410 Watchdog",
  171. };
  172. static struct watchdog_ops s3c2410wdt_ops = {
  173. .owner = THIS_MODULE,
  174. .start = s3c2410wdt_start,
  175. .stop = s3c2410wdt_stop,
  176. .ping = s3c2410wdt_keepalive,
  177. .set_timeout = s3c2410wdt_set_heartbeat,
  178. };
  179. static struct watchdog_device s3c2410_wdd = {
  180. .info = &s3c2410_wdt_ident,
  181. .ops = &s3c2410wdt_ops,
  182. };
  183. /* interrupt handler code */
  184. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  185. {
  186. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  187. s3c2410wdt_keepalive(&s3c2410_wdd);
  188. return IRQ_HANDLED;
  189. }
  190. #ifdef CONFIG_CPU_FREQ
  191. static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
  192. unsigned long val, void *data)
  193. {
  194. int ret;
  195. if (!s3c2410wdt_is_running())
  196. goto done;
  197. if (val == CPUFREQ_PRECHANGE) {
  198. /* To ensure that over the change we don't cause the
  199. * watchdog to trigger, we perform an keep-alive if
  200. * the watchdog is running.
  201. */
  202. s3c2410wdt_keepalive(&s3c2410_wdd);
  203. } else if (val == CPUFREQ_POSTCHANGE) {
  204. s3c2410wdt_stop(&s3c2410_wdd);
  205. ret = s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout);
  206. if (ret >= 0)
  207. s3c2410wdt_start(&s3c2410_wdd);
  208. else
  209. goto err;
  210. }
  211. done:
  212. return 0;
  213. err:
  214. dev_err(wdt_dev, "cannot set new value for timeout %d\n",
  215. s3c2410_wdd.timeout);
  216. return ret;
  217. }
  218. static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
  219. .notifier_call = s3c2410wdt_cpufreq_transition,
  220. };
  221. static inline int s3c2410wdt_cpufreq_register(void)
  222. {
  223. return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
  224. CPUFREQ_TRANSITION_NOTIFIER);
  225. }
  226. static inline void s3c2410wdt_cpufreq_deregister(void)
  227. {
  228. cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
  229. CPUFREQ_TRANSITION_NOTIFIER);
  230. }
  231. #else
  232. static inline int s3c2410wdt_cpufreq_register(void)
  233. {
  234. return 0;
  235. }
  236. static inline void s3c2410wdt_cpufreq_deregister(void)
  237. {
  238. }
  239. #endif
  240. static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
  241. {
  242. struct device *dev;
  243. unsigned int wtcon;
  244. int started = 0;
  245. int ret;
  246. int size;
  247. DBG("%s: probe=%p\n", __func__, pdev);
  248. dev = &pdev->dev;
  249. wdt_dev = &pdev->dev;
  250. wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  251. if (wdt_mem == NULL) {
  252. dev_err(dev, "no memory resource specified\n");
  253. return -ENOENT;
  254. }
  255. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  256. if (wdt_irq == NULL) {
  257. dev_err(dev, "no irq resource specified\n");
  258. ret = -ENOENT;
  259. goto err;
  260. }
  261. /* get the memory region for the watchdog timer */
  262. size = resource_size(wdt_mem);
  263. if (!request_mem_region(wdt_mem->start, size, pdev->name)) {
  264. dev_err(dev, "failed to get memory region\n");
  265. ret = -EBUSY;
  266. goto err;
  267. }
  268. wdt_base = ioremap(wdt_mem->start, size);
  269. if (wdt_base == NULL) {
  270. dev_err(dev, "failed to ioremap() region\n");
  271. ret = -EINVAL;
  272. goto err_req;
  273. }
  274. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  275. wdt_clock = clk_get(&pdev->dev, "watchdog");
  276. if (IS_ERR(wdt_clock)) {
  277. dev_err(dev, "failed to find watchdog clock source\n");
  278. ret = PTR_ERR(wdt_clock);
  279. goto err_map;
  280. }
  281. clk_enable(wdt_clock);
  282. ret = s3c2410wdt_cpufreq_register();
  283. if (ret < 0) {
  284. pr_err("failed to register cpufreq\n");
  285. goto err_clk;
  286. }
  287. /* see if we can actually set the requested timer margin, and if
  288. * not, try the default value */
  289. if (s3c2410wdt_set_heartbeat(&s3c2410_wdd, tmr_margin)) {
  290. started = s3c2410wdt_set_heartbeat(&s3c2410_wdd,
  291. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  292. if (started == 0)
  293. dev_info(dev,
  294. "tmr_margin value out of range, default %d used\n",
  295. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  296. else
  297. dev_info(dev, "default timer value is out of range, "
  298. "cannot start\n");
  299. }
  300. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  301. if (ret != 0) {
  302. dev_err(dev, "failed to install irq (%d)\n", ret);
  303. goto err_cpufreq;
  304. }
  305. watchdog_set_nowayout(&s3c2410_wdd, nowayout);
  306. ret = watchdog_register_device(&s3c2410_wdd);
  307. if (ret) {
  308. dev_err(dev, "cannot register watchdog (%d)\n", ret);
  309. goto err_irq;
  310. }
  311. if (tmr_atboot && started == 0) {
  312. dev_info(dev, "starting watchdog timer\n");
  313. s3c2410wdt_start(&s3c2410_wdd);
  314. } else if (!tmr_atboot) {
  315. /* if we're not enabling the watchdog, then ensure it is
  316. * disabled if it has been left running from the bootloader
  317. * or other source */
  318. s3c2410wdt_stop(&s3c2410_wdd);
  319. }
  320. /* print out a statement of readiness */
  321. wtcon = readl(wdt_base + S3C2410_WTCON);
  322. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  323. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  324. (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
  325. (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
  326. return 0;
  327. err_irq:
  328. free_irq(wdt_irq->start, pdev);
  329. err_cpufreq:
  330. s3c2410wdt_cpufreq_deregister();
  331. err_clk:
  332. clk_disable(wdt_clock);
  333. clk_put(wdt_clock);
  334. wdt_clock = NULL;
  335. err_map:
  336. iounmap(wdt_base);
  337. err_req:
  338. release_mem_region(wdt_mem->start, size);
  339. err:
  340. wdt_irq = NULL;
  341. wdt_mem = NULL;
  342. return ret;
  343. }
  344. static int __devexit s3c2410wdt_remove(struct platform_device *dev)
  345. {
  346. watchdog_unregister_device(&s3c2410_wdd);
  347. free_irq(wdt_irq->start, dev);
  348. s3c2410wdt_cpufreq_deregister();
  349. clk_disable(wdt_clock);
  350. clk_put(wdt_clock);
  351. wdt_clock = NULL;
  352. iounmap(wdt_base);
  353. release_mem_region(wdt_mem->start, resource_size(wdt_mem));
  354. wdt_irq = NULL;
  355. wdt_mem = NULL;
  356. return 0;
  357. }
  358. static void s3c2410wdt_shutdown(struct platform_device *dev)
  359. {
  360. s3c2410wdt_stop(&s3c2410_wdd);
  361. }
  362. #ifdef CONFIG_PM
  363. static unsigned long wtcon_save;
  364. static unsigned long wtdat_save;
  365. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  366. {
  367. /* Save watchdog state, and turn it off. */
  368. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  369. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  370. /* Note that WTCNT doesn't need to be saved. */
  371. s3c2410wdt_stop(&s3c2410_wdd);
  372. return 0;
  373. }
  374. static int s3c2410wdt_resume(struct platform_device *dev)
  375. {
  376. /* Restore watchdog state. */
  377. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  378. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  379. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  380. pr_info("watchdog %sabled\n",
  381. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  382. return 0;
  383. }
  384. #else
  385. #define s3c2410wdt_suspend NULL
  386. #define s3c2410wdt_resume NULL
  387. #endif /* CONFIG_PM */
  388. #ifdef CONFIG_OF
  389. static const struct of_device_id s3c2410_wdt_match[] = {
  390. { .compatible = "samsung,s3c2410-wdt" },
  391. {},
  392. };
  393. MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
  394. #else
  395. #define s3c2410_wdt_match NULL
  396. #endif
  397. static struct platform_driver s3c2410wdt_driver = {
  398. .probe = s3c2410wdt_probe,
  399. .remove = __devexit_p(s3c2410wdt_remove),
  400. .shutdown = s3c2410wdt_shutdown,
  401. .suspend = s3c2410wdt_suspend,
  402. .resume = s3c2410wdt_resume,
  403. .driver = {
  404. .owner = THIS_MODULE,
  405. .name = "s3c2410-wdt",
  406. .of_match_table = s3c2410_wdt_match,
  407. },
  408. };
  409. static int __init watchdog_init(void)
  410. {
  411. pr_info("S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
  412. return platform_driver_register(&s3c2410wdt_driver);
  413. }
  414. static void __exit watchdog_exit(void)
  415. {
  416. platform_driver_unregister(&s3c2410wdt_driver);
  417. }
  418. module_init(watchdog_init);
  419. module_exit(watchdog_exit);
  420. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  421. "Dimitry Andric <dimitry.andric@tomtom.com>");
  422. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  423. MODULE_LICENSE("GPL");
  424. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  425. MODULE_ALIAS("platform:s3c2410-wdt");