cx23885-dvb.c 40 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc4000.h"
  38. #include "xc5000.h"
  39. #include "max2165.h"
  40. #include "tda10048.h"
  41. #include "tuner-xc2028.h"
  42. #include "tuner-simple.h"
  43. #include "dib7000p.h"
  44. #include "dibx000_common.h"
  45. #include "zl10353.h"
  46. #include "stv0900.h"
  47. #include "stv0900_reg.h"
  48. #include "stv6110.h"
  49. #include "lnbh24.h"
  50. #include "cx24116.h"
  51. #include "cimax2.h"
  52. #include "lgs8gxx.h"
  53. #include "netup-eeprom.h"
  54. #include "netup-init.h"
  55. #include "lgdt3305.h"
  56. #include "atbm8830.h"
  57. #include "ts2020.h"
  58. #include "ds3000.h"
  59. #include "cx23885-f300.h"
  60. #include "altera-ci.h"
  61. #include "stv0367.h"
  62. #include "drxk.h"
  63. #include "mt2063.h"
  64. #include "stv090x.h"
  65. #include "stb6100.h"
  66. #include "stb6100_cfg.h"
  67. #include "tda10071.h"
  68. #include "a8293.h"
  69. #include "mb86a20s.h"
  70. static unsigned int debug;
  71. #define dprintk(level, fmt, arg...)\
  72. do { if (debug >= level)\
  73. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  74. } while (0)
  75. /* ------------------------------------------------------------------ */
  76. static unsigned int alt_tuner;
  77. module_param(alt_tuner, int, 0644);
  78. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  79. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  80. /* ------------------------------------------------------------------ */
  81. static int dvb_buf_setup(struct videobuf_queue *q,
  82. unsigned int *count, unsigned int *size)
  83. {
  84. struct cx23885_tsport *port = q->priv_data;
  85. port->ts_packet_size = 188 * 4;
  86. port->ts_packet_count = 32;
  87. *size = port->ts_packet_size * port->ts_packet_count;
  88. *count = 32;
  89. return 0;
  90. }
  91. static int dvb_buf_prepare(struct videobuf_queue *q,
  92. struct videobuf_buffer *vb, enum v4l2_field field)
  93. {
  94. struct cx23885_tsport *port = q->priv_data;
  95. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  96. }
  97. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  98. {
  99. struct cx23885_tsport *port = q->priv_data;
  100. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  101. }
  102. static void dvb_buf_release(struct videobuf_queue *q,
  103. struct videobuf_buffer *vb)
  104. {
  105. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  106. }
  107. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  108. {
  109. struct videobuf_dvb_frontends *f;
  110. struct videobuf_dvb_frontend *fe;
  111. f = &port->frontends;
  112. if (f->gate <= 1) /* undefined or fe0 */
  113. fe = videobuf_dvb_get_frontend(f, 1);
  114. else
  115. fe = videobuf_dvb_get_frontend(f, f->gate);
  116. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  117. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  118. }
  119. static struct videobuf_queue_ops dvb_qops = {
  120. .buf_setup = dvb_buf_setup,
  121. .buf_prepare = dvb_buf_prepare,
  122. .buf_queue = dvb_buf_queue,
  123. .buf_release = dvb_buf_release,
  124. };
  125. static struct s5h1409_config hauppauge_generic_config = {
  126. .demod_address = 0x32 >> 1,
  127. .output_mode = S5H1409_SERIAL_OUTPUT,
  128. .gpio = S5H1409_GPIO_ON,
  129. .qam_if = 44000,
  130. .inversion = S5H1409_INVERSION_OFF,
  131. .status_mode = S5H1409_DEMODLOCKING,
  132. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  133. };
  134. static struct tda10048_config hauppauge_hvr1200_config = {
  135. .demod_address = 0x10 >> 1,
  136. .output_mode = TDA10048_SERIAL_OUTPUT,
  137. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  138. .inversion = TDA10048_INVERSION_ON,
  139. .dtv6_if_freq_khz = TDA10048_IF_3300,
  140. .dtv7_if_freq_khz = TDA10048_IF_3800,
  141. .dtv8_if_freq_khz = TDA10048_IF_4300,
  142. .clk_freq_khz = TDA10048_CLK_16000,
  143. };
  144. static struct tda10048_config hauppauge_hvr1210_config = {
  145. .demod_address = 0x10 >> 1,
  146. .output_mode = TDA10048_SERIAL_OUTPUT,
  147. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  148. .inversion = TDA10048_INVERSION_ON,
  149. .dtv6_if_freq_khz = TDA10048_IF_3300,
  150. .dtv7_if_freq_khz = TDA10048_IF_3500,
  151. .dtv8_if_freq_khz = TDA10048_IF_4000,
  152. .clk_freq_khz = TDA10048_CLK_16000,
  153. };
  154. static struct s5h1409_config hauppauge_ezqam_config = {
  155. .demod_address = 0x32 >> 1,
  156. .output_mode = S5H1409_SERIAL_OUTPUT,
  157. .gpio = S5H1409_GPIO_OFF,
  158. .qam_if = 4000,
  159. .inversion = S5H1409_INVERSION_ON,
  160. .status_mode = S5H1409_DEMODLOCKING,
  161. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  162. };
  163. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  164. .demod_address = 0x32 >> 1,
  165. .output_mode = S5H1409_SERIAL_OUTPUT,
  166. .gpio = S5H1409_GPIO_OFF,
  167. .qam_if = 44000,
  168. .inversion = S5H1409_INVERSION_OFF,
  169. .status_mode = S5H1409_DEMODLOCKING,
  170. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  171. };
  172. static struct s5h1409_config hauppauge_hvr1500_config = {
  173. .demod_address = 0x32 >> 1,
  174. .output_mode = S5H1409_SERIAL_OUTPUT,
  175. .gpio = S5H1409_GPIO_OFF,
  176. .inversion = S5H1409_INVERSION_OFF,
  177. .status_mode = S5H1409_DEMODLOCKING,
  178. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  179. };
  180. static struct mt2131_config hauppauge_generic_tunerconfig = {
  181. 0x61
  182. };
  183. static struct lgdt330x_config fusionhdtv_5_express = {
  184. .demod_address = 0x0e,
  185. .demod_chip = LGDT3303,
  186. .serial_mpeg = 0x40,
  187. };
  188. static struct s5h1409_config hauppauge_hvr1500q_config = {
  189. .demod_address = 0x32 >> 1,
  190. .output_mode = S5H1409_SERIAL_OUTPUT,
  191. .gpio = S5H1409_GPIO_ON,
  192. .qam_if = 44000,
  193. .inversion = S5H1409_INVERSION_OFF,
  194. .status_mode = S5H1409_DEMODLOCKING,
  195. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  196. };
  197. static struct s5h1409_config dvico_s5h1409_config = {
  198. .demod_address = 0x32 >> 1,
  199. .output_mode = S5H1409_SERIAL_OUTPUT,
  200. .gpio = S5H1409_GPIO_ON,
  201. .qam_if = 44000,
  202. .inversion = S5H1409_INVERSION_OFF,
  203. .status_mode = S5H1409_DEMODLOCKING,
  204. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  205. };
  206. static struct s5h1411_config dvico_s5h1411_config = {
  207. .output_mode = S5H1411_SERIAL_OUTPUT,
  208. .gpio = S5H1411_GPIO_ON,
  209. .qam_if = S5H1411_IF_44000,
  210. .vsb_if = S5H1411_IF_44000,
  211. .inversion = S5H1411_INVERSION_OFF,
  212. .status_mode = S5H1411_DEMODLOCKING,
  213. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  214. };
  215. static struct s5h1411_config hcw_s5h1411_config = {
  216. .output_mode = S5H1411_SERIAL_OUTPUT,
  217. .gpio = S5H1411_GPIO_OFF,
  218. .vsb_if = S5H1411_IF_44000,
  219. .qam_if = S5H1411_IF_4000,
  220. .inversion = S5H1411_INVERSION_ON,
  221. .status_mode = S5H1411_DEMODLOCKING,
  222. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  223. };
  224. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  225. .i2c_address = 0x61,
  226. .if_khz = 5380,
  227. };
  228. static struct xc5000_config dvico_xc5000_tunerconfig = {
  229. .i2c_address = 0x64,
  230. .if_khz = 5380,
  231. };
  232. static struct tda829x_config tda829x_no_probe = {
  233. .probe_tuner = TDA829X_DONT_PROBE,
  234. };
  235. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  236. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  237. .if_lvl = 6, .rfagc_top = 0x37 },
  238. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  239. .if_lvl = 6, .rfagc_top = 0x37 },
  240. };
  241. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  242. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  243. .if_lvl = 1, .rfagc_top = 0x37, },
  244. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  245. .if_lvl = 1, .rfagc_top = 0x37, },
  246. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  247. .if_lvl = 1, .rfagc_top = 0x37, },
  248. };
  249. static struct tda18271_config hauppauge_tda18271_config = {
  250. .std_map = &hauppauge_tda18271_std_map,
  251. .gate = TDA18271_GATE_ANALOG,
  252. .output_opt = TDA18271_OUTPUT_LT_OFF,
  253. };
  254. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  255. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  256. .gate = TDA18271_GATE_ANALOG,
  257. .output_opt = TDA18271_OUTPUT_LT_OFF,
  258. };
  259. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  260. .gate = TDA18271_GATE_DIGITAL,
  261. .output_opt = TDA18271_OUTPUT_LT_OFF,
  262. };
  263. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  264. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  265. .if_lvl = 1, .rfagc_top = 0x58 },
  266. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  267. .if_lvl = 1, .rfagc_top = 0x58 },
  268. };
  269. static struct tda18271_config hauppauge_hvr127x_config = {
  270. .std_map = &hauppauge_hvr127x_std_map,
  271. .output_opt = TDA18271_OUTPUT_LT_OFF,
  272. };
  273. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  274. .i2c_addr = 0x0e,
  275. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  276. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  277. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  278. .deny_i2c_rptr = 1,
  279. .spectral_inversion = 1,
  280. .qam_if_khz = 4000,
  281. .vsb_if_khz = 3250,
  282. };
  283. static struct dibx000_agc_config xc3028_agc_config = {
  284. BAND_VHF | BAND_UHF, /* band_caps */
  285. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  286. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  287. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  288. * P_agc_nb_est=2, P_agc_write=0
  289. */
  290. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  291. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  292. 712, /* inv_gain */
  293. 21, /* time_stabiliz */
  294. 0, /* alpha_level */
  295. 118, /* thlock */
  296. 0, /* wbd_inv */
  297. 2867, /* wbd_ref */
  298. 0, /* wbd_sel */
  299. 2, /* wbd_alpha */
  300. 0, /* agc1_max */
  301. 0, /* agc1_min */
  302. 39718, /* agc2_max */
  303. 9930, /* agc2_min */
  304. 0, /* agc1_pt1 */
  305. 0, /* agc1_pt2 */
  306. 0, /* agc1_pt3 */
  307. 0, /* agc1_slope1 */
  308. 0, /* agc1_slope2 */
  309. 0, /* agc2_pt1 */
  310. 128, /* agc2_pt2 */
  311. 29, /* agc2_slope1 */
  312. 29, /* agc2_slope2 */
  313. 17, /* alpha_mant */
  314. 27, /* alpha_exp */
  315. 23, /* beta_mant */
  316. 51, /* beta_exp */
  317. 1, /* perform_agc_softsplit */
  318. };
  319. /* PLL Configuration for COFDM BW_MHz = 8.000000
  320. * With external clock = 30.000000 */
  321. static struct dibx000_bandwidth_config xc3028_bw_config = {
  322. 60000, /* internal */
  323. 30000, /* sampling */
  324. 1, /* pll_cfg: prediv */
  325. 8, /* pll_cfg: ratio */
  326. 3, /* pll_cfg: range */
  327. 1, /* pll_cfg: reset */
  328. 0, /* pll_cfg: bypass */
  329. 0, /* misc: refdiv */
  330. 0, /* misc: bypclk_div */
  331. 1, /* misc: IO_CLK_en_core */
  332. 1, /* misc: ADClkSrc */
  333. 0, /* misc: modulo */
  334. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  335. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  336. 20452225, /* timf */
  337. 30000000 /* xtal_hz */
  338. };
  339. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  340. .output_mpeg2_in_188_bytes = 1,
  341. .hostbus_diversity = 1,
  342. .tuner_is_baseband = 0,
  343. .update_lna = NULL,
  344. .agc_config_count = 1,
  345. .agc = &xc3028_agc_config,
  346. .bw = &xc3028_bw_config,
  347. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  348. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  349. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  350. .pwm_freq_div = 0,
  351. .agc_control = NULL,
  352. .spur_protect = 0,
  353. .output_mode = OUTMODE_MPEG2_SERIAL,
  354. };
  355. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  356. .demod_address = 0x0f,
  357. .if2 = 45600,
  358. .no_tuner = 1,
  359. .disable_i2c_gate_ctrl = 1,
  360. };
  361. static struct stv0900_reg stv0900_ts_regs[] = {
  362. { R0900_TSGENERAL, 0x00 },
  363. { R0900_P1_TSSPEED, 0x40 },
  364. { R0900_P2_TSSPEED, 0x40 },
  365. { R0900_P1_TSCFGM, 0xc0 },
  366. { R0900_P2_TSCFGM, 0xc0 },
  367. { R0900_P1_TSCFGH, 0xe0 },
  368. { R0900_P2_TSCFGH, 0xe0 },
  369. { R0900_P1_TSCFGL, 0x20 },
  370. { R0900_P2_TSCFGL, 0x20 },
  371. { 0xffff, 0xff }, /* terminate */
  372. };
  373. static struct stv0900_config netup_stv0900_config = {
  374. .demod_address = 0x68,
  375. .demod_mode = 1, /* dual */
  376. .xtal = 8000000,
  377. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  378. .diseqc_mode = 2,/* 2/3 PWM */
  379. .ts_config_regs = stv0900_ts_regs,
  380. .tun1_maddress = 0,/* 0x60 */
  381. .tun2_maddress = 3,/* 0x63 */
  382. .tun1_adc = 1,/* 1 Vpp */
  383. .tun2_adc = 1,/* 1 Vpp */
  384. };
  385. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  386. .i2c_address = 0x60,
  387. .mclk = 16000000,
  388. .clk_div = 1,
  389. .gain = 8, /* +16 dB - maximum gain */
  390. };
  391. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  392. .i2c_address = 0x63,
  393. .mclk = 16000000,
  394. .clk_div = 1,
  395. .gain = 8, /* +16 dB - maximum gain */
  396. };
  397. static struct cx24116_config tbs_cx24116_config = {
  398. .demod_address = 0x55,
  399. };
  400. static struct ds3000_config tevii_ds3000_config = {
  401. .demod_address = 0x68,
  402. };
  403. static struct ts2020_config tevii_ts2020_config = {
  404. .tuner_address = 0x60,
  405. .clk_out_div = 1,
  406. };
  407. static struct cx24116_config dvbworld_cx24116_config = {
  408. .demod_address = 0x05,
  409. };
  410. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  411. .prod = LGS8GXX_PROD_LGS8GL5,
  412. .demod_address = 0x19,
  413. .serial_ts = 0,
  414. .ts_clk_pol = 1,
  415. .ts_clk_gated = 1,
  416. .if_clk_freq = 30400, /* 30.4 MHz */
  417. .if_freq = 5380, /* 5.38 MHz */
  418. .if_neg_center = 1,
  419. .ext_adc = 0,
  420. .adc_signed = 0,
  421. .if_neg_edge = 0,
  422. };
  423. static struct xc5000_config mygica_x8506_xc5000_config = {
  424. .i2c_address = 0x61,
  425. .if_khz = 5380,
  426. };
  427. static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
  428. .demod_address = 0x10,
  429. };
  430. static struct xc5000_config mygica_x8507_xc5000_config = {
  431. .i2c_address = 0x61,
  432. .if_khz = 4000,
  433. };
  434. static struct stv090x_config prof_8000_stv090x_config = {
  435. .device = STV0903,
  436. .demod_mode = STV090x_SINGLE,
  437. .clk_mode = STV090x_CLK_EXT,
  438. .xtal = 27000000,
  439. .address = 0x6A,
  440. .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
  441. .repeater_level = STV090x_RPTLEVEL_64,
  442. .adc1_range = STV090x_ADC_2Vpp,
  443. .diseqc_envelope_mode = false,
  444. .tuner_get_frequency = stb6100_get_frequency,
  445. .tuner_set_frequency = stb6100_set_frequency,
  446. .tuner_set_bandwidth = stb6100_set_bandwidth,
  447. .tuner_get_bandwidth = stb6100_get_bandwidth,
  448. };
  449. static struct stb6100_config prof_8000_stb6100_config = {
  450. .tuner_address = 0x60,
  451. .refclock = 27000000,
  452. };
  453. static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  454. {
  455. struct cx23885_tsport *port = fe->dvb->priv;
  456. struct cx23885_dev *dev = port->dev;
  457. if (voltage == SEC_VOLTAGE_18)
  458. cx_write(MC417_RWD, 0x00001e00);
  459. else if (voltage == SEC_VOLTAGE_13)
  460. cx_write(MC417_RWD, 0x00001a00);
  461. else
  462. cx_write(MC417_RWD, 0x00001800);
  463. return 0;
  464. }
  465. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
  466. {
  467. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  468. struct cx23885_tsport *port = fe->dvb->priv;
  469. struct cx23885_dev *dev = port->dev;
  470. switch (dev->board) {
  471. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  472. switch (p->modulation) {
  473. case VSB_8:
  474. cx23885_gpio_clear(dev, GPIO_5);
  475. break;
  476. case QAM_64:
  477. case QAM_256:
  478. default:
  479. cx23885_gpio_set(dev, GPIO_5);
  480. break;
  481. }
  482. break;
  483. case CX23885_BOARD_MYGICA_X8506:
  484. case CX23885_BOARD_MYGICA_X8507:
  485. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  486. /* Select Digital TV */
  487. cx23885_gpio_set(dev, GPIO_0);
  488. break;
  489. }
  490. /* Call the real set_frontend */
  491. if (port->set_frontend)
  492. return port->set_frontend(fe);
  493. return 0;
  494. }
  495. static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
  496. struct dvb_frontend *fe)
  497. {
  498. port->set_frontend = fe->ops.set_frontend;
  499. fe->ops.set_frontend = cx23885_dvb_set_frontend;
  500. }
  501. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  502. .prod = LGS8GXX_PROD_LGS8G75,
  503. .demod_address = 0x19,
  504. .serial_ts = 0,
  505. .ts_clk_pol = 1,
  506. .ts_clk_gated = 1,
  507. .if_clk_freq = 30400, /* 30.4 MHz */
  508. .if_freq = 6500, /* 6.50 MHz */
  509. .if_neg_center = 1,
  510. .ext_adc = 0,
  511. .adc_signed = 1,
  512. .adc_vpp = 2, /* 1.6 Vpp */
  513. .if_neg_edge = 1,
  514. };
  515. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  516. .i2c_address = 0x61,
  517. .if_khz = 6500,
  518. };
  519. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  520. .prod = ATBM8830_PROD_8830,
  521. .demod_address = 0x44,
  522. .serial_ts = 0,
  523. .ts_sampling_edge = 1,
  524. .ts_clk_gated = 0,
  525. .osc_clk_freq = 30400, /* in kHz */
  526. .if_freq = 0, /* zero IF */
  527. .zif_swap_iq = 1,
  528. .agc_min = 0x2E,
  529. .agc_max = 0xFF,
  530. .agc_hold_loop = 0,
  531. };
  532. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  533. .i2c_address = 0x60,
  534. .osc_clk = 20
  535. };
  536. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  537. .prod = ATBM8830_PROD_8830,
  538. .demod_address = 0x44,
  539. .serial_ts = 1,
  540. .ts_sampling_edge = 1,
  541. .ts_clk_gated = 0,
  542. .osc_clk_freq = 30400, /* in kHz */
  543. .if_freq = 0, /* zero IF */
  544. .zif_swap_iq = 1,
  545. .agc_min = 0x2E,
  546. .agc_max = 0xFF,
  547. .agc_hold_loop = 0,
  548. };
  549. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  550. .i2c_address = 0x60,
  551. .osc_clk = 20
  552. };
  553. static struct stv0367_config netup_stv0367_config[] = {
  554. {
  555. .demod_address = 0x1c,
  556. .xtal = 27000000,
  557. .if_khz = 4500,
  558. .if_iq_mode = 0,
  559. .ts_mode = 1,
  560. .clk_pol = 0,
  561. }, {
  562. .demod_address = 0x1d,
  563. .xtal = 27000000,
  564. .if_khz = 4500,
  565. .if_iq_mode = 0,
  566. .ts_mode = 1,
  567. .clk_pol = 0,
  568. },
  569. };
  570. static struct xc5000_config netup_xc5000_config[] = {
  571. {
  572. .i2c_address = 0x61,
  573. .if_khz = 4500,
  574. }, {
  575. .i2c_address = 0x64,
  576. .if_khz = 4500,
  577. },
  578. };
  579. static struct drxk_config terratec_drxk_config[] = {
  580. {
  581. .adr = 0x29,
  582. .no_i2c_bridge = 1,
  583. }, {
  584. .adr = 0x2a,
  585. .no_i2c_bridge = 1,
  586. },
  587. };
  588. static struct mt2063_config terratec_mt2063_config[] = {
  589. {
  590. .tuner_address = 0x60,
  591. }, {
  592. .tuner_address = 0x67,
  593. },
  594. };
  595. static const struct tda10071_config hauppauge_tda10071_config = {
  596. .demod_i2c_addr = 0x05,
  597. .tuner_i2c_addr = 0x54,
  598. .i2c_wr_max = 64,
  599. .ts_mode = TDA10071_TS_SERIAL,
  600. .spec_inv = 0,
  601. .xtal = 40444000, /* 40.444 MHz */
  602. .pll_multiplier = 20,
  603. };
  604. static const struct a8293_config hauppauge_a8293_config = {
  605. .i2c_addr = 0x0b,
  606. };
  607. static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  608. {
  609. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  610. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  611. uint32_t mem = 0;
  612. mem = cx_read(MC417_RWD);
  613. if (read)
  614. cx_set(MC417_OEN, ALT_DATA);
  615. else {
  616. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  617. mem &= ~ALT_DATA;
  618. mem |= (data & ALT_DATA);
  619. }
  620. if (flag)
  621. mem |= ALT_AD_RG;
  622. else
  623. mem &= ~ALT_AD_RG;
  624. mem &= ~ALT_CS;
  625. if (read)
  626. mem = (mem & ~ALT_RD) | ALT_WR;
  627. else
  628. mem = (mem & ~ALT_WR) | ALT_RD;
  629. cx_write(MC417_RWD, mem); /* start RW cycle */
  630. for (;;) {
  631. mem = cx_read(MC417_RWD);
  632. if ((mem & ALT_RDY) == 0)
  633. break;
  634. if (time_after(jiffies, timeout))
  635. break;
  636. udelay(1);
  637. }
  638. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  639. if (read)
  640. return mem & ALT_DATA;
  641. return 0;
  642. };
  643. static int dvb_register(struct cx23885_tsport *port)
  644. {
  645. struct cx23885_dev *dev = port->dev;
  646. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  647. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  648. int mfe_shared = 0; /* bus not shared by default */
  649. int ret;
  650. /* Get the first frontend */
  651. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  652. if (!fe0)
  653. return -EINVAL;
  654. /* init struct videobuf_dvb */
  655. fe0->dvb.name = dev->name;
  656. /* multi-frontend gate control is undefined or defaults to fe0 */
  657. port->frontends.gate = 0;
  658. /* Sets the gate control callback to be used by i2c command calls */
  659. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  660. /* init frontend */
  661. switch (dev->board) {
  662. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  663. i2c_bus = &dev->i2c_bus[0];
  664. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  665. &hauppauge_generic_config,
  666. &i2c_bus->i2c_adap);
  667. if (fe0->dvb.frontend != NULL) {
  668. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  669. &i2c_bus->i2c_adap,
  670. &hauppauge_generic_tunerconfig, 0);
  671. }
  672. break;
  673. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  674. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  675. i2c_bus = &dev->i2c_bus[0];
  676. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  677. &hauppauge_lgdt3305_config,
  678. &i2c_bus->i2c_adap);
  679. if (fe0->dvb.frontend != NULL) {
  680. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  681. 0x60, &dev->i2c_bus[1].i2c_adap,
  682. &hauppauge_hvr127x_config);
  683. }
  684. if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
  685. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  686. break;
  687. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  688. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  689. i2c_bus = &dev->i2c_bus[0];
  690. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  691. &hcw_s5h1411_config,
  692. &i2c_bus->i2c_adap);
  693. if (fe0->dvb.frontend != NULL) {
  694. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  695. 0x60, &dev->i2c_bus[1].i2c_adap,
  696. &hauppauge_tda18271_config);
  697. }
  698. tda18271_attach(&dev->ts1.analog_fe,
  699. 0x60, &dev->i2c_bus[1].i2c_adap,
  700. &hauppauge_tda18271_config);
  701. break;
  702. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  703. i2c_bus = &dev->i2c_bus[0];
  704. switch (alt_tuner) {
  705. case 1:
  706. fe0->dvb.frontend =
  707. dvb_attach(s5h1409_attach,
  708. &hauppauge_ezqam_config,
  709. &i2c_bus->i2c_adap);
  710. if (fe0->dvb.frontend != NULL) {
  711. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  712. &dev->i2c_bus[1].i2c_adap, 0x42,
  713. &tda829x_no_probe);
  714. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  715. 0x60, &dev->i2c_bus[1].i2c_adap,
  716. &hauppauge_tda18271_config);
  717. }
  718. break;
  719. case 0:
  720. default:
  721. fe0->dvb.frontend =
  722. dvb_attach(s5h1409_attach,
  723. &hauppauge_generic_config,
  724. &i2c_bus->i2c_adap);
  725. if (fe0->dvb.frontend != NULL)
  726. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  727. &i2c_bus->i2c_adap,
  728. &hauppauge_generic_tunerconfig, 0);
  729. break;
  730. }
  731. break;
  732. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  733. i2c_bus = &dev->i2c_bus[0];
  734. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  735. &hauppauge_hvr1800lp_config,
  736. &i2c_bus->i2c_adap);
  737. if (fe0->dvb.frontend != NULL) {
  738. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  739. &i2c_bus->i2c_adap,
  740. &hauppauge_generic_tunerconfig, 0);
  741. }
  742. break;
  743. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  744. i2c_bus = &dev->i2c_bus[0];
  745. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  746. &fusionhdtv_5_express,
  747. &i2c_bus->i2c_adap);
  748. if (fe0->dvb.frontend != NULL) {
  749. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  750. &i2c_bus->i2c_adap, 0x61,
  751. TUNER_LG_TDVS_H06XF);
  752. }
  753. break;
  754. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  755. i2c_bus = &dev->i2c_bus[1];
  756. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  757. &hauppauge_hvr1500q_config,
  758. &dev->i2c_bus[0].i2c_adap);
  759. if (fe0->dvb.frontend != NULL)
  760. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  761. &i2c_bus->i2c_adap,
  762. &hauppauge_hvr1500q_tunerconfig);
  763. break;
  764. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  765. i2c_bus = &dev->i2c_bus[1];
  766. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  767. &hauppauge_hvr1500_config,
  768. &dev->i2c_bus[0].i2c_adap);
  769. if (fe0->dvb.frontend != NULL) {
  770. struct dvb_frontend *fe;
  771. struct xc2028_config cfg = {
  772. .i2c_adap = &i2c_bus->i2c_adap,
  773. .i2c_addr = 0x61,
  774. };
  775. static struct xc2028_ctrl ctl = {
  776. .fname = XC2028_DEFAULT_FIRMWARE,
  777. .max_len = 64,
  778. .demod = XC3028_FE_OREN538,
  779. };
  780. fe = dvb_attach(xc2028_attach,
  781. fe0->dvb.frontend, &cfg);
  782. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  783. fe->ops.tuner_ops.set_config(fe, &ctl);
  784. }
  785. break;
  786. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  787. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  788. i2c_bus = &dev->i2c_bus[0];
  789. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  790. &hauppauge_hvr1200_config,
  791. &i2c_bus->i2c_adap);
  792. if (fe0->dvb.frontend != NULL) {
  793. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  794. &dev->i2c_bus[1].i2c_adap, 0x42,
  795. &tda829x_no_probe);
  796. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  797. 0x60, &dev->i2c_bus[1].i2c_adap,
  798. &hauppauge_hvr1200_tuner_config);
  799. }
  800. break;
  801. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  802. i2c_bus = &dev->i2c_bus[0];
  803. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  804. &hauppauge_hvr1210_config,
  805. &i2c_bus->i2c_adap);
  806. if (fe0->dvb.frontend != NULL) {
  807. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  808. 0x60, &dev->i2c_bus[1].i2c_adap,
  809. &hauppauge_hvr1210_tuner_config);
  810. }
  811. break;
  812. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  813. i2c_bus = &dev->i2c_bus[0];
  814. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  815. &i2c_bus->i2c_adap,
  816. 0x12, &hauppauge_hvr1400_dib7000_config);
  817. if (fe0->dvb.frontend != NULL) {
  818. struct dvb_frontend *fe;
  819. struct xc2028_config cfg = {
  820. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  821. .i2c_addr = 0x64,
  822. };
  823. static struct xc2028_ctrl ctl = {
  824. .fname = XC3028L_DEFAULT_FIRMWARE,
  825. .max_len = 64,
  826. .demod = XC3028_FE_DIBCOM52,
  827. /* This is true for all demods with
  828. v36 firmware? */
  829. .type = XC2028_D2633,
  830. };
  831. fe = dvb_attach(xc2028_attach,
  832. fe0->dvb.frontend, &cfg);
  833. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  834. fe->ops.tuner_ops.set_config(fe, &ctl);
  835. }
  836. break;
  837. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  838. i2c_bus = &dev->i2c_bus[port->nr - 1];
  839. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  840. &dvico_s5h1409_config,
  841. &i2c_bus->i2c_adap);
  842. if (fe0->dvb.frontend == NULL)
  843. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  844. &dvico_s5h1411_config,
  845. &i2c_bus->i2c_adap);
  846. if (fe0->dvb.frontend != NULL)
  847. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  848. &i2c_bus->i2c_adap,
  849. &dvico_xc5000_tunerconfig);
  850. break;
  851. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  852. i2c_bus = &dev->i2c_bus[port->nr - 1];
  853. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  854. &dvico_fusionhdtv_xc3028,
  855. &i2c_bus->i2c_adap);
  856. if (fe0->dvb.frontend != NULL) {
  857. struct dvb_frontend *fe;
  858. struct xc2028_config cfg = {
  859. .i2c_adap = &i2c_bus->i2c_adap,
  860. .i2c_addr = 0x61,
  861. };
  862. static struct xc2028_ctrl ctl = {
  863. .fname = XC2028_DEFAULT_FIRMWARE,
  864. .max_len = 64,
  865. .demod = XC3028_FE_ZARLINK456,
  866. };
  867. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  868. &cfg);
  869. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  870. fe->ops.tuner_ops.set_config(fe, &ctl);
  871. }
  872. break;
  873. }
  874. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  875. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  876. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  877. i2c_bus = &dev->i2c_bus[0];
  878. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  879. &dvico_fusionhdtv_xc3028,
  880. &i2c_bus->i2c_adap);
  881. if (fe0->dvb.frontend != NULL) {
  882. struct dvb_frontend *fe;
  883. struct xc2028_config cfg = {
  884. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  885. .i2c_addr = 0x61,
  886. };
  887. static struct xc2028_ctrl ctl = {
  888. .fname = XC2028_DEFAULT_FIRMWARE,
  889. .max_len = 64,
  890. .demod = XC3028_FE_ZARLINK456,
  891. };
  892. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  893. &cfg);
  894. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  895. fe->ops.tuner_ops.set_config(fe, &ctl);
  896. }
  897. break;
  898. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  899. i2c_bus = &dev->i2c_bus[0];
  900. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  901. &dvico_fusionhdtv_xc3028,
  902. &i2c_bus->i2c_adap);
  903. if (fe0->dvb.frontend != NULL) {
  904. struct dvb_frontend *fe;
  905. struct xc4000_config cfg = {
  906. .i2c_address = 0x61,
  907. .default_pm = 0,
  908. .dvb_amplitude = 134,
  909. .set_smoothedcvbs = 1,
  910. .if_khz = 4560
  911. };
  912. fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
  913. &dev->i2c_bus[1].i2c_adap, &cfg);
  914. if (!fe) {
  915. printk(KERN_ERR "%s/2: xc4000 attach failed\n",
  916. dev->name);
  917. goto frontend_detach;
  918. }
  919. }
  920. break;
  921. case CX23885_BOARD_TBS_6920:
  922. i2c_bus = &dev->i2c_bus[1];
  923. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  924. &tbs_cx24116_config,
  925. &i2c_bus->i2c_adap);
  926. if (fe0->dvb.frontend != NULL)
  927. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  928. break;
  929. case CX23885_BOARD_TEVII_S470:
  930. i2c_bus = &dev->i2c_bus[1];
  931. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  932. &tevii_ds3000_config,
  933. &i2c_bus->i2c_adap);
  934. if (fe0->dvb.frontend != NULL) {
  935. dvb_attach(ts2020_attach, fe0->dvb.frontend,
  936. &tevii_ts2020_config, &i2c_bus->i2c_adap);
  937. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  938. }
  939. break;
  940. case CX23885_BOARD_DVBWORLD_2005:
  941. i2c_bus = &dev->i2c_bus[1];
  942. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  943. &dvbworld_cx24116_config,
  944. &i2c_bus->i2c_adap);
  945. break;
  946. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  947. i2c_bus = &dev->i2c_bus[0];
  948. switch (port->nr) {
  949. /* port B */
  950. case 1:
  951. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  952. &netup_stv0900_config,
  953. &i2c_bus->i2c_adap, 0);
  954. if (fe0->dvb.frontend != NULL) {
  955. if (dvb_attach(stv6110_attach,
  956. fe0->dvb.frontend,
  957. &netup_stv6110_tunerconfig_a,
  958. &i2c_bus->i2c_adap)) {
  959. if (!dvb_attach(lnbh24_attach,
  960. fe0->dvb.frontend,
  961. &i2c_bus->i2c_adap,
  962. LNBH24_PCL | LNBH24_TTX,
  963. LNBH24_TEN, 0x09))
  964. printk(KERN_ERR
  965. "No LNBH24 found!\n");
  966. }
  967. }
  968. break;
  969. /* port C */
  970. case 2:
  971. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  972. &netup_stv0900_config,
  973. &i2c_bus->i2c_adap, 1);
  974. if (fe0->dvb.frontend != NULL) {
  975. if (dvb_attach(stv6110_attach,
  976. fe0->dvb.frontend,
  977. &netup_stv6110_tunerconfig_b,
  978. &i2c_bus->i2c_adap)) {
  979. if (!dvb_attach(lnbh24_attach,
  980. fe0->dvb.frontend,
  981. &i2c_bus->i2c_adap,
  982. LNBH24_PCL | LNBH24_TTX,
  983. LNBH24_TEN, 0x0a))
  984. printk(KERN_ERR
  985. "No LNBH24 found!\n");
  986. }
  987. }
  988. break;
  989. }
  990. break;
  991. case CX23885_BOARD_MYGICA_X8506:
  992. i2c_bus = &dev->i2c_bus[0];
  993. i2c_bus2 = &dev->i2c_bus[1];
  994. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  995. &mygica_x8506_lgs8gl5_config,
  996. &i2c_bus->i2c_adap);
  997. if (fe0->dvb.frontend != NULL) {
  998. dvb_attach(xc5000_attach,
  999. fe0->dvb.frontend,
  1000. &i2c_bus2->i2c_adap,
  1001. &mygica_x8506_xc5000_config);
  1002. }
  1003. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  1004. break;
  1005. case CX23885_BOARD_MYGICA_X8507:
  1006. i2c_bus = &dev->i2c_bus[0];
  1007. i2c_bus2 = &dev->i2c_bus[1];
  1008. fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
  1009. &mygica_x8507_mb86a20s_config,
  1010. &i2c_bus->i2c_adap);
  1011. if (fe0->dvb.frontend != NULL) {
  1012. dvb_attach(xc5000_attach,
  1013. fe0->dvb.frontend,
  1014. &i2c_bus2->i2c_adap,
  1015. &mygica_x8507_xc5000_config);
  1016. }
  1017. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  1018. break;
  1019. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1020. i2c_bus = &dev->i2c_bus[0];
  1021. i2c_bus2 = &dev->i2c_bus[1];
  1022. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  1023. &magicpro_prohdtve2_lgs8g75_config,
  1024. &i2c_bus->i2c_adap);
  1025. if (fe0->dvb.frontend != NULL) {
  1026. dvb_attach(xc5000_attach,
  1027. fe0->dvb.frontend,
  1028. &i2c_bus2->i2c_adap,
  1029. &magicpro_prohdtve2_xc5000_config);
  1030. }
  1031. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  1032. break;
  1033. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1034. i2c_bus = &dev->i2c_bus[0];
  1035. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1036. &hcw_s5h1411_config,
  1037. &i2c_bus->i2c_adap);
  1038. if (fe0->dvb.frontend != NULL)
  1039. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1040. 0x60, &dev->i2c_bus[0].i2c_adap,
  1041. &hauppauge_tda18271_config);
  1042. tda18271_attach(&dev->ts1.analog_fe,
  1043. 0x60, &dev->i2c_bus[1].i2c_adap,
  1044. &hauppauge_tda18271_config);
  1045. break;
  1046. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1047. i2c_bus = &dev->i2c_bus[0];
  1048. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1049. &hcw_s5h1411_config,
  1050. &i2c_bus->i2c_adap);
  1051. if (fe0->dvb.frontend != NULL)
  1052. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1053. 0x60, &dev->i2c_bus[0].i2c_adap,
  1054. &hauppauge_tda18271_config);
  1055. break;
  1056. case CX23885_BOARD_MYGICA_X8558PRO:
  1057. switch (port->nr) {
  1058. /* port B */
  1059. case 1:
  1060. i2c_bus = &dev->i2c_bus[0];
  1061. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1062. &mygica_x8558pro_atbm8830_cfg1,
  1063. &i2c_bus->i2c_adap);
  1064. if (fe0->dvb.frontend != NULL) {
  1065. dvb_attach(max2165_attach,
  1066. fe0->dvb.frontend,
  1067. &i2c_bus->i2c_adap,
  1068. &mygic_x8558pro_max2165_cfg1);
  1069. }
  1070. break;
  1071. /* port C */
  1072. case 2:
  1073. i2c_bus = &dev->i2c_bus[1];
  1074. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1075. &mygica_x8558pro_atbm8830_cfg2,
  1076. &i2c_bus->i2c_adap);
  1077. if (fe0->dvb.frontend != NULL) {
  1078. dvb_attach(max2165_attach,
  1079. fe0->dvb.frontend,
  1080. &i2c_bus->i2c_adap,
  1081. &mygic_x8558pro_max2165_cfg2);
  1082. }
  1083. break;
  1084. }
  1085. break;
  1086. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1087. i2c_bus = &dev->i2c_bus[0];
  1088. mfe_shared = 1;/* MFE */
  1089. port->frontends.gate = 0;/* not clear for me yet */
  1090. /* ports B, C */
  1091. /* MFE frontend 1 DVB-T */
  1092. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  1093. &netup_stv0367_config[port->nr - 1],
  1094. &i2c_bus->i2c_adap);
  1095. if (fe0->dvb.frontend != NULL) {
  1096. if (NULL == dvb_attach(xc5000_attach,
  1097. fe0->dvb.frontend,
  1098. &i2c_bus->i2c_adap,
  1099. &netup_xc5000_config[port->nr - 1]))
  1100. goto frontend_detach;
  1101. /* load xc5000 firmware */
  1102. fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
  1103. }
  1104. /* MFE frontend 2 */
  1105. fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
  1106. if (fe1 == NULL)
  1107. goto frontend_detach;
  1108. /* DVB-C init */
  1109. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  1110. &netup_stv0367_config[port->nr - 1],
  1111. &i2c_bus->i2c_adap);
  1112. if (fe1->dvb.frontend != NULL) {
  1113. fe1->dvb.frontend->id = 1;
  1114. if (NULL == dvb_attach(xc5000_attach,
  1115. fe1->dvb.frontend,
  1116. &i2c_bus->i2c_adap,
  1117. &netup_xc5000_config[port->nr - 1]))
  1118. goto frontend_detach;
  1119. }
  1120. break;
  1121. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1122. i2c_bus = &dev->i2c_bus[0];
  1123. i2c_bus2 = &dev->i2c_bus[1];
  1124. switch (port->nr) {
  1125. /* port b */
  1126. case 1:
  1127. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1128. &terratec_drxk_config[0],
  1129. &i2c_bus->i2c_adap);
  1130. if (fe0->dvb.frontend != NULL) {
  1131. if (!dvb_attach(mt2063_attach,
  1132. fe0->dvb.frontend,
  1133. &terratec_mt2063_config[0],
  1134. &i2c_bus2->i2c_adap))
  1135. goto frontend_detach;
  1136. }
  1137. break;
  1138. /* port c */
  1139. case 2:
  1140. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1141. &terratec_drxk_config[1],
  1142. &i2c_bus->i2c_adap);
  1143. if (fe0->dvb.frontend != NULL) {
  1144. if (!dvb_attach(mt2063_attach,
  1145. fe0->dvb.frontend,
  1146. &terratec_mt2063_config[1],
  1147. &i2c_bus2->i2c_adap))
  1148. goto frontend_detach;
  1149. }
  1150. break;
  1151. }
  1152. break;
  1153. case CX23885_BOARD_TEVII_S471:
  1154. i2c_bus = &dev->i2c_bus[1];
  1155. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  1156. &tevii_ds3000_config,
  1157. &i2c_bus->i2c_adap);
  1158. if (fe0->dvb.frontend != NULL) {
  1159. dvb_attach(ts2020_attach, fe0->dvb.frontend,
  1160. &tevii_ts2020_config, &i2c_bus->i2c_adap);
  1161. }
  1162. break;
  1163. case CX23885_BOARD_PROF_8000:
  1164. i2c_bus = &dev->i2c_bus[0];
  1165. fe0->dvb.frontend = dvb_attach(stv090x_attach,
  1166. &prof_8000_stv090x_config,
  1167. &i2c_bus->i2c_adap,
  1168. STV090x_DEMODULATOR_0);
  1169. if (fe0->dvb.frontend != NULL) {
  1170. if (!dvb_attach(stb6100_attach,
  1171. fe0->dvb.frontend,
  1172. &prof_8000_stb6100_config,
  1173. &i2c_bus->i2c_adap))
  1174. goto frontend_detach;
  1175. fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
  1176. }
  1177. break;
  1178. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1179. i2c_bus = &dev->i2c_bus[0];
  1180. fe0->dvb.frontend = dvb_attach(tda10071_attach,
  1181. &hauppauge_tda10071_config,
  1182. &i2c_bus->i2c_adap);
  1183. if (fe0->dvb.frontend != NULL) {
  1184. dvb_attach(a8293_attach, fe0->dvb.frontend,
  1185. &i2c_bus->i2c_adap,
  1186. &hauppauge_a8293_config);
  1187. }
  1188. break;
  1189. default:
  1190. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  1191. " isn't supported yet\n",
  1192. dev->name);
  1193. break;
  1194. }
  1195. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  1196. printk(KERN_ERR "%s: frontend initialization failed\n",
  1197. dev->name);
  1198. goto frontend_detach;
  1199. }
  1200. /* define general-purpose callback pointer */
  1201. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1202. if (fe1)
  1203. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1204. #if 0
  1205. /* Ensure all frontends negotiate bus access */
  1206. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1207. if (fe1)
  1208. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1209. #endif
  1210. /* Put the analog decoder in standby to keep it quiet */
  1211. call_all(dev, core, s_power, 0);
  1212. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1213. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1214. /* register everything */
  1215. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1216. &dev->pci->dev, adapter_nr, mfe_shared);
  1217. if (ret)
  1218. goto frontend_detach;
  1219. /* init CI & MAC */
  1220. switch (dev->board) {
  1221. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1222. static struct netup_card_info cinfo;
  1223. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1224. memcpy(port->frontends.adapter.proposed_mac,
  1225. cinfo.port[port->nr - 1].mac, 6);
  1226. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1227. port->nr, port->frontends.adapter.proposed_mac);
  1228. netup_ci_init(port);
  1229. break;
  1230. }
  1231. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1232. struct altera_ci_config netup_ci_cfg = {
  1233. .dev = dev,/* magic number to identify*/
  1234. .adapter = &port->frontends.adapter,/* for CI */
  1235. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1236. .fpga_rw = netup_altera_fpga_rw,
  1237. };
  1238. altera_ci_init(&netup_ci_cfg, port->nr);
  1239. break;
  1240. }
  1241. case CX23885_BOARD_TEVII_S470: {
  1242. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1243. if (port->nr != 1)
  1244. break;
  1245. /* Read entire EEPROM */
  1246. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1247. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1248. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1249. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1250. break;
  1251. }
  1252. }
  1253. return ret;
  1254. frontend_detach:
  1255. port->gate_ctrl = NULL;
  1256. videobuf_dvb_dealloc_frontends(&port->frontends);
  1257. return -EINVAL;
  1258. }
  1259. int cx23885_dvb_register(struct cx23885_tsport *port)
  1260. {
  1261. struct videobuf_dvb_frontend *fe0;
  1262. struct cx23885_dev *dev = port->dev;
  1263. int err, i;
  1264. /* Here we need to allocate the correct number of frontends,
  1265. * as reflected in the cards struct. The reality is that currently
  1266. * no cx23885 boards support this - yet. But, if we don't modify this
  1267. * code then the second frontend would never be allocated (later)
  1268. * and fail with error before the attach in dvb_register().
  1269. * Without these changes we risk an OOPS later. The changes here
  1270. * are for safety, and should provide a good foundation for the
  1271. * future addition of any multi-frontend cx23885 based boards.
  1272. */
  1273. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1274. port->num_frontends);
  1275. for (i = 1; i <= port->num_frontends; i++) {
  1276. if (videobuf_dvb_alloc_frontend(
  1277. &port->frontends, i) == NULL) {
  1278. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1279. return -ENOMEM;
  1280. }
  1281. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  1282. if (!fe0)
  1283. err = -EINVAL;
  1284. dprintk(1, "%s\n", __func__);
  1285. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1286. dev->board,
  1287. dev->name,
  1288. dev->pci_bus,
  1289. dev->pci_slot);
  1290. err = -ENODEV;
  1291. /* dvb stuff */
  1292. /* We have to init the queue for each frontend on a port. */
  1293. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1294. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  1295. &dev->pci->dev, &port->slock,
  1296. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  1297. sizeof(struct cx23885_buffer), port, NULL);
  1298. }
  1299. err = dvb_register(port);
  1300. if (err != 0)
  1301. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1302. __func__, err);
  1303. return err;
  1304. }
  1305. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1306. {
  1307. struct videobuf_dvb_frontend *fe0;
  1308. /* FIXME: in an error condition where the we have
  1309. * an expected number of frontends (attach problem)
  1310. * then this might not clean up correctly, if 1
  1311. * is invalid.
  1312. * This comment only applies to future boards IF they
  1313. * implement MFE support.
  1314. */
  1315. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  1316. if (fe0 && fe0->dvb.frontend)
  1317. videobuf_dvb_unregister_bus(&port->frontends);
  1318. switch (port->dev->board) {
  1319. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1320. netup_ci_exit(port);
  1321. break;
  1322. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1323. altera_ci_release(port->dev, port->nr);
  1324. break;
  1325. }
  1326. port->gate_ctrl = NULL;
  1327. return 0;
  1328. }