ste-nomadik-stn8815.dtsi 1.7 KB

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  1. /*
  2. * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
  3. */
  4. /include/ "skeleton.dtsi"
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. memory {
  9. reg = <0x00000000 0x04000000>,
  10. <0x08000000 0x04000000>;
  11. };
  12. L2: l2-cache {
  13. compatible = "arm,l210-cache";
  14. reg = <0x10210000 0x1000>;
  15. interrupt-parent = <&vica>;
  16. interrupts = <30>;
  17. cache-unified;
  18. cache-level = <2>;
  19. };
  20. mtu0 {
  21. /* Nomadik system timer */
  22. reg = <0x101e2000 0x1000>;
  23. interrupt-parent = <&vica>;
  24. interrupts = <4>;
  25. };
  26. mtu1 {
  27. /* Secondary timer */
  28. reg = <0x101e3000 0x1000>;
  29. interrupt-parent = <&vica>;
  30. interrupts = <5>;
  31. };
  32. amba {
  33. compatible = "arm,amba-bus";
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. ranges;
  37. vica: intc@0x10140000 {
  38. compatible = "arm,versatile-vic";
  39. interrupt-controller;
  40. #interrupt-cells = <1>;
  41. reg = <0x10140000 0x20>;
  42. };
  43. vicb: intc@0x10140020 {
  44. compatible = "arm,versatile-vic";
  45. interrupt-controller;
  46. #interrupt-cells = <1>;
  47. reg = <0x10140020 0x20>;
  48. };
  49. uart0: uart@101fd000 {
  50. compatible = "arm,pl011", "arm,primecell";
  51. reg = <0x101fd000 0x1000>;
  52. interrupt-parent = <&vica>;
  53. interrupts = <12>;
  54. };
  55. uart1: uart@101fb000 {
  56. compatible = "arm,pl011", "arm,primecell";
  57. reg = <0x101fb000 0x1000>;
  58. interrupt-parent = <&vica>;
  59. interrupts = <17>;
  60. };
  61. uart2: uart@101f2000 {
  62. compatible = "arm,pl011", "arm,primecell";
  63. reg = <0x101f2000 0x1000>;
  64. interrupt-parent = <&vica>;
  65. interrupts = <28>;
  66. status = "disabled";
  67. };
  68. rng: rng@101b0000 {
  69. compatible = "arm,primecell";
  70. reg = <0x101b0000 0x1000>;
  71. };
  72. rtc: rtc@101e8000 {
  73. compatible = "arm,pl031", "arm,primecell";
  74. reg = <0x101e8000 0x1000>;
  75. interrupt-parent = <&vica>;
  76. interrupts = <10>;
  77. };
  78. };
  79. };