phy.c 74 KB

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  1. /*
  2. * PHY functions
  3. *
  4. * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
  5. * Copyright (c) 2006, 2007 Nick Kossifidis <mickflemm@gmail.com>
  6. * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
  7. *
  8. * Permission to use, copy, modify, and distribute this software for any
  9. * purpose with or without fee is hereby granted, provided that the above
  10. * copyright notice and this permission notice appear in all copies.
  11. *
  12. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19. *
  20. */
  21. #include <linux/delay.h>
  22. #include "ath5k.h"
  23. #include "reg.h"
  24. #include "base.h"
  25. /* Struct to hold initial RF register values (RF Banks) */
  26. struct ath5k_ini_rf {
  27. u8 rf_bank; /* check out ath5k_reg.h */
  28. u16 rf_register; /* register address */
  29. u32 rf_value[5]; /* register value for different modes (above) */
  30. };
  31. /*
  32. * Mode-specific RF Gain table (64bytes) for RF5111/5112
  33. * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
  34. * RF Gain values are included in AR5K_AR5210_INI)
  35. */
  36. struct ath5k_ini_rfgain {
  37. u16 rfg_register; /* RF Gain register address */
  38. u32 rfg_value[2]; /* [freq (see below)] */
  39. };
  40. struct ath5k_gain_opt {
  41. u32 go_default;
  42. u32 go_steps_count;
  43. const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
  44. };
  45. /* RF5111 mode-specific init registers */
  46. static const struct ath5k_ini_rf rfregs_5111[] = {
  47. { 0, 0x989c,
  48. /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
  49. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  50. { 0, 0x989c,
  51. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  52. { 0, 0x989c,
  53. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  54. { 0, 0x989c,
  55. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  56. { 0, 0x989c,
  57. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  58. { 0, 0x989c,
  59. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  60. { 0, 0x989c,
  61. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  62. { 0, 0x989c,
  63. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  64. { 0, 0x989c,
  65. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  66. { 0, 0x989c,
  67. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  68. { 0, 0x989c,
  69. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  70. { 0, 0x989c,
  71. { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
  72. { 0, 0x989c,
  73. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  74. { 0, 0x989c,
  75. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  76. { 0, 0x989c,
  77. { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
  78. { 0, 0x989c,
  79. { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
  80. { 0, 0x98d4,
  81. { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
  82. { 1, 0x98d4,
  83. { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
  84. { 2, 0x98d4,
  85. { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
  86. { 3, 0x98d8,
  87. { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
  88. { 6, 0x989c,
  89. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  90. { 6, 0x989c,
  91. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  92. { 6, 0x989c,
  93. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  94. { 6, 0x989c,
  95. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  96. { 6, 0x989c,
  97. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  98. { 6, 0x989c,
  99. { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
  100. { 6, 0x989c,
  101. { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
  102. { 6, 0x989c,
  103. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  104. { 6, 0x989c,
  105. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  106. { 6, 0x989c,
  107. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  108. { 6, 0x989c,
  109. { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
  110. { 6, 0x989c,
  111. { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
  112. { 6, 0x989c,
  113. { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
  114. { 6, 0x989c,
  115. { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
  116. { 6, 0x989c,
  117. { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
  118. { 6, 0x989c,
  119. { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
  120. { 6, 0x98d4,
  121. { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
  122. { 7, 0x989c,
  123. { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
  124. { 7, 0x989c,
  125. { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
  126. { 7, 0x989c,
  127. { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
  128. { 7, 0x989c,
  129. { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
  130. { 7, 0x989c,
  131. { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
  132. { 7, 0x989c,
  133. { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
  134. { 7, 0x989c,
  135. { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
  136. { 7, 0x98cc,
  137. { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
  138. };
  139. /* Initial RF Gain settings for RF5111 */
  140. static const struct ath5k_ini_rfgain rfgain_5111[] = {
  141. /* 5Ghz 2Ghz */
  142. { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
  143. { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
  144. { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
  145. { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
  146. { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
  147. { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
  148. { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
  149. { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
  150. { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
  151. { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
  152. { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
  153. { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
  154. { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
  155. { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
  156. { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
  157. { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
  158. { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
  159. { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
  160. { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
  161. { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
  162. { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
  163. { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
  164. { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
  165. { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
  166. { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
  167. { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
  168. { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
  169. { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
  170. { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
  171. { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
  172. { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
  173. { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
  174. { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
  175. { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
  176. { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
  177. { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
  178. { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
  179. { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
  180. { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
  181. { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
  182. { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
  183. { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
  184. { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
  185. { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
  186. { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
  187. { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
  188. { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
  189. { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
  190. { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
  191. { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
  192. { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
  193. { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
  194. { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
  195. { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
  196. { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
  197. { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
  198. { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
  199. { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
  200. { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
  201. { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
  202. { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
  203. { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
  204. { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
  205. { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
  206. };
  207. static const struct ath5k_gain_opt rfgain_opt_5111 = {
  208. 4,
  209. 9,
  210. {
  211. { { 4, 1, 1, 1 }, 6 },
  212. { { 4, 0, 1, 1 }, 4 },
  213. { { 3, 1, 1, 1 }, 3 },
  214. { { 4, 0, 0, 1 }, 1 },
  215. { { 4, 1, 1, 0 }, 0 },
  216. { { 4, 0, 1, 0 }, -2 },
  217. { { 3, 1, 1, 0 }, -3 },
  218. { { 4, 0, 0, 0 }, -4 },
  219. { { 2, 1, 1, 0 }, -6 }
  220. }
  221. };
  222. /* RF5112 mode-specific init registers */
  223. static const struct ath5k_ini_rf rfregs_5112[] = {
  224. { 1, 0x98d4,
  225. /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
  226. { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
  227. { 2, 0x98d0,
  228. { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
  229. { 3, 0x98dc,
  230. { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
  231. { 6, 0x989c,
  232. { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
  233. { 6, 0x989c,
  234. { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
  235. { 6, 0x989c,
  236. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  237. { 6, 0x989c,
  238. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  239. { 6, 0x989c,
  240. { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
  241. { 6, 0x989c,
  242. { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
  243. { 6, 0x989c,
  244. { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
  245. { 6, 0x989c,
  246. { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
  247. { 6, 0x989c,
  248. { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
  249. { 6, 0x989c,
  250. { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
  251. { 6, 0x989c,
  252. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  253. { 6, 0x989c,
  254. { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
  255. { 6, 0x989c,
  256. { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
  257. { 6, 0x989c,
  258. { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
  259. { 6, 0x989c,
  260. { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
  261. { 6, 0x989c,
  262. { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
  263. { 6, 0x989c,
  264. { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
  265. { 6, 0x989c,
  266. { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
  267. { 6, 0x989c,
  268. { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
  269. { 6, 0x989c,
  270. { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
  271. { 6, 0x989c,
  272. { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
  273. { 6, 0x989c,
  274. { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
  275. { 6, 0x989c,
  276. { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
  277. { 6, 0x989c,
  278. { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
  279. { 6, 0x989c,
  280. { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
  281. { 6, 0x989c,
  282. { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
  283. { 6, 0x989c,
  284. { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
  285. { 6, 0x989c,
  286. { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
  287. { 6, 0x989c,
  288. { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
  289. { 6, 0x989c,
  290. { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
  291. { 6, 0x989c,
  292. { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
  293. { 6, 0x989c,
  294. { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
  295. { 6, 0x989c,
  296. { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
  297. { 6, 0x989c,
  298. { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
  299. { 6, 0x989c,
  300. { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
  301. { 6, 0x989c,
  302. { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
  303. { 6, 0x989c,
  304. { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
  305. { 6, 0x98d0,
  306. { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
  307. { 7, 0x989c,
  308. { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
  309. { 7, 0x989c,
  310. { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
  311. { 7, 0x989c,
  312. { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
  313. { 7, 0x989c,
  314. { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
  315. { 7, 0x989c,
  316. { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
  317. { 7, 0x989c,
  318. { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
  319. { 7, 0x989c,
  320. { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
  321. { 7, 0x989c,
  322. { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
  323. { 7, 0x989c,
  324. { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
  325. { 7, 0x989c,
  326. { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
  327. { 7, 0x989c,
  328. { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
  329. { 7, 0x989c,
  330. { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
  331. { 7, 0x98c4,
  332. { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
  333. };
  334. /* RF5112A mode-specific init registers */
  335. static const struct ath5k_ini_rf rfregs_5112a[] = {
  336. { 1, 0x98d4,
  337. /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
  338. { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
  339. { 2, 0x98d0,
  340. { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
  341. { 3, 0x98dc,
  342. { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
  343. { 6, 0x989c,
  344. { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
  345. { 6, 0x989c,
  346. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  347. { 6, 0x989c,
  348. { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
  349. { 6, 0x989c,
  350. { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
  351. { 6, 0x989c,
  352. { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
  353. { 6, 0x989c,
  354. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  355. { 6, 0x989c,
  356. { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
  357. { 6, 0x989c,
  358. { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
  359. { 6, 0x989c,
  360. { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
  361. { 6, 0x989c,
  362. { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
  363. { 6, 0x989c,
  364. { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
  365. { 6, 0x989c,
  366. { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
  367. { 6, 0x989c,
  368. { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
  369. { 6, 0x989c,
  370. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  371. { 6, 0x989c,
  372. { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
  373. { 6, 0x989c,
  374. { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
  375. { 6, 0x989c,
  376. { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
  377. { 6, 0x989c,
  378. { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
  379. { 6, 0x989c,
  380. { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
  381. { 6, 0x989c,
  382. { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
  383. { 6, 0x989c,
  384. { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
  385. { 6, 0x989c,
  386. { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
  387. { 6, 0x989c,
  388. { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
  389. { 6, 0x989c,
  390. { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
  391. { 6, 0x989c,
  392. { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
  393. { 6, 0x989c,
  394. { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
  395. { 6, 0x989c,
  396. { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
  397. { 6, 0x989c,
  398. { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
  399. { 6, 0x989c,
  400. { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
  401. { 6, 0x989c,
  402. { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
  403. { 6, 0x989c,
  404. { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
  405. { 6, 0x989c,
  406. { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
  407. { 6, 0x989c,
  408. { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
  409. { 6, 0x989c,
  410. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  411. { 6, 0x989c,
  412. { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
  413. { 6, 0x989c,
  414. { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
  415. { 6, 0x989c,
  416. { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
  417. { 6, 0x989c,
  418. { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
  419. { 6, 0x989c,
  420. { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
  421. { 6, 0x98d8,
  422. { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
  423. { 7, 0x989c,
  424. { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
  425. { 7, 0x989c,
  426. { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
  427. { 7, 0x989c,
  428. { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
  429. { 7, 0x989c,
  430. { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
  431. { 7, 0x989c,
  432. { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
  433. { 7, 0x989c,
  434. { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
  435. { 7, 0x989c,
  436. { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
  437. { 7, 0x989c,
  438. { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
  439. { 7, 0x989c,
  440. { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
  441. { 7, 0x989c,
  442. { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
  443. { 7, 0x989c,
  444. { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
  445. { 7, 0x989c,
  446. { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
  447. { 7, 0x98c4,
  448. { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
  449. };
  450. static const struct ath5k_ini_rf rfregs_2112a[] = {
  451. { 1, AR5K_RF_BUFFER_CONTROL_4,
  452. /* mode b mode g mode gTurbo */
  453. { 0x00000020, 0x00000020, 0x00000020 } },
  454. { 2, AR5K_RF_BUFFER_CONTROL_3,
  455. { 0x03060408, 0x03060408, 0x03070408 } },
  456. { 3, AR5K_RF_BUFFER_CONTROL_6,
  457. { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
  458. { 6, AR5K_RF_BUFFER,
  459. { 0x0a000000, 0x0a000000, 0x0a000000 } },
  460. { 6, AR5K_RF_BUFFER,
  461. { 0x00000000, 0x00000000, 0x00000000 } },
  462. { 6, AR5K_RF_BUFFER,
  463. { 0x00800000, 0x00800000, 0x00800000 } },
  464. { 6, AR5K_RF_BUFFER,
  465. { 0x002a0000, 0x002a0000, 0x002a0000 } },
  466. { 6, AR5K_RF_BUFFER,
  467. { 0x00010000, 0x00010000, 0x00010000 } },
  468. { 6, AR5K_RF_BUFFER,
  469. { 0x00000000, 0x00000000, 0x00000000 } },
  470. { 6, AR5K_RF_BUFFER,
  471. { 0x00180000, 0x00180000, 0x00180000 } },
  472. { 6, AR5K_RF_BUFFER,
  473. { 0x006e0000, 0x006e0000, 0x006e0000 } },
  474. { 6, AR5K_RF_BUFFER,
  475. { 0x00c70000, 0x00c70000, 0x00c70000 } },
  476. { 6, AR5K_RF_BUFFER,
  477. { 0x004b0000, 0x004b0000, 0x004b0000 } },
  478. { 6, AR5K_RF_BUFFER,
  479. { 0x04480000, 0x04480000, 0x04480000 } },
  480. { 6, AR5K_RF_BUFFER,
  481. { 0x002a0000, 0x002a0000, 0x002a0000 } },
  482. { 6, AR5K_RF_BUFFER,
  483. { 0x00e40000, 0x00e40000, 0x00e40000 } },
  484. { 6, AR5K_RF_BUFFER,
  485. { 0x00000000, 0x00000000, 0x00000000 } },
  486. { 6, AR5K_RF_BUFFER,
  487. { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
  488. { 6, AR5K_RF_BUFFER,
  489. { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
  490. { 6, AR5K_RF_BUFFER,
  491. { 0x043f0000, 0x043f0000, 0x043f0000 } },
  492. { 6, AR5K_RF_BUFFER,
  493. { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
  494. { 6, AR5K_RF_BUFFER,
  495. { 0x02190000, 0x02190000, 0x02190000 } },
  496. { 6, AR5K_RF_BUFFER,
  497. { 0x00240000, 0x00240000, 0x00240000 } },
  498. { 6, AR5K_RF_BUFFER,
  499. { 0x00b40000, 0x00b40000, 0x00b40000 } },
  500. { 6, AR5K_RF_BUFFER,
  501. { 0x00990000, 0x00990000, 0x00990000 } },
  502. { 6, AR5K_RF_BUFFER,
  503. { 0x00500000, 0x00500000, 0x00500000 } },
  504. { 6, AR5K_RF_BUFFER,
  505. { 0x002a0000, 0x002a0000, 0x002a0000 } },
  506. { 6, AR5K_RF_BUFFER,
  507. { 0x00120000, 0x00120000, 0x00120000 } },
  508. { 6, AR5K_RF_BUFFER,
  509. { 0xc0320000, 0xc0320000, 0xc0320000 } },
  510. { 6, AR5K_RF_BUFFER,
  511. { 0x01740000, 0x01740000, 0x01740000 } },
  512. { 6, AR5K_RF_BUFFER,
  513. { 0x00110000, 0x00110000, 0x00110000 } },
  514. { 6, AR5K_RF_BUFFER,
  515. { 0x86280000, 0x86280000, 0x86280000 } },
  516. { 6, AR5K_RF_BUFFER,
  517. { 0x31840000, 0x31840000, 0x31840000 } },
  518. { 6, AR5K_RF_BUFFER,
  519. { 0x00f20080, 0x00f20080, 0x00f20080 } },
  520. { 6, AR5K_RF_BUFFER,
  521. { 0x00070019, 0x00070019, 0x00070019 } },
  522. { 6, AR5K_RF_BUFFER,
  523. { 0x00000000, 0x00000000, 0x00000000 } },
  524. { 6, AR5K_RF_BUFFER,
  525. { 0x00000000, 0x00000000, 0x00000000 } },
  526. { 6, AR5K_RF_BUFFER,
  527. { 0x000000b2, 0x000000b2, 0x000000b2 } },
  528. { 6, AR5K_RF_BUFFER,
  529. { 0x00b02184, 0x00b02184, 0x00b02184 } },
  530. { 6, AR5K_RF_BUFFER,
  531. { 0x004125a4, 0x004125a4, 0x004125a4 } },
  532. { 6, AR5K_RF_BUFFER,
  533. { 0x00119220, 0x00119220, 0x00119220 } },
  534. { 6, AR5K_RF_BUFFER,
  535. { 0x001a4800, 0x001a4800, 0x001a4800 } },
  536. { 6, AR5K_RF_BUFFER_CONTROL_5,
  537. { 0x000b0230, 0x000b0230, 0x000b0230 } },
  538. { 7, AR5K_RF_BUFFER,
  539. { 0x00000094, 0x00000094, 0x00000094 } },
  540. { 7, AR5K_RF_BUFFER,
  541. { 0x00000091, 0x00000091, 0x00000091 } },
  542. { 7, AR5K_RF_BUFFER,
  543. { 0x00000012, 0x00000012, 0x00000012 } },
  544. { 7, AR5K_RF_BUFFER,
  545. { 0x00000080, 0x00000080, 0x00000080 } },
  546. { 7, AR5K_RF_BUFFER,
  547. { 0x000000d9, 0x000000d9, 0x000000d9 } },
  548. { 7, AR5K_RF_BUFFER,
  549. { 0x00000060, 0x00000060, 0x00000060 } },
  550. { 7, AR5K_RF_BUFFER,
  551. { 0x000000f0, 0x000000f0, 0x000000f0 } },
  552. { 7, AR5K_RF_BUFFER,
  553. { 0x000000a2, 0x000000a2, 0x000000a2 } },
  554. { 7, AR5K_RF_BUFFER,
  555. { 0x00000052, 0x00000052, 0x00000052 } },
  556. { 7, AR5K_RF_BUFFER,
  557. { 0x000000d4, 0x000000d4, 0x000000d4 } },
  558. { 7, AR5K_RF_BUFFER,
  559. { 0x000014cc, 0x000014cc, 0x000014cc } },
  560. { 7, AR5K_RF_BUFFER,
  561. { 0x0000048c, 0x0000048c, 0x0000048c } },
  562. { 7, AR5K_RF_BUFFER_CONTROL_1,
  563. { 0x00000003, 0x00000003, 0x00000003 } },
  564. };
  565. /* RF5413/5414 mode-specific init registers */
  566. static const struct ath5k_ini_rf rfregs_5413[] = {
  567. { 1, 0x98d4,
  568. /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
  569. { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
  570. { 2, 0x98d0,
  571. { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
  572. { 3, 0x98dc,
  573. { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
  574. { 6, 0x989c,
  575. { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
  576. { 6, 0x989c,
  577. { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
  578. { 6, 0x989c,
  579. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  580. { 6, 0x989c,
  581. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  582. { 6, 0x989c,
  583. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  584. { 6, 0x989c,
  585. { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
  586. { 6, 0x989c,
  587. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  588. { 6, 0x989c,
  589. { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
  590. { 6, 0x989c,
  591. { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
  592. { 6, 0x989c,
  593. { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
  594. { 6, 0x989c,
  595. { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
  596. { 6, 0x989c,
  597. { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
  598. { 6, 0x989c,
  599. { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
  600. { 6, 0x989c,
  601. { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
  602. { 6, 0x989c,
  603. { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
  604. { 6, 0x989c,
  605. { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
  606. { 6, 0x989c,
  607. { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
  608. { 6, 0x989c,
  609. { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
  610. { 6, 0x989c,
  611. { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
  612. { 6, 0x989c,
  613. { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
  614. { 6, 0x989c,
  615. { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
  616. { 6, 0x989c,
  617. { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
  618. { 6, 0x989c,
  619. { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
  620. { 6, 0x989c,
  621. { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
  622. { 6, 0x989c,
  623. { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
  624. { 6, 0x989c,
  625. { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
  626. { 6, 0x989c,
  627. { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
  628. { 6, 0x989c,
  629. { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
  630. { 6, 0x989c,
  631. { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
  632. { 6, 0x989c,
  633. { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
  634. { 6, 0x989c,
  635. { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
  636. { 6, 0x989c,
  637. { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
  638. { 6, 0x989c,
  639. { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
  640. { 6, 0x989c,
  641. { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
  642. { 6, 0x989c,
  643. { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
  644. { 6, 0x989c,
  645. { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
  646. { 6, 0x98c8,
  647. { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
  648. { 7, 0x989c,
  649. { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
  650. { 7, 0x989c,
  651. { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
  652. { 7, 0x98cc,
  653. { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
  654. };
  655. /* RF2413/2414 mode-specific init registers */
  656. static const struct ath5k_ini_rf rfregs_2413[] = {
  657. { 1, AR5K_RF_BUFFER_CONTROL_4,
  658. /* mode b mode g mode gTurbo */
  659. { 0x00000020, 0x00000020, 0x00000020 } },
  660. { 2, AR5K_RF_BUFFER_CONTROL_3,
  661. { 0x02001408, 0x02001408, 0x02001408 } },
  662. { 3, AR5K_RF_BUFFER_CONTROL_6,
  663. { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
  664. { 6, AR5K_RF_BUFFER,
  665. { 0xf0000000, 0xf0000000, 0xf0000000 } },
  666. { 6, AR5K_RF_BUFFER,
  667. { 0x00000000, 0x00000000, 0x00000000 } },
  668. { 6, AR5K_RF_BUFFER,
  669. { 0x03000000, 0x03000000, 0x03000000 } },
  670. { 6, AR5K_RF_BUFFER,
  671. { 0x00000000, 0x00000000, 0x00000000 } },
  672. { 6, AR5K_RF_BUFFER,
  673. { 0x00000000, 0x00000000, 0x00000000 } },
  674. { 6, AR5K_RF_BUFFER,
  675. { 0x00000000, 0x00000000, 0x00000000 } },
  676. { 6, AR5K_RF_BUFFER,
  677. { 0x00000000, 0x00000000, 0x00000000 } },
  678. { 6, AR5K_RF_BUFFER,
  679. { 0x00000000, 0x00000000, 0x00000000 } },
  680. { 6, AR5K_RF_BUFFER,
  681. { 0x40400000, 0x40400000, 0x40400000 } },
  682. { 6, AR5K_RF_BUFFER,
  683. { 0x65050000, 0x65050000, 0x65050000 } },
  684. { 6, AR5K_RF_BUFFER,
  685. { 0x00000000, 0x00000000, 0x00000000 } },
  686. { 6, AR5K_RF_BUFFER,
  687. { 0x00000000, 0x00000000, 0x00000000 } },
  688. { 6, AR5K_RF_BUFFER,
  689. { 0x00420000, 0x00420000, 0x00420000 } },
  690. { 6, AR5K_RF_BUFFER,
  691. { 0x00b50000, 0x00b50000, 0x00b50000 } },
  692. { 6, AR5K_RF_BUFFER,
  693. { 0x00030000, 0x00030000, 0x00030000 } },
  694. { 6, AR5K_RF_BUFFER,
  695. { 0x00f70000, 0x00f70000, 0x00f70000 } },
  696. { 6, AR5K_RF_BUFFER,
  697. { 0x009d0000, 0x009d0000, 0x009d0000 } },
  698. { 6, AR5K_RF_BUFFER,
  699. { 0x00220000, 0x00220000, 0x00220000 } },
  700. { 6, AR5K_RF_BUFFER,
  701. { 0x04220000, 0x04220000, 0x04220000 } },
  702. { 6, AR5K_RF_BUFFER,
  703. { 0x00230018, 0x00230018, 0x00230018 } },
  704. { 6, AR5K_RF_BUFFER,
  705. { 0x00280050, 0x00280050, 0x00280050 } },
  706. { 6, AR5K_RF_BUFFER,
  707. { 0x005000c3, 0x005000c3, 0x005000c3 } },
  708. { 6, AR5K_RF_BUFFER,
  709. { 0x0004007f, 0x0004007f, 0x0004007f } },
  710. { 6, AR5K_RF_BUFFER,
  711. { 0x00000458, 0x00000458, 0x00000458 } },
  712. { 6, AR5K_RF_BUFFER,
  713. { 0x00000000, 0x00000000, 0x00000000 } },
  714. { 6, AR5K_RF_BUFFER,
  715. { 0x0000c000, 0x0000c000, 0x0000c000 } },
  716. { 6, AR5K_RF_BUFFER_CONTROL_5,
  717. { 0x00400230, 0x00400230, 0x00400230 } },
  718. { 7, AR5K_RF_BUFFER,
  719. { 0x00006400, 0x00006400, 0x00006400 } },
  720. { 7, AR5K_RF_BUFFER,
  721. { 0x00000800, 0x00000800, 0x00000800 } },
  722. { 7, AR5K_RF_BUFFER_CONTROL_2,
  723. { 0x0000000e, 0x0000000e, 0x0000000e } },
  724. };
  725. /* RF2425 mode-specific init registers */
  726. static const struct ath5k_ini_rf rfregs_2425[] = {
  727. { 1, AR5K_RF_BUFFER_CONTROL_4,
  728. /* mode g mode gTurbo */
  729. { 0x00000020, 0x00000020 } },
  730. { 2, AR5K_RF_BUFFER_CONTROL_3,
  731. { 0x02001408, 0x02001408 } },
  732. { 3, AR5K_RF_BUFFER_CONTROL_6,
  733. { 0x00e020c0, 0x00e020c0 } },
  734. { 6, AR5K_RF_BUFFER,
  735. { 0x10000000, 0x10000000 } },
  736. { 6, AR5K_RF_BUFFER,
  737. { 0x00000000, 0x00000000 } },
  738. { 6, AR5K_RF_BUFFER,
  739. { 0x00000000, 0x00000000 } },
  740. { 6, AR5K_RF_BUFFER,
  741. { 0x00000000, 0x00000000 } },
  742. { 6, AR5K_RF_BUFFER,
  743. { 0x00000000, 0x00000000 } },
  744. { 6, AR5K_RF_BUFFER,
  745. { 0x00000000, 0x00000000 } },
  746. { 6, AR5K_RF_BUFFER,
  747. { 0x00000000, 0x00000000 } },
  748. { 6, AR5K_RF_BUFFER,
  749. { 0x00000000, 0x00000000 } },
  750. { 6, AR5K_RF_BUFFER,
  751. { 0x00000000, 0x00000000 } },
  752. { 6, AR5K_RF_BUFFER,
  753. { 0x00000000, 0x00000000 } },
  754. { 6, AR5K_RF_BUFFER,
  755. { 0x00000000, 0x00000000 } },
  756. { 6, AR5K_RF_BUFFER,
  757. { 0x002a0000, 0x002a0000 } },
  758. { 6, AR5K_RF_BUFFER,
  759. { 0x00000000, 0x00000000 } },
  760. { 6, AR5K_RF_BUFFER,
  761. { 0x00000000, 0x00000000 } },
  762. { 6, AR5K_RF_BUFFER,
  763. { 0x00100000, 0x00100000 } },
  764. { 6, AR5K_RF_BUFFER,
  765. { 0x00020000, 0x00020000 } },
  766. { 6, AR5K_RF_BUFFER,
  767. { 0x00730000, 0x00730000 } },
  768. { 6, AR5K_RF_BUFFER,
  769. { 0x00f80000, 0x00f80000 } },
  770. { 6, AR5K_RF_BUFFER,
  771. { 0x00e70000, 0x00e70000 } },
  772. { 6, AR5K_RF_BUFFER,
  773. { 0x00140000, 0x00140000 } },
  774. { 6, AR5K_RF_BUFFER,
  775. { 0x00910040, 0x00910040 } },
  776. { 6, AR5K_RF_BUFFER,
  777. { 0x0007001a, 0x0007001a } },
  778. { 6, AR5K_RF_BUFFER,
  779. { 0x00410000, 0x00410000 } },
  780. { 6, AR5K_RF_BUFFER,
  781. { 0x00810060, 0x00810060 } },
  782. { 6, AR5K_RF_BUFFER,
  783. { 0x00020803, 0x00020803 } },
  784. { 6, AR5K_RF_BUFFER,
  785. { 0x00000000, 0x00000000 } },
  786. { 6, AR5K_RF_BUFFER,
  787. { 0x00000000, 0x00000000 } },
  788. { 6, AR5K_RF_BUFFER,
  789. { 0x00001660, 0x00001660 } },
  790. { 6, AR5K_RF_BUFFER,
  791. { 0x00001688, 0x00001688 } },
  792. { 6, AR5K_RF_BUFFER_CONTROL_1,
  793. { 0x00000001, 0x00000001 } },
  794. { 7, AR5K_RF_BUFFER,
  795. { 0x00006400, 0x00006400 } },
  796. { 7, AR5K_RF_BUFFER,
  797. { 0x00000800, 0x00000800 } },
  798. { 7, AR5K_RF_BUFFER_CONTROL_2,
  799. { 0x0000000e, 0x0000000e } },
  800. };
  801. /* Initial RF Gain settings for RF5112 */
  802. static const struct ath5k_ini_rfgain rfgain_5112[] = {
  803. /* 5Ghz 2Ghz */
  804. { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
  805. { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
  806. { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
  807. { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
  808. { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
  809. { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
  810. { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
  811. { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
  812. { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
  813. { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
  814. { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
  815. { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
  816. { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
  817. { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
  818. { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
  819. { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
  820. { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
  821. { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
  822. { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
  823. { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
  824. { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
  825. { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
  826. { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
  827. { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
  828. { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
  829. { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
  830. { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
  831. { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
  832. { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
  833. { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
  834. { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
  835. { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
  836. { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
  837. { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
  838. { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
  839. { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
  840. { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
  841. { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
  842. { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
  843. { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
  844. { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
  845. { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
  846. { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
  847. { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
  848. { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
  849. { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
  850. { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
  851. { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
  852. { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
  853. { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
  854. { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
  855. { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
  856. { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
  857. { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
  858. { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
  859. { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
  860. { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
  861. { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
  862. { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
  863. { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
  864. { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
  865. { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
  866. { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
  867. { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
  868. };
  869. /* Initial RF Gain settings for RF5413 */
  870. static const struct ath5k_ini_rfgain rfgain_5413[] = {
  871. /* 5Ghz 2Ghz */
  872. { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
  873. { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
  874. { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
  875. { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
  876. { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
  877. { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
  878. { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
  879. { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
  880. { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
  881. { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
  882. { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
  883. { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
  884. { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
  885. { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
  886. { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
  887. { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
  888. { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
  889. { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
  890. { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
  891. { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
  892. { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
  893. { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
  894. { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
  895. { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
  896. { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
  897. { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
  898. { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
  899. { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
  900. { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
  901. { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
  902. { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
  903. { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
  904. { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
  905. { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
  906. { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
  907. { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
  908. { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
  909. { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
  910. { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
  911. { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
  912. { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
  913. { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
  914. { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
  915. { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
  916. { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
  917. { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
  918. { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
  919. { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
  920. { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
  921. { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
  922. { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
  923. { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
  924. { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
  925. { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
  926. { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
  927. { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
  928. { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
  929. { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
  930. { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
  931. { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
  932. { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
  933. { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
  934. { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
  935. { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
  936. };
  937. /* Initial RF Gain settings for RF2413 */
  938. static const struct ath5k_ini_rfgain rfgain_2413[] = {
  939. { AR5K_RF_GAIN(0), { 0x00000000 } },
  940. { AR5K_RF_GAIN(1), { 0x00000040 } },
  941. { AR5K_RF_GAIN(2), { 0x00000080 } },
  942. { AR5K_RF_GAIN(3), { 0x00000181 } },
  943. { AR5K_RF_GAIN(4), { 0x000001c1 } },
  944. { AR5K_RF_GAIN(5), { 0x00000001 } },
  945. { AR5K_RF_GAIN(6), { 0x00000041 } },
  946. { AR5K_RF_GAIN(7), { 0x00000081 } },
  947. { AR5K_RF_GAIN(8), { 0x00000168 } },
  948. { AR5K_RF_GAIN(9), { 0x000001a8 } },
  949. { AR5K_RF_GAIN(10), { 0x000001e8 } },
  950. { AR5K_RF_GAIN(11), { 0x00000028 } },
  951. { AR5K_RF_GAIN(12), { 0x00000068 } },
  952. { AR5K_RF_GAIN(13), { 0x00000189 } },
  953. { AR5K_RF_GAIN(14), { 0x000001c9 } },
  954. { AR5K_RF_GAIN(15), { 0x00000009 } },
  955. { AR5K_RF_GAIN(16), { 0x00000049 } },
  956. { AR5K_RF_GAIN(17), { 0x00000089 } },
  957. { AR5K_RF_GAIN(18), { 0x00000190 } },
  958. { AR5K_RF_GAIN(19), { 0x000001d0 } },
  959. { AR5K_RF_GAIN(20), { 0x00000010 } },
  960. { AR5K_RF_GAIN(21), { 0x00000050 } },
  961. { AR5K_RF_GAIN(22), { 0x00000090 } },
  962. { AR5K_RF_GAIN(23), { 0x00000191 } },
  963. { AR5K_RF_GAIN(24), { 0x000001d1 } },
  964. { AR5K_RF_GAIN(25), { 0x00000011 } },
  965. { AR5K_RF_GAIN(26), { 0x00000051 } },
  966. { AR5K_RF_GAIN(27), { 0x00000091 } },
  967. { AR5K_RF_GAIN(28), { 0x00000178 } },
  968. { AR5K_RF_GAIN(29), { 0x000001b8 } },
  969. { AR5K_RF_GAIN(30), { 0x000001f8 } },
  970. { AR5K_RF_GAIN(31), { 0x00000038 } },
  971. { AR5K_RF_GAIN(32), { 0x00000078 } },
  972. { AR5K_RF_GAIN(33), { 0x00000199 } },
  973. { AR5K_RF_GAIN(34), { 0x000001d9 } },
  974. { AR5K_RF_GAIN(35), { 0x00000019 } },
  975. { AR5K_RF_GAIN(36), { 0x00000059 } },
  976. { AR5K_RF_GAIN(37), { 0x00000099 } },
  977. { AR5K_RF_GAIN(38), { 0x000000d9 } },
  978. { AR5K_RF_GAIN(39), { 0x000000f9 } },
  979. { AR5K_RF_GAIN(40), { 0x000000f9 } },
  980. { AR5K_RF_GAIN(41), { 0x000000f9 } },
  981. { AR5K_RF_GAIN(42), { 0x000000f9 } },
  982. { AR5K_RF_GAIN(43), { 0x000000f9 } },
  983. { AR5K_RF_GAIN(44), { 0x000000f9 } },
  984. { AR5K_RF_GAIN(45), { 0x000000f9 } },
  985. { AR5K_RF_GAIN(46), { 0x000000f9 } },
  986. { AR5K_RF_GAIN(47), { 0x000000f9 } },
  987. { AR5K_RF_GAIN(48), { 0x000000f9 } },
  988. { AR5K_RF_GAIN(49), { 0x000000f9 } },
  989. { AR5K_RF_GAIN(50), { 0x000000f9 } },
  990. { AR5K_RF_GAIN(51), { 0x000000f9 } },
  991. { AR5K_RF_GAIN(52), { 0x000000f9 } },
  992. { AR5K_RF_GAIN(53), { 0x000000f9 } },
  993. { AR5K_RF_GAIN(54), { 0x000000f9 } },
  994. { AR5K_RF_GAIN(55), { 0x000000f9 } },
  995. { AR5K_RF_GAIN(56), { 0x000000f9 } },
  996. { AR5K_RF_GAIN(57), { 0x000000f9 } },
  997. { AR5K_RF_GAIN(58), { 0x000000f9 } },
  998. { AR5K_RF_GAIN(59), { 0x000000f9 } },
  999. { AR5K_RF_GAIN(60), { 0x000000f9 } },
  1000. { AR5K_RF_GAIN(61), { 0x000000f9 } },
  1001. { AR5K_RF_GAIN(62), { 0x000000f9 } },
  1002. { AR5K_RF_GAIN(63), { 0x000000f9 } },
  1003. };
  1004. /* Initial RF Gain settings for RF2425 */
  1005. static const struct ath5k_ini_rfgain rfgain_2425[] = {
  1006. { AR5K_RF_GAIN(0), { 0x00000000 } },
  1007. { AR5K_RF_GAIN(1), { 0x00000040 } },
  1008. { AR5K_RF_GAIN(2), { 0x00000080 } },
  1009. { AR5K_RF_GAIN(3), { 0x00000181 } },
  1010. { AR5K_RF_GAIN(4), { 0x000001c1 } },
  1011. { AR5K_RF_GAIN(5), { 0x00000001 } },
  1012. { AR5K_RF_GAIN(6), { 0x00000041 } },
  1013. { AR5K_RF_GAIN(7), { 0x00000081 } },
  1014. { AR5K_RF_GAIN(8), { 0x00000188 } },
  1015. { AR5K_RF_GAIN(9), { 0x000001c8 } },
  1016. { AR5K_RF_GAIN(10), { 0x00000008 } },
  1017. { AR5K_RF_GAIN(11), { 0x00000048 } },
  1018. { AR5K_RF_GAIN(12), { 0x00000088 } },
  1019. { AR5K_RF_GAIN(13), { 0x00000189 } },
  1020. { AR5K_RF_GAIN(14), { 0x000001c9 } },
  1021. { AR5K_RF_GAIN(15), { 0x00000009 } },
  1022. { AR5K_RF_GAIN(16), { 0x00000049 } },
  1023. { AR5K_RF_GAIN(17), { 0x00000089 } },
  1024. { AR5K_RF_GAIN(18), { 0x000001b0 } },
  1025. { AR5K_RF_GAIN(19), { 0x000001f0 } },
  1026. { AR5K_RF_GAIN(20), { 0x00000030 } },
  1027. { AR5K_RF_GAIN(21), { 0x00000070 } },
  1028. { AR5K_RF_GAIN(22), { 0x00000171 } },
  1029. { AR5K_RF_GAIN(23), { 0x000001b1 } },
  1030. { AR5K_RF_GAIN(24), { 0x000001f1 } },
  1031. { AR5K_RF_GAIN(25), { 0x00000031 } },
  1032. { AR5K_RF_GAIN(26), { 0x00000071 } },
  1033. { AR5K_RF_GAIN(27), { 0x000001b8 } },
  1034. { AR5K_RF_GAIN(28), { 0x000001f8 } },
  1035. { AR5K_RF_GAIN(29), { 0x00000038 } },
  1036. { AR5K_RF_GAIN(30), { 0x00000078 } },
  1037. { AR5K_RF_GAIN(31), { 0x000000b8 } },
  1038. { AR5K_RF_GAIN(32), { 0x000001b9 } },
  1039. { AR5K_RF_GAIN(33), { 0x000001f9 } },
  1040. { AR5K_RF_GAIN(34), { 0x00000039 } },
  1041. { AR5K_RF_GAIN(35), { 0x00000079 } },
  1042. { AR5K_RF_GAIN(36), { 0x000000b9 } },
  1043. { AR5K_RF_GAIN(37), { 0x000000f9 } },
  1044. { AR5K_RF_GAIN(38), { 0x000000f9 } },
  1045. { AR5K_RF_GAIN(39), { 0x000000f9 } },
  1046. { AR5K_RF_GAIN(40), { 0x000000f9 } },
  1047. { AR5K_RF_GAIN(41), { 0x000000f9 } },
  1048. { AR5K_RF_GAIN(42), { 0x000000f9 } },
  1049. { AR5K_RF_GAIN(43), { 0x000000f9 } },
  1050. { AR5K_RF_GAIN(44), { 0x000000f9 } },
  1051. { AR5K_RF_GAIN(45), { 0x000000f9 } },
  1052. { AR5K_RF_GAIN(46), { 0x000000f9 } },
  1053. { AR5K_RF_GAIN(47), { 0x000000f9 } },
  1054. { AR5K_RF_GAIN(48), { 0x000000f9 } },
  1055. { AR5K_RF_GAIN(49), { 0x000000f9 } },
  1056. { AR5K_RF_GAIN(50), { 0x000000f9 } },
  1057. { AR5K_RF_GAIN(51), { 0x000000f9 } },
  1058. { AR5K_RF_GAIN(52), { 0x000000f9 } },
  1059. { AR5K_RF_GAIN(53), { 0x000000f9 } },
  1060. { AR5K_RF_GAIN(54), { 0x000000f9 } },
  1061. { AR5K_RF_GAIN(55), { 0x000000f9 } },
  1062. { AR5K_RF_GAIN(56), { 0x000000f9 } },
  1063. { AR5K_RF_GAIN(57), { 0x000000f9 } },
  1064. { AR5K_RF_GAIN(58), { 0x000000f9 } },
  1065. { AR5K_RF_GAIN(59), { 0x000000f9 } },
  1066. { AR5K_RF_GAIN(60), { 0x000000f9 } },
  1067. { AR5K_RF_GAIN(61), { 0x000000f9 } },
  1068. { AR5K_RF_GAIN(62), { 0x000000f9 } },
  1069. { AR5K_RF_GAIN(63), { 0x000000f9 } },
  1070. };
  1071. static const struct ath5k_gain_opt rfgain_opt_5112 = {
  1072. 1,
  1073. 8,
  1074. {
  1075. { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
  1076. { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
  1077. { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
  1078. { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
  1079. { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
  1080. { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
  1081. { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
  1082. { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
  1083. }
  1084. };
  1085. /*
  1086. * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
  1087. */
  1088. static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
  1089. u32 first, u32 col, bool set)
  1090. {
  1091. u32 mask, entry, last, data, shift, position;
  1092. s32 left;
  1093. int i;
  1094. data = 0;
  1095. if (rf == NULL)
  1096. /* should not happen */
  1097. return 0;
  1098. if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
  1099. ATH5K_PRINTF("invalid values at offset %u\n", offset);
  1100. return 0;
  1101. }
  1102. entry = ((first - 1) / 8) + offset;
  1103. position = (first - 1) % 8;
  1104. if (set)
  1105. data = ath5k_hw_bitswap(reg, bits);
  1106. for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
  1107. last = (position + left > 8) ? 8 : position + left;
  1108. mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
  1109. if (set) {
  1110. rf[entry] &= ~mask;
  1111. rf[entry] |= ((data << position) << (col * 8)) & mask;
  1112. data >>= (8 - position);
  1113. } else {
  1114. data = (((rf[entry] & mask) >> (col * 8)) >> position)
  1115. << shift;
  1116. shift += last - position;
  1117. }
  1118. left -= 8 - position;
  1119. }
  1120. data = set ? 1 : ath5k_hw_bitswap(data, bits);
  1121. return data;
  1122. }
  1123. static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
  1124. {
  1125. u32 mix, step;
  1126. u32 *rf;
  1127. if (ah->ah_rf_banks == NULL)
  1128. return 0;
  1129. rf = ah->ah_rf_banks;
  1130. ah->ah_gain.g_f_corr = 0;
  1131. if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
  1132. return 0;
  1133. step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
  1134. mix = ah->ah_gain.g_step->gos_param[0];
  1135. switch (mix) {
  1136. case 3:
  1137. ah->ah_gain.g_f_corr = step * 2;
  1138. break;
  1139. case 2:
  1140. ah->ah_gain.g_f_corr = (step - 5) * 2;
  1141. break;
  1142. case 1:
  1143. ah->ah_gain.g_f_corr = step;
  1144. break;
  1145. default:
  1146. ah->ah_gain.g_f_corr = 0;
  1147. break;
  1148. }
  1149. return ah->ah_gain.g_f_corr;
  1150. }
  1151. static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
  1152. {
  1153. u32 step, mix, level[4];
  1154. u32 *rf;
  1155. if (ah->ah_rf_banks == NULL)
  1156. return false;
  1157. rf = ah->ah_rf_banks;
  1158. if (ah->ah_radio == AR5K_RF5111) {
  1159. step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
  1160. false);
  1161. level[0] = 0;
  1162. level[1] = (step == 0x3f) ? 0x32 : step + 4;
  1163. level[2] = (step != 0x3f) ? 0x40 : level[0];
  1164. level[3] = level[2] + 0x32;
  1165. ah->ah_gain.g_high = level[3] -
  1166. (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
  1167. ah->ah_gain.g_low = level[0] +
  1168. (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
  1169. } else {
  1170. mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
  1171. false);
  1172. level[0] = level[2] = 0;
  1173. if (mix == 1) {
  1174. level[1] = level[3] = 83;
  1175. } else {
  1176. level[1] = level[3] = 107;
  1177. ah->ah_gain.g_high = 55;
  1178. }
  1179. }
  1180. return (ah->ah_gain.g_current >= level[0] &&
  1181. ah->ah_gain.g_current <= level[1]) ||
  1182. (ah->ah_gain.g_current >= level[2] &&
  1183. ah->ah_gain.g_current <= level[3]);
  1184. }
  1185. static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
  1186. {
  1187. const struct ath5k_gain_opt *go;
  1188. int ret = 0;
  1189. switch (ah->ah_radio) {
  1190. case AR5K_RF5111:
  1191. go = &rfgain_opt_5111;
  1192. break;
  1193. case AR5K_RF5112:
  1194. go = &rfgain_opt_5112;
  1195. break;
  1196. default:
  1197. return 0;
  1198. }
  1199. ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
  1200. if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
  1201. if (ah->ah_gain.g_step_idx == 0)
  1202. return -1;
  1203. for (ah->ah_gain.g_target = ah->ah_gain.g_current;
  1204. ah->ah_gain.g_target >= ah->ah_gain.g_high &&
  1205. ah->ah_gain.g_step_idx > 0;
  1206. ah->ah_gain.g_step =
  1207. &go->go_step[ah->ah_gain.g_step_idx])
  1208. ah->ah_gain.g_target -= 2 *
  1209. (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
  1210. ah->ah_gain.g_step->gos_gain);
  1211. ret = 1;
  1212. goto done;
  1213. }
  1214. if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
  1215. if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
  1216. return -2;
  1217. for (ah->ah_gain.g_target = ah->ah_gain.g_current;
  1218. ah->ah_gain.g_target <= ah->ah_gain.g_low &&
  1219. ah->ah_gain.g_step_idx < go->go_steps_count-1;
  1220. ah->ah_gain.g_step =
  1221. &go->go_step[ah->ah_gain.g_step_idx])
  1222. ah->ah_gain.g_target -= 2 *
  1223. (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
  1224. ah->ah_gain.g_step->gos_gain);
  1225. ret = 2;
  1226. goto done;
  1227. }
  1228. done:
  1229. ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  1230. "ret %d, gain step %u, current gain %u, target gain %u\n",
  1231. ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
  1232. ah->ah_gain.g_target);
  1233. return ret;
  1234. }
  1235. /*
  1236. * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
  1237. */
  1238. static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
  1239. struct ieee80211_channel *channel, unsigned int mode)
  1240. {
  1241. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1242. u32 *rf;
  1243. const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
  1244. unsigned int i;
  1245. int obdb = -1, bank = -1;
  1246. u32 ee_mode;
  1247. AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
  1248. rf = ah->ah_rf_banks;
  1249. /* Copy values to modify them */
  1250. for (i = 0; i < rf_size; i++) {
  1251. if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
  1252. ATH5K_ERR(ah->ah_sc, "invalid bank\n");
  1253. return -EINVAL;
  1254. }
  1255. if (bank != rfregs_5111[i].rf_bank) {
  1256. bank = rfregs_5111[i].rf_bank;
  1257. ah->ah_offset[bank] = i;
  1258. }
  1259. rf[i] = rfregs_5111[i].rf_value[mode];
  1260. }
  1261. /* Modify bank 0 */
  1262. if (channel->hw_value & CHANNEL_2GHZ) {
  1263. if (channel->hw_value & CHANNEL_CCK)
  1264. ee_mode = AR5K_EEPROM_MODE_11B;
  1265. else
  1266. ee_mode = AR5K_EEPROM_MODE_11G;
  1267. obdb = 0;
  1268. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
  1269. ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
  1270. return -EINVAL;
  1271. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
  1272. ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
  1273. return -EINVAL;
  1274. obdb = 1;
  1275. /* Modify bank 6 */
  1276. } else {
  1277. /* For 11a, Turbo and XR */
  1278. ee_mode = AR5K_EEPROM_MODE_11A;
  1279. obdb = channel->center_freq >= 5725 ? 3 :
  1280. (channel->center_freq >= 5500 ? 2 :
  1281. (channel->center_freq >= 5260 ? 1 :
  1282. (channel->center_freq > 4000 ? 0 : -1)));
  1283. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1284. ee->ee_pwd_84, 1, 51, 3, true))
  1285. return -EINVAL;
  1286. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1287. ee->ee_pwd_90, 1, 45, 3, true))
  1288. return -EINVAL;
  1289. }
  1290. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1291. !ee->ee_xpd[ee_mode], 1, 95, 0, true))
  1292. return -EINVAL;
  1293. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1294. ee->ee_x_gain[ee_mode], 4, 96, 0, true))
  1295. return -EINVAL;
  1296. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
  1297. ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
  1298. return -EINVAL;
  1299. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
  1300. ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
  1301. return -EINVAL;
  1302. /* Modify bank 7 */
  1303. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
  1304. ee->ee_i_gain[ee_mode], 6, 29, 0, true))
  1305. return -EINVAL;
  1306. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
  1307. ee->ee_xpd[ee_mode], 1, 4, 0, true))
  1308. return -EINVAL;
  1309. /* Write RF values */
  1310. for (i = 0; i < rf_size; i++) {
  1311. AR5K_REG_WAIT(i);
  1312. ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
  1313. }
  1314. return 0;
  1315. }
  1316. /*
  1317. * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
  1318. */
  1319. static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
  1320. struct ieee80211_channel *channel, unsigned int mode)
  1321. {
  1322. const struct ath5k_ini_rf *rf_ini;
  1323. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1324. u32 *rf;
  1325. unsigned int rf_size, i;
  1326. int obdb = -1, bank = -1;
  1327. u32 ee_mode;
  1328. AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
  1329. rf = ah->ah_rf_banks;
  1330. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
  1331. && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
  1332. rf_ini = rfregs_2112a;
  1333. rf_size = ARRAY_SIZE(rfregs_5112a);
  1334. if (mode < 2) {
  1335. ATH5K_ERR(ah->ah_sc,"invalid channel mode: %i\n",mode);
  1336. return -EINVAL;
  1337. }
  1338. mode = mode - 2; /*no a/turboa modes for 2112*/
  1339. } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
  1340. rf_ini = rfregs_5112a;
  1341. rf_size = ARRAY_SIZE(rfregs_5112a);
  1342. } else {
  1343. rf_ini = rfregs_5112;
  1344. rf_size = ARRAY_SIZE(rfregs_5112);
  1345. }
  1346. /* Copy values to modify them */
  1347. for (i = 0; i < rf_size; i++) {
  1348. if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
  1349. ATH5K_ERR(ah->ah_sc, "invalid bank\n");
  1350. return -EINVAL;
  1351. }
  1352. if (bank != rf_ini[i].rf_bank) {
  1353. bank = rf_ini[i].rf_bank;
  1354. ah->ah_offset[bank] = i;
  1355. }
  1356. rf[i] = rf_ini[i].rf_value[mode];
  1357. }
  1358. /* Modify bank 6 */
  1359. if (channel->hw_value & CHANNEL_2GHZ) {
  1360. if (channel->hw_value & CHANNEL_OFDM)
  1361. ee_mode = AR5K_EEPROM_MODE_11G;
  1362. else
  1363. ee_mode = AR5K_EEPROM_MODE_11B;
  1364. obdb = 0;
  1365. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1366. ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
  1367. return -EINVAL;
  1368. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1369. ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
  1370. return -EINVAL;
  1371. } else {
  1372. /* For 11a, Turbo and XR */
  1373. ee_mode = AR5K_EEPROM_MODE_11A;
  1374. obdb = channel->center_freq >= 5725 ? 3 :
  1375. (channel->center_freq >= 5500 ? 2 :
  1376. (channel->center_freq >= 5260 ? 1 :
  1377. (channel->center_freq > 4000 ? 0 : -1)));
  1378. if (obdb == -1)
  1379. return -EINVAL;
  1380. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1381. ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
  1382. return -EINVAL;
  1383. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1384. ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
  1385. return -EINVAL;
  1386. }
  1387. ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1388. ee->ee_x_gain[ee_mode], 2, 270, 0, true);
  1389. ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1390. ee->ee_x_gain[ee_mode], 2, 257, 0, true);
  1391. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
  1392. ee->ee_xpd[ee_mode], 1, 302, 0, true))
  1393. return -EINVAL;
  1394. /* Modify bank 7 */
  1395. if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
  1396. ee->ee_i_gain[ee_mode], 6, 14, 0, true))
  1397. return -EINVAL;
  1398. /* Write RF values */
  1399. for (i = 0; i < rf_size; i++)
  1400. ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
  1401. return 0;
  1402. }
  1403. /*
  1404. * Initialize RF5413/5414 and future chips
  1405. * (until we come up with a better solution)
  1406. */
  1407. static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
  1408. struct ieee80211_channel *channel, unsigned int mode)
  1409. {
  1410. const struct ath5k_ini_rf *rf_ini;
  1411. u32 *rf;
  1412. unsigned int rf_size, i;
  1413. int bank = -1;
  1414. AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
  1415. rf = ah->ah_rf_banks;
  1416. switch (ah->ah_radio) {
  1417. case AR5K_RF5413:
  1418. rf_ini = rfregs_5413;
  1419. rf_size = ARRAY_SIZE(rfregs_5413);
  1420. break;
  1421. case AR5K_RF2413:
  1422. rf_ini = rfregs_2413;
  1423. rf_size = ARRAY_SIZE(rfregs_2413);
  1424. if (mode < 2) {
  1425. ATH5K_ERR(ah->ah_sc,
  1426. "invalid channel mode: %i\n", mode);
  1427. return -EINVAL;
  1428. }
  1429. mode = mode - 2;
  1430. break;
  1431. case AR5K_RF2425:
  1432. rf_ini = rfregs_2425;
  1433. rf_size = ARRAY_SIZE(rfregs_2425);
  1434. if (mode < 2) {
  1435. ATH5K_ERR(ah->ah_sc,
  1436. "invalid channel mode: %i\n", mode);
  1437. return -EINVAL;
  1438. }
  1439. /* Map b to g */
  1440. if (mode == 2)
  1441. mode = 0;
  1442. else
  1443. mode = mode - 3;
  1444. break;
  1445. default:
  1446. return -EINVAL;
  1447. }
  1448. /* Copy values to modify them */
  1449. for (i = 0; i < rf_size; i++) {
  1450. if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
  1451. ATH5K_ERR(ah->ah_sc, "invalid bank\n");
  1452. return -EINVAL;
  1453. }
  1454. if (bank != rf_ini[i].rf_bank) {
  1455. bank = rf_ini[i].rf_bank;
  1456. ah->ah_offset[bank] = i;
  1457. }
  1458. rf[i] = rf_ini[i].rf_value[mode];
  1459. }
  1460. /*
  1461. * After compairing dumps from different cards
  1462. * we get the same RF_BUFFER settings (diff returns
  1463. * 0 lines). It seems that RF_BUFFER settings are static
  1464. * and are written unmodified (no EEPROM stuff
  1465. * is used because calibration data would be
  1466. * different between different cards and would result
  1467. * different RF_BUFFER settings)
  1468. */
  1469. /* Write RF values */
  1470. for (i = 0; i < rf_size; i++)
  1471. ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
  1472. return 0;
  1473. }
  1474. /*
  1475. * Initialize RF
  1476. */
  1477. int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  1478. unsigned int mode)
  1479. {
  1480. int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
  1481. int ret;
  1482. switch (ah->ah_radio) {
  1483. case AR5K_RF5111:
  1484. ah->ah_rf_banks_size = sizeof(rfregs_5111);
  1485. func = ath5k_hw_rf5111_rfregs;
  1486. break;
  1487. case AR5K_RF5112:
  1488. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
  1489. ah->ah_rf_banks_size = sizeof(rfregs_5112a);
  1490. else
  1491. ah->ah_rf_banks_size = sizeof(rfregs_5112);
  1492. func = ath5k_hw_rf5112_rfregs;
  1493. break;
  1494. case AR5K_RF5413:
  1495. ah->ah_rf_banks_size = sizeof(rfregs_5413);
  1496. func = ath5k_hw_rf5413_rfregs;
  1497. break;
  1498. case AR5K_RF2413:
  1499. ah->ah_rf_banks_size = sizeof(rfregs_2413);
  1500. func = ath5k_hw_rf5413_rfregs;
  1501. break;
  1502. case AR5K_RF2425:
  1503. ah->ah_rf_banks_size = sizeof(rfregs_2425);
  1504. func = ath5k_hw_rf5413_rfregs;
  1505. break;
  1506. default:
  1507. return -EINVAL;
  1508. }
  1509. if (ah->ah_rf_banks == NULL) {
  1510. /* XXX do extra checks? */
  1511. ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
  1512. if (ah->ah_rf_banks == NULL) {
  1513. ATH5K_ERR(ah->ah_sc, "out of memory\n");
  1514. return -ENOMEM;
  1515. }
  1516. }
  1517. ret = func(ah, channel, mode);
  1518. if (!ret)
  1519. ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
  1520. return ret;
  1521. }
  1522. int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
  1523. {
  1524. const struct ath5k_ini_rfgain *ath5k_rfg;
  1525. unsigned int i, size;
  1526. switch (ah->ah_radio) {
  1527. case AR5K_RF5111:
  1528. ath5k_rfg = rfgain_5111;
  1529. size = ARRAY_SIZE(rfgain_5111);
  1530. break;
  1531. case AR5K_RF5112:
  1532. ath5k_rfg = rfgain_5112;
  1533. size = ARRAY_SIZE(rfgain_5112);
  1534. break;
  1535. case AR5K_RF5413:
  1536. ath5k_rfg = rfgain_5413;
  1537. size = ARRAY_SIZE(rfgain_5413);
  1538. break;
  1539. case AR5K_RF2413:
  1540. ath5k_rfg = rfgain_2413;
  1541. size = ARRAY_SIZE(rfgain_2413);
  1542. freq = 0; /* only 2Ghz */
  1543. break;
  1544. case AR5K_RF2425:
  1545. ath5k_rfg = rfgain_2425;
  1546. size = ARRAY_SIZE(rfgain_2425);
  1547. freq = 0; /* only 2Ghz */
  1548. break;
  1549. default:
  1550. return -EINVAL;
  1551. }
  1552. switch (freq) {
  1553. case AR5K_INI_RFGAIN_2GHZ:
  1554. case AR5K_INI_RFGAIN_5GHZ:
  1555. break;
  1556. default:
  1557. return -EINVAL;
  1558. }
  1559. for (i = 0; i < size; i++) {
  1560. AR5K_REG_WAIT(i);
  1561. ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
  1562. (u32)ath5k_rfg[i].rfg_register);
  1563. }
  1564. return 0;
  1565. }
  1566. enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
  1567. {
  1568. u32 data, type;
  1569. ATH5K_TRACE(ah->ah_sc);
  1570. if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
  1571. ah->ah_version <= AR5K_AR5211)
  1572. return AR5K_RFGAIN_INACTIVE;
  1573. if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
  1574. goto done;
  1575. data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
  1576. if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
  1577. ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
  1578. type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
  1579. if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
  1580. ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
  1581. if (ah->ah_radio >= AR5K_RF5112) {
  1582. ath5k_hw_rfregs_gainf_corr(ah);
  1583. ah->ah_gain.g_current =
  1584. ah->ah_gain.g_current>=ah->ah_gain.g_f_corr ?
  1585. (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
  1586. 0;
  1587. }
  1588. if (ath5k_hw_rfregs_gain_readback(ah) &&
  1589. AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
  1590. ath5k_hw_rfregs_gain_adjust(ah))
  1591. ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
  1592. }
  1593. done:
  1594. return ah->ah_rf_gain;
  1595. }
  1596. int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
  1597. {
  1598. /* Initialize the gain optimization values */
  1599. switch (ah->ah_radio) {
  1600. case AR5K_RF5111:
  1601. ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
  1602. ah->ah_gain.g_step =
  1603. &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
  1604. ah->ah_gain.g_low = 20;
  1605. ah->ah_gain.g_high = 35;
  1606. ah->ah_gain.g_active = 1;
  1607. break;
  1608. case AR5K_RF5112:
  1609. ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
  1610. ah->ah_gain.g_step =
  1611. &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
  1612. ah->ah_gain.g_low = 20;
  1613. ah->ah_gain.g_high = 85;
  1614. ah->ah_gain.g_active = 1;
  1615. break;
  1616. default:
  1617. return -EINVAL;
  1618. }
  1619. return 0;
  1620. }
  1621. /**************************\
  1622. PHY/RF channel functions
  1623. \**************************/
  1624. /*
  1625. * Check if a channel is supported
  1626. */
  1627. bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
  1628. {
  1629. /* Check if the channel is in our supported range */
  1630. if (flags & CHANNEL_2GHZ) {
  1631. if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
  1632. (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
  1633. return true;
  1634. } else if (flags & CHANNEL_5GHZ)
  1635. if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
  1636. (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
  1637. return true;
  1638. return false;
  1639. }
  1640. /*
  1641. * Convertion needed for RF5110
  1642. */
  1643. static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
  1644. {
  1645. u32 athchan;
  1646. /*
  1647. * Convert IEEE channel/MHz to an internal channel value used
  1648. * by the AR5210 chipset. This has not been verified with
  1649. * newer chipsets like the AR5212A who have a completely
  1650. * different RF/PHY part.
  1651. */
  1652. athchan = (ath5k_hw_bitswap(
  1653. (ieee80211_frequency_to_channel(
  1654. channel->center_freq) - 24) / 2, 5)
  1655. << 1) | (1 << 6) | 0x1;
  1656. return athchan;
  1657. }
  1658. /*
  1659. * Set channel on RF5110
  1660. */
  1661. static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
  1662. struct ieee80211_channel *channel)
  1663. {
  1664. u32 data;
  1665. /*
  1666. * Set the channel and wait
  1667. */
  1668. data = ath5k_hw_rf5110_chan2athchan(channel);
  1669. ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
  1670. ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
  1671. mdelay(1);
  1672. return 0;
  1673. }
  1674. /*
  1675. * Convertion needed for 5111
  1676. */
  1677. static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
  1678. struct ath5k_athchan_2ghz *athchan)
  1679. {
  1680. int channel;
  1681. /* Cast this value to catch negative channel numbers (>= -19) */
  1682. channel = (int)ieee;
  1683. /*
  1684. * Map 2GHz IEEE channel to 5GHz Atheros channel
  1685. */
  1686. if (channel <= 13) {
  1687. athchan->a2_athchan = 115 + channel;
  1688. athchan->a2_flags = 0x46;
  1689. } else if (channel == 14) {
  1690. athchan->a2_athchan = 124;
  1691. athchan->a2_flags = 0x44;
  1692. } else if (channel >= 15 && channel <= 26) {
  1693. athchan->a2_athchan = ((channel - 14) * 4) + 132;
  1694. athchan->a2_flags = 0x46;
  1695. } else
  1696. return -EINVAL;
  1697. return 0;
  1698. }
  1699. /*
  1700. * Set channel on 5111
  1701. */
  1702. static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
  1703. struct ieee80211_channel *channel)
  1704. {
  1705. struct ath5k_athchan_2ghz ath5k_channel_2ghz;
  1706. unsigned int ath5k_channel =
  1707. ieee80211_frequency_to_channel(channel->center_freq);
  1708. u32 data0, data1, clock;
  1709. int ret;
  1710. /*
  1711. * Set the channel on the RF5111 radio
  1712. */
  1713. data0 = data1 = 0;
  1714. if (channel->hw_value & CHANNEL_2GHZ) {
  1715. /* Map 2GHz channel to 5GHz Atheros channel ID */
  1716. ret = ath5k_hw_rf5111_chan2athchan(
  1717. ieee80211_frequency_to_channel(channel->center_freq),
  1718. &ath5k_channel_2ghz);
  1719. if (ret)
  1720. return ret;
  1721. ath5k_channel = ath5k_channel_2ghz.a2_athchan;
  1722. data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
  1723. << 5) | (1 << 4);
  1724. }
  1725. if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
  1726. clock = 1;
  1727. data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
  1728. (clock << 1) | (1 << 10) | 1;
  1729. } else {
  1730. clock = 0;
  1731. data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
  1732. << 2) | (clock << 1) | (1 << 10) | 1;
  1733. }
  1734. ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
  1735. AR5K_RF_BUFFER);
  1736. ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
  1737. AR5K_RF_BUFFER_CONTROL_3);
  1738. return 0;
  1739. }
  1740. /*
  1741. * Set channel on 5112 and newer
  1742. */
  1743. static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
  1744. struct ieee80211_channel *channel)
  1745. {
  1746. u32 data, data0, data1, data2;
  1747. u16 c;
  1748. data = data0 = data1 = data2 = 0;
  1749. c = channel->center_freq;
  1750. /*
  1751. * Set the channel on the RF5112 or newer
  1752. */
  1753. if (c < 4800) {
  1754. if (!((c - 2224) % 5)) {
  1755. data0 = ((2 * (c - 704)) - 3040) / 10;
  1756. data1 = 1;
  1757. } else if (!((c - 2192) % 5)) {
  1758. data0 = ((2 * (c - 672)) - 3040) / 10;
  1759. data1 = 0;
  1760. } else
  1761. return -EINVAL;
  1762. data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
  1763. } else {
  1764. if (!(c % 20) && c >= 5120) {
  1765. data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
  1766. data2 = ath5k_hw_bitswap(3, 2);
  1767. } else if (!(c % 10)) {
  1768. data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
  1769. data2 = ath5k_hw_bitswap(2, 2);
  1770. } else if (!(c % 5)) {
  1771. data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
  1772. data2 = ath5k_hw_bitswap(1, 2);
  1773. } else
  1774. return -EINVAL;
  1775. }
  1776. data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
  1777. ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
  1778. ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
  1779. return 0;
  1780. }
  1781. /*
  1782. * Set a channel on the radio chip
  1783. */
  1784. int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
  1785. {
  1786. int ret;
  1787. /*
  1788. * Check bounds supported by the PHY (we don't care about regultory
  1789. * restrictions at this point). Note: hw_value already has the band
  1790. * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
  1791. * of the band by that */
  1792. if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
  1793. ATH5K_ERR(ah->ah_sc,
  1794. "channel frequency (%u MHz) out of supported "
  1795. "band range\n",
  1796. channel->center_freq);
  1797. return -EINVAL;
  1798. }
  1799. /*
  1800. * Set the channel and wait
  1801. */
  1802. switch (ah->ah_radio) {
  1803. case AR5K_RF5110:
  1804. ret = ath5k_hw_rf5110_channel(ah, channel);
  1805. break;
  1806. case AR5K_RF5111:
  1807. ret = ath5k_hw_rf5111_channel(ah, channel);
  1808. break;
  1809. default:
  1810. ret = ath5k_hw_rf5112_channel(ah, channel);
  1811. break;
  1812. }
  1813. if (ret)
  1814. return ret;
  1815. ah->ah_current_channel.center_freq = channel->center_freq;
  1816. ah->ah_current_channel.hw_value = channel->hw_value;
  1817. ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
  1818. return 0;
  1819. }
  1820. /*****************\
  1821. PHY calibration
  1822. \*****************/
  1823. /**
  1824. * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
  1825. *
  1826. * @ah: struct ath5k_hw pointer we are operating on
  1827. * @freq: the channel frequency, just used for error logging
  1828. *
  1829. * This function performs a noise floor calibration of the PHY and waits for
  1830. * it to complete. Then the noise floor value is compared to some maximum
  1831. * noise floor we consider valid.
  1832. *
  1833. * Note that this is different from what the madwifi HAL does: it reads the
  1834. * noise floor and afterwards initiates the calibration. Since the noise floor
  1835. * calibration can take some time to finish, depending on the current channel
  1836. * use, that avoids the occasional timeout warnings we are seeing now.
  1837. *
  1838. * See the following link for an Atheros patent on noise floor calibration:
  1839. * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
  1840. * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
  1841. *
  1842. */
  1843. int
  1844. ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
  1845. {
  1846. int ret;
  1847. unsigned int i;
  1848. s32 noise_floor;
  1849. /*
  1850. * Enable noise floor calibration and wait until completion
  1851. */
  1852. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1853. AR5K_PHY_AGCCTL_NF);
  1854. ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
  1855. AR5K_PHY_AGCCTL_NF, 0, false);
  1856. if (ret) {
  1857. ATH5K_ERR(ah->ah_sc,
  1858. "noise floor calibration timeout (%uMHz)\n", freq);
  1859. return ret;
  1860. }
  1861. /* Wait until the noise floor is calibrated and read the value */
  1862. for (i = 20; i > 0; i--) {
  1863. mdelay(1);
  1864. noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
  1865. noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
  1866. if (noise_floor & AR5K_PHY_NF_ACTIVE) {
  1867. noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
  1868. if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
  1869. break;
  1870. }
  1871. }
  1872. ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  1873. "noise floor %d\n", noise_floor);
  1874. if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
  1875. ATH5K_ERR(ah->ah_sc,
  1876. "noise floor calibration failed (%uMHz)\n", freq);
  1877. return -EIO;
  1878. }
  1879. ah->ah_noise_floor = noise_floor;
  1880. return 0;
  1881. }
  1882. /*
  1883. * Perform a PHY calibration on RF5110
  1884. * -Fix BPSK/QAM Constellation (I/Q correction)
  1885. * -Calculate Noise Floor
  1886. */
  1887. static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
  1888. struct ieee80211_channel *channel)
  1889. {
  1890. u32 phy_sig, phy_agc, phy_sat, beacon;
  1891. int ret;
  1892. /*
  1893. * Disable beacons and RX/TX queues, wait
  1894. */
  1895. AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
  1896. AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
  1897. beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
  1898. ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
  1899. udelay(2300);
  1900. /*
  1901. * Set the channel (with AGC turned off)
  1902. */
  1903. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1904. udelay(10);
  1905. ret = ath5k_hw_channel(ah, channel);
  1906. /*
  1907. * Activate PHY and wait
  1908. */
  1909. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
  1910. mdelay(1);
  1911. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1912. if (ret)
  1913. return ret;
  1914. /*
  1915. * Calibrate the radio chip
  1916. */
  1917. /* Remember normal state */
  1918. phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
  1919. phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
  1920. phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
  1921. /* Update radio registers */
  1922. ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
  1923. AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
  1924. ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
  1925. AR5K_PHY_AGCCOARSE_LO)) |
  1926. AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
  1927. AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
  1928. ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
  1929. AR5K_PHY_ADCSAT_THR)) |
  1930. AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
  1931. AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
  1932. udelay(20);
  1933. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1934. udelay(10);
  1935. ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
  1936. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1937. mdelay(1);
  1938. /*
  1939. * Enable calibration and wait until completion
  1940. */
  1941. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
  1942. ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
  1943. AR5K_PHY_AGCCTL_CAL, 0, false);
  1944. /* Reset to normal state */
  1945. ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
  1946. ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
  1947. ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
  1948. if (ret) {
  1949. ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
  1950. channel->center_freq);
  1951. return ret;
  1952. }
  1953. ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
  1954. if (ret)
  1955. return ret;
  1956. /*
  1957. * Re-enable RX/TX and beacons
  1958. */
  1959. AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
  1960. AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
  1961. ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
  1962. return 0;
  1963. }
  1964. /*
  1965. * Perform a PHY calibration on RF5111/5112
  1966. */
  1967. static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
  1968. struct ieee80211_channel *channel)
  1969. {
  1970. u32 i_pwr, q_pwr;
  1971. s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
  1972. ATH5K_TRACE(ah->ah_sc);
  1973. if (!ah->ah_calibration ||
  1974. ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
  1975. goto done;
  1976. ah->ah_calibration = false;
  1977. iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
  1978. i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
  1979. q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
  1980. i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
  1981. q_coffd = q_pwr >> 6;
  1982. if (i_coffd == 0 || q_coffd == 0)
  1983. goto done;
  1984. i_coff = ((-iq_corr) / i_coffd) & 0x3f;
  1985. q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
  1986. /* Commit new IQ value */
  1987. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
  1988. ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
  1989. done:
  1990. ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
  1991. /* Request RF gain */
  1992. if (channel->hw_value & CHANNEL_5GHZ) {
  1993. ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
  1994. AR5K_PHY_PAPD_PROBE_TXPOWER) |
  1995. AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
  1996. ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
  1997. }
  1998. return 0;
  1999. }
  2000. /*
  2001. * Perform a PHY calibration
  2002. */
  2003. int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
  2004. struct ieee80211_channel *channel)
  2005. {
  2006. int ret;
  2007. if (ah->ah_radio == AR5K_RF5110)
  2008. ret = ath5k_hw_rf5110_calibrate(ah, channel);
  2009. else
  2010. ret = ath5k_hw_rf511x_calibrate(ah, channel);
  2011. return ret;
  2012. }
  2013. int ath5k_hw_phy_disable(struct ath5k_hw *ah)
  2014. {
  2015. ATH5K_TRACE(ah->ah_sc);
  2016. /*Just a try M.F.*/
  2017. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
  2018. return 0;
  2019. }
  2020. /********************\
  2021. Misc PHY functions
  2022. \********************/
  2023. /*
  2024. * Get the PHY Chip revision
  2025. */
  2026. u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
  2027. {
  2028. unsigned int i;
  2029. u32 srev;
  2030. u16 ret;
  2031. ATH5K_TRACE(ah->ah_sc);
  2032. /*
  2033. * Set the radio chip access register
  2034. */
  2035. switch (chan) {
  2036. case CHANNEL_2GHZ:
  2037. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
  2038. break;
  2039. case CHANNEL_5GHZ:
  2040. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
  2041. break;
  2042. default:
  2043. return 0;
  2044. }
  2045. mdelay(2);
  2046. /* ...wait until PHY is ready and read the selected radio revision */
  2047. ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
  2048. for (i = 0; i < 8; i++)
  2049. ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
  2050. if (ah->ah_version == AR5K_AR5210) {
  2051. srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
  2052. ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
  2053. } else {
  2054. srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
  2055. ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
  2056. ((srev & 0x0f) << 4), 8);
  2057. }
  2058. /* Reset to the 5GHz mode */
  2059. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
  2060. return ret;
  2061. }
  2062. void /*TODO:Boundary check*/
  2063. ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
  2064. {
  2065. ATH5K_TRACE(ah->ah_sc);
  2066. /*Just a try M.F.*/
  2067. if (ah->ah_version != AR5K_AR5210)
  2068. ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
  2069. }
  2070. unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
  2071. {
  2072. ATH5K_TRACE(ah->ah_sc);
  2073. /*Just a try M.F.*/
  2074. if (ah->ah_version != AR5K_AR5210)
  2075. return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
  2076. return false; /*XXX: What do we return for 5210 ?*/
  2077. }
  2078. /*
  2079. * TX power setup
  2080. */
  2081. /*
  2082. * Initialize the tx power table (not fully implemented)
  2083. */
  2084. static void ath5k_txpower_table(struct ath5k_hw *ah,
  2085. struct ieee80211_channel *channel, s16 max_power)
  2086. {
  2087. unsigned int i, min, max, n;
  2088. u16 txpower, *rates;
  2089. rates = ah->ah_txpower.txp_rates;
  2090. txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
  2091. if (max_power > txpower)
  2092. txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
  2093. AR5K_TUNE_MAX_TXPOWER : max_power;
  2094. for (i = 0; i < AR5K_MAX_RATES; i++)
  2095. rates[i] = txpower;
  2096. /* XXX setup target powers by rate */
  2097. ah->ah_txpower.txp_min = rates[7];
  2098. ah->ah_txpower.txp_max = rates[0];
  2099. ah->ah_txpower.txp_ofdm = rates[0];
  2100. /* Calculate the power table */
  2101. n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
  2102. min = AR5K_EEPROM_PCDAC_START;
  2103. max = AR5K_EEPROM_PCDAC_STOP;
  2104. for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
  2105. ah->ah_txpower.txp_pcdac[i] =
  2106. #ifdef notyet
  2107. min + ((i * (max - min)) / n);
  2108. #else
  2109. min;
  2110. #endif
  2111. }
  2112. /*
  2113. * Set transmition power
  2114. */
  2115. int /*O.K. - txpower_table is unimplemented so this doesn't work*/
  2116. ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  2117. unsigned int txpower)
  2118. {
  2119. bool tpc = ah->ah_txpower.txp_tpc;
  2120. unsigned int i;
  2121. ATH5K_TRACE(ah->ah_sc);
  2122. if (txpower > AR5K_TUNE_MAX_TXPOWER) {
  2123. ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
  2124. return -EINVAL;
  2125. }
  2126. /*
  2127. * RF2413 for some reason can't
  2128. * transmit anything if we call
  2129. * this funtion, so we skip it
  2130. * until we fix txpower.
  2131. *
  2132. * XXX: Assume same for RF2425
  2133. * to be safe.
  2134. */
  2135. if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425))
  2136. return 0;
  2137. /* Reset TX power values */
  2138. memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
  2139. ah->ah_txpower.txp_tpc = tpc;
  2140. /* Initialize TX power table */
  2141. ath5k_txpower_table(ah, channel, txpower);
  2142. /*
  2143. * Write TX power values
  2144. */
  2145. for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
  2146. ath5k_hw_reg_write(ah,
  2147. ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
  2148. (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff),
  2149. AR5K_PHY_PCDAC_TXPOWER(i));
  2150. }
  2151. ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
  2152. AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
  2153. AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
  2154. ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
  2155. AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
  2156. AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
  2157. ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
  2158. AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
  2159. AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
  2160. ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
  2161. AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
  2162. AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
  2163. if (ah->ah_txpower.txp_tpc)
  2164. ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
  2165. AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
  2166. else
  2167. ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
  2168. AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
  2169. return 0;
  2170. }
  2171. int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
  2172. {
  2173. /*Just a try M.F.*/
  2174. struct ieee80211_channel *channel = &ah->ah_current_channel;
  2175. ATH5K_TRACE(ah->ah_sc);
  2176. ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
  2177. "changing txpower to %d\n", power);
  2178. return ath5k_hw_txpower(ah, channel, power);
  2179. }