s3c-i2s-v2.c 17 KB

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  1. /* sound/soc/s3c24xx/s3c-i2c-v2.c
  2. *
  3. * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
  4. *
  5. * Copyright (c) 2006 Wolfson Microelectronics PLC.
  6. * Graeme Gregory graeme.gregory@wolfsonmicro.com
  7. * linux@wolfsonmicro.com
  8. *
  9. * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
  10. * http://armlinux.simtec.co.uk/
  11. * Ben Dooks <ben@simtec.co.uk>
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/device.h>
  21. #include <linux/delay.h>
  22. #include <linux/clk.h>
  23. #include <linux/kernel.h>
  24. #include <linux/io.h>
  25. #include <sound/core.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/initval.h>
  29. #include <sound/soc.h>
  30. #include <plat/regs-s3c2412-iis.h>
  31. #include <plat/audio.h>
  32. #include <mach/dma.h>
  33. #include "s3c-i2s-v2.h"
  34. #undef S3C_IIS_V2_SUPPORTED
  35. #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
  36. #define S3C_IIS_V2_SUPPORTED
  37. #endif
  38. #ifdef CONFIG_PLAT_S3C64XX
  39. #define S3C_IIS_V2_SUPPORTED
  40. #endif
  41. #ifndef S3C_IIS_V2_SUPPORTED
  42. #error Unsupported CPU model
  43. #endif
  44. #define S3C2412_I2S_DEBUG_CON 0
  45. static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
  46. {
  47. return cpu_dai->private_data;
  48. }
  49. #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
  50. #if S3C2412_I2S_DEBUG_CON
  51. static void dbg_showcon(const char *fn, u32 con)
  52. {
  53. printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
  54. bit_set(con, S3C2412_IISCON_LRINDEX),
  55. bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
  56. bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
  57. bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
  58. bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
  59. printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
  60. fn,
  61. bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
  62. bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
  63. bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
  64. bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
  65. printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
  66. bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
  67. bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
  68. bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
  69. }
  70. #else
  71. static inline void dbg_showcon(const char *fn, u32 con)
  72. {
  73. }
  74. #endif
  75. /* Turn on or off the transmission path. */
  76. static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
  77. {
  78. void __iomem *regs = i2s->regs;
  79. u32 fic, con, mod;
  80. pr_debug("%s(%d)\n", __func__, on);
  81. fic = readl(regs + S3C2412_IISFIC);
  82. con = readl(regs + S3C2412_IISCON);
  83. mod = readl(regs + S3C2412_IISMOD);
  84. pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
  85. if (on) {
  86. con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
  87. con &= ~S3C2412_IISCON_TXDMA_PAUSE;
  88. con &= ~S3C2412_IISCON_TXCH_PAUSE;
  89. switch (mod & S3C2412_IISMOD_MODE_MASK) {
  90. case S3C2412_IISMOD_MODE_TXONLY:
  91. case S3C2412_IISMOD_MODE_TXRX:
  92. /* do nothing, we are in the right mode */
  93. break;
  94. case S3C2412_IISMOD_MODE_RXONLY:
  95. mod &= ~S3C2412_IISMOD_MODE_MASK;
  96. mod |= S3C2412_IISMOD_MODE_TXRX;
  97. break;
  98. default:
  99. dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
  100. mod & S3C2412_IISMOD_MODE_MASK);
  101. break;
  102. }
  103. writel(con, regs + S3C2412_IISCON);
  104. writel(mod, regs + S3C2412_IISMOD);
  105. } else {
  106. /* Note, we do not have any indication that the FIFO problems
  107. * tha the S3C2410/2440 had apply here, so we should be able
  108. * to disable the DMA and TX without resetting the FIFOS.
  109. */
  110. con |= S3C2412_IISCON_TXDMA_PAUSE;
  111. con |= S3C2412_IISCON_TXCH_PAUSE;
  112. con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
  113. switch (mod & S3C2412_IISMOD_MODE_MASK) {
  114. case S3C2412_IISMOD_MODE_TXRX:
  115. mod &= ~S3C2412_IISMOD_MODE_MASK;
  116. mod |= S3C2412_IISMOD_MODE_RXONLY;
  117. break;
  118. case S3C2412_IISMOD_MODE_TXONLY:
  119. mod &= ~S3C2412_IISMOD_MODE_MASK;
  120. con &= ~S3C2412_IISCON_IIS_ACTIVE;
  121. break;
  122. default:
  123. dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
  124. mod & S3C2412_IISMOD_MODE_MASK);
  125. break;
  126. }
  127. writel(mod, regs + S3C2412_IISMOD);
  128. writel(con, regs + S3C2412_IISCON);
  129. }
  130. fic = readl(regs + S3C2412_IISFIC);
  131. dbg_showcon(__func__, con);
  132. pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
  133. }
  134. static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
  135. {
  136. void __iomem *regs = i2s->regs;
  137. u32 fic, con, mod;
  138. pr_debug("%s(%d)\n", __func__, on);
  139. fic = readl(regs + S3C2412_IISFIC);
  140. con = readl(regs + S3C2412_IISCON);
  141. mod = readl(regs + S3C2412_IISMOD);
  142. pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
  143. if (on) {
  144. con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
  145. con &= ~S3C2412_IISCON_RXDMA_PAUSE;
  146. con &= ~S3C2412_IISCON_RXCH_PAUSE;
  147. switch (mod & S3C2412_IISMOD_MODE_MASK) {
  148. case S3C2412_IISMOD_MODE_TXRX:
  149. case S3C2412_IISMOD_MODE_RXONLY:
  150. /* do nothing, we are in the right mode */
  151. break;
  152. case S3C2412_IISMOD_MODE_TXONLY:
  153. mod &= ~S3C2412_IISMOD_MODE_MASK;
  154. mod |= S3C2412_IISMOD_MODE_TXRX;
  155. break;
  156. default:
  157. dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
  158. mod & S3C2412_IISMOD_MODE_MASK);
  159. }
  160. writel(mod, regs + S3C2412_IISMOD);
  161. writel(con, regs + S3C2412_IISCON);
  162. } else {
  163. /* See txctrl notes on FIFOs. */
  164. con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
  165. con |= S3C2412_IISCON_RXDMA_PAUSE;
  166. con |= S3C2412_IISCON_RXCH_PAUSE;
  167. switch (mod & S3C2412_IISMOD_MODE_MASK) {
  168. case S3C2412_IISMOD_MODE_RXONLY:
  169. con &= ~S3C2412_IISCON_IIS_ACTIVE;
  170. mod &= ~S3C2412_IISMOD_MODE_MASK;
  171. break;
  172. case S3C2412_IISMOD_MODE_TXRX:
  173. mod &= ~S3C2412_IISMOD_MODE_MASK;
  174. mod |= S3C2412_IISMOD_MODE_TXONLY;
  175. break;
  176. default:
  177. dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
  178. mod & S3C2412_IISMOD_MODE_MASK);
  179. }
  180. writel(con, regs + S3C2412_IISCON);
  181. writel(mod, regs + S3C2412_IISMOD);
  182. }
  183. fic = readl(regs + S3C2412_IISFIC);
  184. pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
  185. }
  186. /*
  187. * Wait for the LR signal to allow synchronisation to the L/R clock
  188. * from the codec. May only be needed for slave mode.
  189. */
  190. static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
  191. {
  192. u32 iiscon;
  193. unsigned long timeout = jiffies + msecs_to_jiffies(5);
  194. pr_debug("Entered %s\n", __func__);
  195. while (1) {
  196. iiscon = readl(i2s->regs + S3C2412_IISCON);
  197. if (iiscon & S3C2412_IISCON_LRINDEX)
  198. break;
  199. if (timeout < jiffies) {
  200. printk(KERN_ERR "%s: timeout\n", __func__);
  201. return -ETIMEDOUT;
  202. }
  203. }
  204. return 0;
  205. }
  206. /*
  207. * Set S3C2412 I2S DAI format
  208. */
  209. static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
  210. unsigned int fmt)
  211. {
  212. struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
  213. u32 iismod;
  214. pr_debug("Entered %s\n", __func__);
  215. iismod = readl(i2s->regs + S3C2412_IISMOD);
  216. pr_debug("hw_params r: IISMOD: %x \n", iismod);
  217. #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
  218. #define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
  219. #define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
  220. #define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
  221. #endif
  222. #if defined(CONFIG_PLAT_S3C64XX)
  223. /* From Rev1.1 datasheet, we have two master and two slave modes:
  224. * IMS[11:10]:
  225. * 00 = master mode, fed from PCLK
  226. * 01 = master mode, fed from CLKAUDIO
  227. * 10 = slave mode, using PCLK
  228. * 11 = slave mode, using I2SCLK
  229. */
  230. #define IISMOD_MASTER_MASK (1 << 11)
  231. #define IISMOD_SLAVE (1 << 11)
  232. #define IISMOD_MASTER (0 << 11)
  233. #endif
  234. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  235. case SND_SOC_DAIFMT_CBM_CFM:
  236. i2s->master = 0;
  237. iismod &= ~IISMOD_MASTER_MASK;
  238. iismod |= IISMOD_SLAVE;
  239. break;
  240. case SND_SOC_DAIFMT_CBS_CFS:
  241. i2s->master = 1;
  242. iismod &= ~IISMOD_MASTER_MASK;
  243. iismod |= IISMOD_MASTER;
  244. break;
  245. default:
  246. pr_err("unknwon master/slave format\n");
  247. return -EINVAL;
  248. }
  249. iismod &= ~S3C2412_IISMOD_SDF_MASK;
  250. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  251. case SND_SOC_DAIFMT_RIGHT_J:
  252. iismod |= S3C2412_IISMOD_SDF_MSB;
  253. break;
  254. case SND_SOC_DAIFMT_LEFT_J:
  255. iismod |= S3C2412_IISMOD_SDF_LSB;
  256. break;
  257. case SND_SOC_DAIFMT_I2S:
  258. iismod |= S3C2412_IISMOD_SDF_IIS;
  259. break;
  260. default:
  261. pr_err("Unknown data format\n");
  262. return -EINVAL;
  263. }
  264. writel(iismod, i2s->regs + S3C2412_IISMOD);
  265. pr_debug("hw_params w: IISMOD: %x \n", iismod);
  266. return 0;
  267. }
  268. static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
  269. struct snd_pcm_hw_params *params,
  270. struct snd_soc_dai *socdai)
  271. {
  272. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  273. struct snd_soc_dai_link *dai = rtd->dai;
  274. struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
  275. u32 iismod;
  276. pr_debug("Entered %s\n", __func__);
  277. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  278. dai->cpu_dai->dma_data = i2s->dma_playback;
  279. else
  280. dai->cpu_dai->dma_data = i2s->dma_capture;
  281. /* Working copies of register */
  282. iismod = readl(i2s->regs + S3C2412_IISMOD);
  283. pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
  284. #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
  285. switch (params_format(params)) {
  286. case SNDRV_PCM_FORMAT_S8:
  287. iismod |= S3C2412_IISMOD_8BIT;
  288. break;
  289. case SNDRV_PCM_FORMAT_S16_LE:
  290. iismod &= ~S3C2412_IISMOD_8BIT;
  291. break;
  292. }
  293. #endif
  294. #ifdef CONFIG_PLAT_S3C64XX
  295. iismod &= ~0x606;
  296. /* Sample size */
  297. switch (params_format(params)) {
  298. case SNDRV_PCM_FORMAT_S8:
  299. /* 8 bit sample, 16fs BCLK */
  300. iismod |= 0x2004;
  301. break;
  302. case SNDRV_PCM_FORMAT_S16_LE:
  303. /* 16 bit sample, 32fs BCLK */
  304. break;
  305. case SNDRV_PCM_FORMAT_S24_LE:
  306. /* 24 bit sample, 48fs BCLK */
  307. iismod |= 0x4002;
  308. break;
  309. }
  310. #endif
  311. writel(iismod, i2s->regs + S3C2412_IISMOD);
  312. pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
  313. return 0;
  314. }
  315. static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  316. struct snd_soc_dai *dai)
  317. {
  318. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  319. struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
  320. int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
  321. unsigned long irqs;
  322. int ret = 0;
  323. pr_debug("Entered %s\n", __func__);
  324. switch (cmd) {
  325. case SNDRV_PCM_TRIGGER_START:
  326. /* On start, ensure that the FIFOs are cleared and reset. */
  327. writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
  328. i2s->regs + S3C2412_IISFIC);
  329. /* clear again, just in case */
  330. writel(0x0, i2s->regs + S3C2412_IISFIC);
  331. case SNDRV_PCM_TRIGGER_RESUME:
  332. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  333. if (!i2s->master) {
  334. ret = s3c2412_snd_lrsync(i2s);
  335. if (ret)
  336. goto exit_err;
  337. }
  338. local_irq_save(irqs);
  339. if (capture)
  340. s3c2412_snd_rxctrl(i2s, 1);
  341. else
  342. s3c2412_snd_txctrl(i2s, 1);
  343. local_irq_restore(irqs);
  344. break;
  345. case SNDRV_PCM_TRIGGER_STOP:
  346. case SNDRV_PCM_TRIGGER_SUSPEND:
  347. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  348. local_irq_save(irqs);
  349. if (capture)
  350. s3c2412_snd_rxctrl(i2s, 0);
  351. else
  352. s3c2412_snd_txctrl(i2s, 0);
  353. local_irq_restore(irqs);
  354. break;
  355. default:
  356. ret = -EINVAL;
  357. break;
  358. }
  359. exit_err:
  360. return ret;
  361. }
  362. /*
  363. * Set S3C2412 Clock dividers
  364. */
  365. static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
  366. int div_id, int div)
  367. {
  368. struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
  369. u32 reg;
  370. pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
  371. switch (div_id) {
  372. case S3C_I2SV2_DIV_BCLK:
  373. reg = readl(i2s->regs + S3C2412_IISMOD);
  374. reg &= ~S3C2412_IISMOD_BCLK_MASK;
  375. writel(reg | div, i2s->regs + S3C2412_IISMOD);
  376. pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
  377. break;
  378. case S3C_I2SV2_DIV_RCLK:
  379. if (div > 3) {
  380. /* convert value to bit field */
  381. switch (div) {
  382. case 256:
  383. div = S3C2412_IISMOD_RCLK_256FS;
  384. break;
  385. case 384:
  386. div = S3C2412_IISMOD_RCLK_384FS;
  387. break;
  388. case 512:
  389. div = S3C2412_IISMOD_RCLK_512FS;
  390. break;
  391. case 768:
  392. div = S3C2412_IISMOD_RCLK_768FS;
  393. break;
  394. default:
  395. return -EINVAL;
  396. }
  397. }
  398. reg = readl(i2s->regs + S3C2412_IISMOD);
  399. reg &= ~S3C2412_IISMOD_RCLK_MASK;
  400. writel(reg | div, i2s->regs + S3C2412_IISMOD);
  401. pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
  402. break;
  403. case S3C_I2SV2_DIV_PRESCALER:
  404. if (div >= 0) {
  405. writel((div << 8) | S3C2412_IISPSR_PSREN,
  406. i2s->regs + S3C2412_IISPSR);
  407. } else {
  408. writel(0x0, i2s->regs + S3C2412_IISPSR);
  409. }
  410. pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
  411. break;
  412. default:
  413. return -EINVAL;
  414. }
  415. return 0;
  416. }
  417. /* default table of all avaialable root fs divisors */
  418. static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
  419. int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
  420. unsigned int *fstab,
  421. unsigned int rate, struct clk *clk)
  422. {
  423. unsigned long clkrate = clk_get_rate(clk);
  424. unsigned int div;
  425. unsigned int fsclk;
  426. unsigned int actual;
  427. unsigned int fs;
  428. unsigned int fsdiv;
  429. signed int deviation = 0;
  430. unsigned int best_fs = 0;
  431. unsigned int best_div = 0;
  432. unsigned int best_rate = 0;
  433. unsigned int best_deviation = INT_MAX;
  434. pr_debug("Input clock rate %ldHz\n", clkrate);
  435. if (fstab == NULL)
  436. fstab = iis_fs_tab;
  437. for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
  438. fsdiv = iis_fs_tab[fs];
  439. fsclk = clkrate / fsdiv;
  440. div = fsclk / rate;
  441. if ((fsclk % rate) > (rate / 2))
  442. div++;
  443. if (div <= 1)
  444. continue;
  445. actual = clkrate / (fsdiv * div);
  446. deviation = actual - rate;
  447. printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
  448. fsdiv, div, actual, deviation);
  449. deviation = abs(deviation);
  450. if (deviation < best_deviation) {
  451. best_fs = fsdiv;
  452. best_div = div;
  453. best_rate = actual;
  454. best_deviation = deviation;
  455. }
  456. if (deviation == 0)
  457. break;
  458. }
  459. printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
  460. best_fs, best_div, best_rate);
  461. info->fs_div = best_fs;
  462. info->clk_div = best_div;
  463. return 0;
  464. }
  465. EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
  466. int s3c_i2sv2_probe(struct platform_device *pdev,
  467. struct snd_soc_dai *dai,
  468. struct s3c_i2sv2_info *i2s,
  469. unsigned long base)
  470. {
  471. struct device *dev = &pdev->dev;
  472. unsigned int iismod;
  473. i2s->dev = dev;
  474. /* record our i2s structure for later use in the callbacks */
  475. dai->private_data = i2s;
  476. if (!base) {
  477. struct resource *res = platform_get_resource(pdev,
  478. IORESOURCE_MEM,
  479. 0);
  480. if (!res) {
  481. dev_err(dev, "Unable to get register resource\n");
  482. return -ENXIO;
  483. }
  484. if (!request_mem_region(res->start, resource_size(res),
  485. "s3c64xx-i2s-v4")) {
  486. dev_err(dev, "Unable to request register region\n");
  487. return -EBUSY;
  488. }
  489. base = res->start;
  490. }
  491. i2s->regs = ioremap(base, 0x100);
  492. if (i2s->regs == NULL) {
  493. dev_err(dev, "cannot ioremap registers\n");
  494. return -ENXIO;
  495. }
  496. i2s->iis_pclk = clk_get(dev, "iis");
  497. if (i2s->iis_pclk == NULL) {
  498. dev_err(dev, "failed to get iis_clock\n");
  499. iounmap(i2s->regs);
  500. return -ENOENT;
  501. }
  502. clk_enable(i2s->iis_pclk);
  503. /* Mark ourselves as in TXRX mode so we can run through our cleanup
  504. * process without warnings. */
  505. iismod = readl(i2s->regs + S3C2412_IISMOD);
  506. iismod |= S3C2412_IISMOD_MODE_TXRX;
  507. writel(iismod, i2s->regs + S3C2412_IISMOD);
  508. s3c2412_snd_txctrl(i2s, 0);
  509. s3c2412_snd_rxctrl(i2s, 0);
  510. return 0;
  511. }
  512. EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
  513. #ifdef CONFIG_PM
  514. static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
  515. {
  516. struct s3c_i2sv2_info *i2s = to_info(dai);
  517. u32 iismod;
  518. if (dai->active) {
  519. i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
  520. i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
  521. i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
  522. /* some basic suspend checks */
  523. iismod = readl(i2s->regs + S3C2412_IISMOD);
  524. if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
  525. pr_warning("%s: RXDMA active?\n", __func__);
  526. if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
  527. pr_warning("%s: TXDMA active?\n", __func__);
  528. if (iismod & S3C2412_IISCON_IIS_ACTIVE)
  529. pr_warning("%s: IIS active\n", __func__);
  530. }
  531. return 0;
  532. }
  533. static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
  534. {
  535. struct s3c_i2sv2_info *i2s = to_info(dai);
  536. pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
  537. dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
  538. if (dai->active) {
  539. writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
  540. writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
  541. writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
  542. writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
  543. i2s->regs + S3C2412_IISFIC);
  544. ndelay(250);
  545. writel(0x0, i2s->regs + S3C2412_IISFIC);
  546. }
  547. return 0;
  548. }
  549. #else
  550. #define s3c2412_i2s_suspend NULL
  551. #define s3c2412_i2s_resume NULL
  552. #endif
  553. int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
  554. {
  555. struct snd_soc_dai_ops *ops = dai->ops;
  556. ops->trigger = s3c2412_i2s_trigger;
  557. ops->hw_params = s3c2412_i2s_hw_params;
  558. ops->set_fmt = s3c2412_i2s_set_fmt;
  559. ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
  560. dai->suspend = s3c2412_i2s_suspend;
  561. dai->resume = s3c2412_i2s_resume;
  562. return snd_soc_register_dai(dai);
  563. }
  564. EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
  565. MODULE_LICENSE("GPL");