tusb6010.c 31 KB

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  1. /*
  2. * TUSB6010 USB 2.0 OTG Dual Role controller
  3. *
  4. * Copyright (C) 2006 Nokia Corporation
  5. * Tony Lindgren <tony@atomide.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Notes:
  12. * - Driver assumes that interface to external host (main CPU) is
  13. * configured for NOR FLASH interface instead of VLYNQ serial
  14. * interface.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/errno.h>
  19. #include <linux/init.h>
  20. #include <linux/usb.h>
  21. #include <linux/irq.h>
  22. #include <linux/platform_device.h>
  23. #include "musb_core.h"
  24. static void tusb_source_power(struct musb *musb, int is_on);
  25. #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
  26. #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
  27. /*
  28. * Checks the revision. We need to use the DMA register as 3.0 does not
  29. * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
  30. */
  31. u8 tusb_get_revision(struct musb *musb)
  32. {
  33. void __iomem *tbase = musb->ctrl_base;
  34. u32 die_id;
  35. u8 rev;
  36. rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
  37. if (TUSB_REV_MAJOR(rev) == 3) {
  38. die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
  39. TUSB_DIDR1_HI));
  40. if (die_id >= TUSB_DIDR1_HI_REV_31)
  41. rev |= 1;
  42. }
  43. return rev;
  44. }
  45. static int __init tusb_print_revision(struct musb *musb)
  46. {
  47. void __iomem *tbase = musb->ctrl_base;
  48. u8 rev;
  49. rev = tusb_get_revision(musb);
  50. pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
  51. "prcm",
  52. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
  53. TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
  54. "int",
  55. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  56. TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  57. "gpio",
  58. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
  59. TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
  60. "dma",
  61. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  62. TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  63. "dieid",
  64. TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
  65. "rev",
  66. TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
  67. return tusb_get_revision(musb);
  68. }
  69. #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
  70. | TUSB_PHY_OTG_CTRL_TESTM0)
  71. /*
  72. * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
  73. * Disables power detection in PHY for the duration of idle.
  74. */
  75. static void tusb_wbus_quirk(struct musb *musb, int enabled)
  76. {
  77. void __iomem *tbase = musb->ctrl_base;
  78. static u32 phy_otg_ctrl, phy_otg_ena;
  79. u32 tmp;
  80. if (enabled) {
  81. phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  82. phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  83. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
  84. | phy_otg_ena | WBUS_QUIRK_MASK;
  85. musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
  86. tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
  87. tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
  88. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
  89. DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
  90. musb_readl(tbase, TUSB_PHY_OTG_CTRL),
  91. musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
  92. } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
  93. & TUSB_PHY_OTG_CTRL_TESTM2) {
  94. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
  95. musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
  96. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
  97. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
  98. DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
  99. musb_readl(tbase, TUSB_PHY_OTG_CTRL),
  100. musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
  101. phy_otg_ctrl = 0;
  102. phy_otg_ena = 0;
  103. }
  104. }
  105. /*
  106. * TUSB 6010 may use a parallel bus that doesn't support byte ops;
  107. * so both loading and unloading FIFOs need explicit byte counts.
  108. */
  109. static inline void
  110. tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
  111. {
  112. u32 val;
  113. int i;
  114. if (len > 4) {
  115. for (i = 0; i < (len >> 2); i++) {
  116. memcpy(&val, buf, 4);
  117. musb_writel(fifo, 0, val);
  118. buf += 4;
  119. }
  120. len %= 4;
  121. }
  122. if (len > 0) {
  123. /* Write the rest 1 - 3 bytes to FIFO */
  124. memcpy(&val, buf, len);
  125. musb_writel(fifo, 0, val);
  126. }
  127. }
  128. static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
  129. void __iomem *buf, u16 len)
  130. {
  131. u32 val;
  132. int i;
  133. if (len > 4) {
  134. for (i = 0; i < (len >> 2); i++) {
  135. val = musb_readl(fifo, 0);
  136. memcpy(buf, &val, 4);
  137. buf += 4;
  138. }
  139. len %= 4;
  140. }
  141. if (len > 0) {
  142. /* Read the rest 1 - 3 bytes from FIFO */
  143. val = musb_readl(fifo, 0);
  144. memcpy(buf, &val, len);
  145. }
  146. }
  147. void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
  148. {
  149. void __iomem *ep_conf = hw_ep->conf;
  150. void __iomem *fifo = hw_ep->fifo;
  151. u8 epnum = hw_ep->epnum;
  152. prefetch(buf);
  153. DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
  154. 'T', epnum, fifo, len, buf);
  155. if (epnum)
  156. musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
  157. TUSB_EP_CONFIG_XFR_SIZE(len));
  158. else
  159. musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
  160. TUSB_EP0_CONFIG_XFR_SIZE(len));
  161. if (likely((0x01 & (unsigned long) buf) == 0)) {
  162. /* Best case is 32bit-aligned destination address */
  163. if ((0x02 & (unsigned long) buf) == 0) {
  164. if (len >= 4) {
  165. writesl(fifo, buf, len >> 2);
  166. buf += (len & ~0x03);
  167. len &= 0x03;
  168. }
  169. } else {
  170. if (len >= 2) {
  171. u32 val;
  172. int i;
  173. /* Cannot use writesw, fifo is 32-bit */
  174. for (i = 0; i < (len >> 2); i++) {
  175. val = (u32)(*(u16 *)buf);
  176. buf += 2;
  177. val |= (*(u16 *)buf) << 16;
  178. buf += 2;
  179. musb_writel(fifo, 0, val);
  180. }
  181. len &= 0x03;
  182. }
  183. }
  184. }
  185. if (len > 0)
  186. tusb_fifo_write_unaligned(fifo, buf, len);
  187. }
  188. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
  189. {
  190. void __iomem *ep_conf = hw_ep->conf;
  191. void __iomem *fifo = hw_ep->fifo;
  192. u8 epnum = hw_ep->epnum;
  193. DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
  194. 'R', epnum, fifo, len, buf);
  195. if (epnum)
  196. musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
  197. TUSB_EP_CONFIG_XFR_SIZE(len));
  198. else
  199. musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
  200. if (likely((0x01 & (unsigned long) buf) == 0)) {
  201. /* Best case is 32bit-aligned destination address */
  202. if ((0x02 & (unsigned long) buf) == 0) {
  203. if (len >= 4) {
  204. readsl(fifo, buf, len >> 2);
  205. buf += (len & ~0x03);
  206. len &= 0x03;
  207. }
  208. } else {
  209. if (len >= 2) {
  210. u32 val;
  211. int i;
  212. /* Cannot use readsw, fifo is 32-bit */
  213. for (i = 0; i < (len >> 2); i++) {
  214. val = musb_readl(fifo, 0);
  215. *(u16 *)buf = (u16)(val & 0xffff);
  216. buf += 2;
  217. *(u16 *)buf = (u16)(val >> 16);
  218. buf += 2;
  219. }
  220. len &= 0x03;
  221. }
  222. }
  223. }
  224. if (len > 0)
  225. tusb_fifo_read_unaligned(fifo, buf, len);
  226. }
  227. #ifdef CONFIG_USB_GADGET_MUSB_HDRC
  228. /* This is used by gadget drivers, and OTG transceiver logic, allowing
  229. * at most mA current to be drawn from VBUS during a Default-B session
  230. * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
  231. * mode), or low power Default-B sessions, something else supplies power.
  232. * Caller must take care of locking.
  233. */
  234. static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
  235. {
  236. struct musb *musb = container_of(x, struct musb, xceiv);
  237. void __iomem *tbase = musb->ctrl_base;
  238. u32 reg;
  239. /*
  240. * Keep clock active when enabled. Note that this is not tied to
  241. * drawing VBUS, as with OTG mA can be less than musb->min_power.
  242. */
  243. if (musb->set_clock) {
  244. if (mA)
  245. musb->set_clock(musb->clock, 1);
  246. else
  247. musb->set_clock(musb->clock, 0);
  248. }
  249. /* tps65030 seems to consume max 100mA, with maybe 60mA available
  250. * (measured on one board) for things other than tps and tusb.
  251. *
  252. * Boards sharing the CPU clock with CLKIN will need to prevent
  253. * certain idle sleep states while the USB link is active.
  254. *
  255. * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
  256. * The actual current usage would be very board-specific. For now,
  257. * it's simpler to just use an aggregate (also board-specific).
  258. */
  259. if (x->default_a || mA < (musb->min_power << 1))
  260. mA = 0;
  261. reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
  262. if (mA) {
  263. musb->is_bus_powered = 1;
  264. reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
  265. } else {
  266. musb->is_bus_powered = 0;
  267. reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
  268. }
  269. musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
  270. DBG(2, "draw max %d mA VBUS\n", mA);
  271. return 0;
  272. }
  273. #else
  274. #define tusb_draw_power NULL
  275. #endif
  276. /* workaround for issue 13: change clock during chip idle
  277. * (to be fixed in rev3 silicon) ... symptoms include disconnect
  278. * or looping suspend/resume cycles
  279. */
  280. static void tusb_set_clock_source(struct musb *musb, unsigned mode)
  281. {
  282. void __iomem *tbase = musb->ctrl_base;
  283. u32 reg;
  284. reg = musb_readl(tbase, TUSB_PRCM_CONF);
  285. reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
  286. /* 0 = refclk (clkin, XI)
  287. * 1 = PHY 60 MHz (internal PLL)
  288. * 2 = not supported
  289. * 3 = what?
  290. */
  291. if (mode > 0)
  292. reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
  293. musb_writel(tbase, TUSB_PRCM_CONF, reg);
  294. /* FIXME tusb6010_platform_retime(mode == 0); */
  295. }
  296. /*
  297. * Idle TUSB6010 until next wake-up event; NOR access always wakes.
  298. * Other code ensures that we idle unless we're connected _and_ the
  299. * USB link is not suspended ... and tells us the relevant wakeup
  300. * events. SW_EN for voltage is handled separately.
  301. */
  302. void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
  303. {
  304. void __iomem *tbase = musb->ctrl_base;
  305. u32 reg;
  306. if ((wakeup_enables & TUSB_PRCM_WBUS)
  307. && (tusb_get_revision(musb) == TUSB_REV_30))
  308. tusb_wbus_quirk(musb, 1);
  309. tusb_set_clock_source(musb, 0);
  310. wakeup_enables |= TUSB_PRCM_WNORCS;
  311. musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
  312. /* REVISIT writeup of WID implies that if WID set and ID is grounded,
  313. * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
  314. * Presumably that's mostly to save power, hence WID is immaterial ...
  315. */
  316. reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
  317. /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
  318. if (is_host_active(musb)) {
  319. reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  320. reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
  321. } else {
  322. reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
  323. reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  324. }
  325. reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
  326. musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
  327. DBG(6, "idle, wake on %02x\n", wakeup_enables);
  328. }
  329. /*
  330. * Updates cable VBUS status. Caller must take care of locking.
  331. */
  332. int musb_platform_get_vbus_status(struct musb *musb)
  333. {
  334. void __iomem *tbase = musb->ctrl_base;
  335. u32 otg_stat, prcm_mngmt;
  336. int ret = 0;
  337. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  338. prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
  339. /* Temporarily enable VBUS detection if it was disabled for
  340. * suspend mode. Unless it's enabled otg_stat and devctl will
  341. * not show correct VBUS state.
  342. */
  343. if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
  344. u32 tmp = prcm_mngmt;
  345. tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  346. musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
  347. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  348. musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
  349. }
  350. if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
  351. ret = 1;
  352. return ret;
  353. }
  354. static struct timer_list musb_idle_timer;
  355. static void musb_do_idle(unsigned long _musb)
  356. {
  357. struct musb *musb = (void *)_musb;
  358. unsigned long flags;
  359. spin_lock_irqsave(&musb->lock, flags);
  360. switch (musb->xceiv.state) {
  361. case OTG_STATE_A_WAIT_BCON:
  362. if ((musb->a_wait_bcon != 0)
  363. && (musb->idle_timeout == 0
  364. || time_after(jiffies, musb->idle_timeout))) {
  365. DBG(4, "Nothing connected %s, turning off VBUS\n",
  366. otg_state_string(musb));
  367. }
  368. /* FALLTHROUGH */
  369. case OTG_STATE_A_IDLE:
  370. tusb_source_power(musb, 0);
  371. default:
  372. break;
  373. }
  374. if (!musb->is_active) {
  375. u32 wakeups;
  376. /* wait until khubd handles port change status */
  377. if (is_host_active(musb) && (musb->port1_status >> 16))
  378. goto done;
  379. #ifdef CONFIG_USB_GADGET_MUSB_HDRC
  380. if (is_peripheral_enabled(musb) && !musb->gadget_driver)
  381. wakeups = 0;
  382. else {
  383. wakeups = TUSB_PRCM_WHOSTDISCON
  384. | TUSB_PRCM_WBUS
  385. | TUSB_PRCM_WVBUS;
  386. if (is_otg_enabled(musb))
  387. wakeups |= TUSB_PRCM_WID;
  388. }
  389. #else
  390. wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
  391. #endif
  392. tusb_allow_idle(musb, wakeups);
  393. }
  394. done:
  395. spin_unlock_irqrestore(&musb->lock, flags);
  396. }
  397. /*
  398. * Maybe put TUSB6010 into idle mode mode depending on USB link status,
  399. * like "disconnected" or "suspended". We'll be woken out of it by
  400. * connect, resume, or disconnect.
  401. *
  402. * Needs to be called as the last function everywhere where there is
  403. * register access to TUSB6010 because of NOR flash wake-up.
  404. * Caller should own controller spinlock.
  405. *
  406. * Delay because peripheral enables D+ pullup 3msec after SE0, and
  407. * we don't want to treat that full speed J as a wakeup event.
  408. * ... peripherals must draw only suspend current after 10 msec.
  409. */
  410. void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
  411. {
  412. unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
  413. static unsigned long last_timer;
  414. if (timeout == 0)
  415. timeout = default_timeout;
  416. /* Never idle if active, or when VBUS timeout is not set as host */
  417. if (musb->is_active || ((musb->a_wait_bcon == 0)
  418. && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
  419. DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
  420. del_timer(&musb_idle_timer);
  421. last_timer = jiffies;
  422. return;
  423. }
  424. if (time_after(last_timer, timeout)) {
  425. if (!timer_pending(&musb_idle_timer))
  426. last_timer = timeout;
  427. else {
  428. DBG(4, "Longer idle timer already pending, ignoring\n");
  429. return;
  430. }
  431. }
  432. last_timer = timeout;
  433. DBG(4, "%s inactive, for idle timer for %lu ms\n",
  434. otg_state_string(musb),
  435. (unsigned long)jiffies_to_msecs(timeout - jiffies));
  436. mod_timer(&musb_idle_timer, timeout);
  437. }
  438. /* ticks of 60 MHz clock */
  439. #define DEVCLOCK 60000000
  440. #define OTG_TIMER_MS(msecs) ((msecs) \
  441. ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
  442. | TUSB_DEV_OTG_TIMER_ENABLE) \
  443. : 0)
  444. static void tusb_source_power(struct musb *musb, int is_on)
  445. {
  446. void __iomem *tbase = musb->ctrl_base;
  447. u32 conf, prcm, timer;
  448. u8 devctl;
  449. /* HDRC controls CPEN, but beware current surges during device
  450. * connect. They can trigger transient overcurrent conditions
  451. * that must be ignored.
  452. */
  453. prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
  454. conf = musb_readl(tbase, TUSB_DEV_CONF);
  455. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  456. if (is_on) {
  457. if (musb->set_clock)
  458. musb->set_clock(musb->clock, 1);
  459. timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
  460. musb->xceiv.default_a = 1;
  461. musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
  462. devctl |= MUSB_DEVCTL_SESSION;
  463. conf |= TUSB_DEV_CONF_USB_HOST_MODE;
  464. MUSB_HST_MODE(musb);
  465. } else {
  466. u32 otg_stat;
  467. timer = 0;
  468. /* If ID pin is grounded, we want to be a_idle */
  469. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  470. if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
  471. switch (musb->xceiv.state) {
  472. case OTG_STATE_A_WAIT_VRISE:
  473. case OTG_STATE_A_WAIT_BCON:
  474. musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
  475. break;
  476. case OTG_STATE_A_WAIT_VFALL:
  477. musb->xceiv.state = OTG_STATE_A_IDLE;
  478. break;
  479. default:
  480. musb->xceiv.state = OTG_STATE_A_IDLE;
  481. }
  482. musb->is_active = 0;
  483. musb->xceiv.default_a = 1;
  484. MUSB_HST_MODE(musb);
  485. } else {
  486. musb->is_active = 0;
  487. musb->xceiv.default_a = 0;
  488. musb->xceiv.state = OTG_STATE_B_IDLE;
  489. MUSB_DEV_MODE(musb);
  490. }
  491. devctl &= ~MUSB_DEVCTL_SESSION;
  492. conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
  493. if (musb->set_clock)
  494. musb->set_clock(musb->clock, 0);
  495. }
  496. prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
  497. musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
  498. musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
  499. musb_writel(tbase, TUSB_DEV_CONF, conf);
  500. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  501. DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
  502. otg_state_string(musb),
  503. musb_readb(musb->mregs, MUSB_DEVCTL),
  504. musb_readl(tbase, TUSB_DEV_OTG_STAT),
  505. conf, prcm);
  506. }
  507. /*
  508. * Sets the mode to OTG, peripheral or host by changing the ID detection.
  509. * Caller must take care of locking.
  510. *
  511. * Note that if a mini-A cable is plugged in the ID line will stay down as
  512. * the weak ID pull-up is not able to pull the ID up.
  513. *
  514. * REVISIT: It would be possible to add support for changing between host
  515. * and peripheral modes in non-OTG configurations by reconfiguring hardware
  516. * and then setting musb->board_mode. For now, only support OTG mode.
  517. */
  518. int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
  519. {
  520. void __iomem *tbase = musb->ctrl_base;
  521. u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
  522. if (musb->board_mode != MUSB_OTG) {
  523. ERR("Changing mode currently only supported in OTG mode\n");
  524. return -EINVAL;
  525. }
  526. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  527. phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  528. phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  529. dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
  530. switch (musb_mode) {
  531. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  532. case MUSB_HOST: /* Disable PHY ID detect, ground ID */
  533. phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  534. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  535. dev_conf |= TUSB_DEV_CONF_ID_SEL;
  536. dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
  537. break;
  538. #endif
  539. #ifdef CONFIG_USB_GADGET_MUSB_HDRC
  540. case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
  541. phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  542. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  543. dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
  544. break;
  545. #endif
  546. #ifdef CONFIG_USB_MUSB_OTG
  547. case MUSB_OTG: /* Use PHY ID detection */
  548. phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  549. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  550. dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
  551. break;
  552. #endif
  553. default:
  554. DBG(2, "Trying to set mode %i\n", musb_mode);
  555. return -EINVAL;
  556. }
  557. musb_writel(tbase, TUSB_PHY_OTG_CTRL,
  558. TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
  559. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
  560. TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
  561. musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
  562. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  563. if ((musb_mode == MUSB_PERIPHERAL) &&
  564. !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
  565. INFO("Cannot be peripheral with mini-A cable "
  566. "otg_stat: %08x\n", otg_stat);
  567. return 0;
  568. }
  569. static inline unsigned long
  570. tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
  571. {
  572. u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  573. unsigned long idle_timeout = 0;
  574. /* ID pin */
  575. if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
  576. int default_a;
  577. if (is_otg_enabled(musb))
  578. default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
  579. else
  580. default_a = is_host_enabled(musb);
  581. DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
  582. musb->xceiv.default_a = default_a;
  583. tusb_source_power(musb, default_a);
  584. /* Don't allow idling immediately */
  585. if (default_a)
  586. idle_timeout = jiffies + (HZ * 3);
  587. }
  588. /* VBUS state change */
  589. if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
  590. /* B-dev state machine: no vbus ~= disconnect */
  591. if ((is_otg_enabled(musb) && !musb->xceiv.default_a)
  592. || !is_host_enabled(musb)) {
  593. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  594. /* ? musb_root_disconnect(musb); */
  595. musb->port1_status &=
  596. ~(USB_PORT_STAT_CONNECTION
  597. | USB_PORT_STAT_ENABLE
  598. | USB_PORT_STAT_LOW_SPEED
  599. | USB_PORT_STAT_HIGH_SPEED
  600. | USB_PORT_STAT_TEST
  601. );
  602. #endif
  603. if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
  604. DBG(1, "Forcing disconnect (no interrupt)\n");
  605. if (musb->xceiv.state != OTG_STATE_B_IDLE) {
  606. /* INTR_DISCONNECT can hide... */
  607. musb->xceiv.state = OTG_STATE_B_IDLE;
  608. musb->int_usb |= MUSB_INTR_DISCONNECT;
  609. }
  610. musb->is_active = 0;
  611. }
  612. DBG(2, "vbus change, %s, otg %03x\n",
  613. otg_state_string(musb), otg_stat);
  614. idle_timeout = jiffies + (1 * HZ);
  615. schedule_work(&musb->irq_work);
  616. } else /* A-dev state machine */ {
  617. DBG(2, "vbus change, %s, otg %03x\n",
  618. otg_state_string(musb), otg_stat);
  619. switch (musb->xceiv.state) {
  620. case OTG_STATE_A_IDLE:
  621. DBG(2, "Got SRP, turning on VBUS\n");
  622. musb_set_vbus(musb, 1);
  623. /* CONNECT can wake if a_wait_bcon is set */
  624. if (musb->a_wait_bcon != 0)
  625. musb->is_active = 0;
  626. else
  627. musb->is_active = 1;
  628. /*
  629. * OPT FS A TD.4.6 needs few seconds for
  630. * A_WAIT_VRISE
  631. */
  632. idle_timeout = jiffies + (2 * HZ);
  633. break;
  634. case OTG_STATE_A_WAIT_VRISE:
  635. /* ignore; A-session-valid < VBUS_VALID/2,
  636. * we monitor this with the timer
  637. */
  638. break;
  639. case OTG_STATE_A_WAIT_VFALL:
  640. /* REVISIT this irq triggers during short
  641. * spikes caused by enumeration ...
  642. */
  643. if (musb->vbuserr_retry) {
  644. musb->vbuserr_retry--;
  645. tusb_source_power(musb, 1);
  646. } else {
  647. musb->vbuserr_retry
  648. = VBUSERR_RETRY_COUNT;
  649. tusb_source_power(musb, 0);
  650. }
  651. break;
  652. default:
  653. break;
  654. }
  655. }
  656. }
  657. /* OTG timer expiration */
  658. if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
  659. u8 devctl;
  660. DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
  661. switch (musb->xceiv.state) {
  662. case OTG_STATE_A_WAIT_VRISE:
  663. /* VBUS has probably been valid for a while now,
  664. * but may well have bounced out of range a bit
  665. */
  666. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  667. if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
  668. if ((devctl & MUSB_DEVCTL_VBUS)
  669. != MUSB_DEVCTL_VBUS) {
  670. DBG(2, "devctl %02x\n", devctl);
  671. break;
  672. }
  673. musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
  674. musb->is_active = 0;
  675. idle_timeout = jiffies
  676. + msecs_to_jiffies(musb->a_wait_bcon);
  677. } else {
  678. /* REVISIT report overcurrent to hub? */
  679. ERR("vbus too slow, devctl %02x\n", devctl);
  680. tusb_source_power(musb, 0);
  681. }
  682. break;
  683. case OTG_STATE_A_WAIT_BCON:
  684. if (musb->a_wait_bcon != 0)
  685. idle_timeout = jiffies
  686. + msecs_to_jiffies(musb->a_wait_bcon);
  687. break;
  688. case OTG_STATE_A_SUSPEND:
  689. break;
  690. case OTG_STATE_B_WAIT_ACON:
  691. break;
  692. default:
  693. break;
  694. }
  695. }
  696. schedule_work(&musb->irq_work);
  697. return idle_timeout;
  698. }
  699. static irqreturn_t tusb_interrupt(int irq, void *__hci)
  700. {
  701. struct musb *musb = __hci;
  702. void __iomem *tbase = musb->ctrl_base;
  703. unsigned long flags, idle_timeout = 0;
  704. u32 int_mask, int_src;
  705. spin_lock_irqsave(&musb->lock, flags);
  706. /* Mask all interrupts to allow using both edge and level GPIO irq */
  707. int_mask = musb_readl(tbase, TUSB_INT_MASK);
  708. musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
  709. int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
  710. DBG(3, "TUSB IRQ %08x\n", int_src);
  711. musb->int_usb = (u8) int_src;
  712. /* Acknowledge wake-up source interrupts */
  713. if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
  714. u32 reg;
  715. u32 i;
  716. if (tusb_get_revision(musb) == TUSB_REV_30)
  717. tusb_wbus_quirk(musb, 0);
  718. /* there are issues re-locking the PLL on wakeup ... */
  719. /* work around issue 8 */
  720. for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
  721. musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
  722. musb_writel(tbase, TUSB_SCRATCH_PAD, i);
  723. reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
  724. if (reg == i)
  725. break;
  726. DBG(6, "TUSB NOR not ready\n");
  727. }
  728. /* work around issue 13 (2nd half) */
  729. tusb_set_clock_source(musb, 1);
  730. reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
  731. musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
  732. if (reg & ~TUSB_PRCM_WNORCS) {
  733. musb->is_active = 1;
  734. schedule_work(&musb->irq_work);
  735. }
  736. DBG(3, "wake %sactive %02x\n",
  737. musb->is_active ? "" : "in", reg);
  738. /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
  739. }
  740. if (int_src & TUSB_INT_SRC_USB_IP_CONN)
  741. del_timer(&musb_idle_timer);
  742. /* OTG state change reports (annoyingly) not issued by Mentor core */
  743. if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
  744. | TUSB_INT_SRC_OTG_TIMEOUT
  745. | TUSB_INT_SRC_ID_STATUS_CHNG))
  746. idle_timeout = tusb_otg_ints(musb, int_src, tbase);
  747. /* TX dma callback must be handled here, RX dma callback is
  748. * handled in tusb_omap_dma_cb.
  749. */
  750. if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
  751. u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
  752. u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
  753. DBG(3, "DMA IRQ %08x\n", dma_src);
  754. real_dma_src = ~real_dma_src & dma_src;
  755. if (tusb_dma_omap() && real_dma_src) {
  756. int tx_source = (real_dma_src & 0xffff);
  757. int i;
  758. for (i = 1; i <= 15; i++) {
  759. if (tx_source & (1 << i)) {
  760. DBG(3, "completing ep%i %s\n", i, "tx");
  761. musb_dma_completion(musb, i, 1);
  762. }
  763. }
  764. }
  765. musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
  766. }
  767. /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
  768. if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
  769. u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
  770. musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
  771. musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
  772. musb->int_tx = (musb_src & 0xffff);
  773. } else {
  774. musb->int_rx = 0;
  775. musb->int_tx = 0;
  776. }
  777. if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
  778. musb_interrupt(musb);
  779. /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
  780. musb_writel(tbase, TUSB_INT_SRC_CLEAR,
  781. int_src & ~TUSB_INT_MASK_RESERVED_BITS);
  782. musb_platform_try_idle(musb, idle_timeout);
  783. musb_writel(tbase, TUSB_INT_MASK, int_mask);
  784. spin_unlock_irqrestore(&musb->lock, flags);
  785. return IRQ_HANDLED;
  786. }
  787. static int dma_off;
  788. /*
  789. * Enables TUSB6010. Caller must take care of locking.
  790. * REVISIT:
  791. * - Check what is unnecessary in MGC_HdrcStart()
  792. */
  793. void musb_platform_enable(struct musb *musb)
  794. {
  795. void __iomem *tbase = musb->ctrl_base;
  796. /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
  797. * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
  798. musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
  799. /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
  800. musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
  801. musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
  802. musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
  803. /* Clear all subsystem interrups */
  804. musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
  805. musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
  806. musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
  807. /* Acknowledge pending interrupt(s) */
  808. musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
  809. /* Only 0 clock cycles for minimum interrupt de-assertion time and
  810. * interrupt polarity active low seems to work reliably here */
  811. musb_writel(tbase, TUSB_INT_CTRL_CONF,
  812. TUSB_INT_CTRL_CONF_INT_RELCYC(0));
  813. set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
  814. /* maybe force into the Default-A OTG state machine */
  815. if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
  816. & TUSB_DEV_OTG_STAT_ID_STATUS))
  817. musb_writel(tbase, TUSB_INT_SRC_SET,
  818. TUSB_INT_SRC_ID_STATUS_CHNG);
  819. if (is_dma_capable() && dma_off)
  820. printk(KERN_WARNING "%s %s: dma not reactivated\n",
  821. __FILE__, __func__);
  822. else
  823. dma_off = 1;
  824. }
  825. /*
  826. * Disables TUSB6010. Caller must take care of locking.
  827. */
  828. void musb_platform_disable(struct musb *musb)
  829. {
  830. void __iomem *tbase = musb->ctrl_base;
  831. /* FIXME stop DMA, IRQs, timers, ... */
  832. /* disable all IRQs */
  833. musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
  834. musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
  835. musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
  836. musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
  837. del_timer(&musb_idle_timer);
  838. if (is_dma_capable() && !dma_off) {
  839. printk(KERN_WARNING "%s %s: dma still active\n",
  840. __FILE__, __func__);
  841. dma_off = 1;
  842. }
  843. }
  844. /*
  845. * Sets up TUSB6010 CPU interface specific signals and registers
  846. * Note: Settings optimized for OMAP24xx
  847. */
  848. static void __init tusb_setup_cpu_interface(struct musb *musb)
  849. {
  850. void __iomem *tbase = musb->ctrl_base;
  851. /*
  852. * Disable GPIO[5:0] pullups (used as output DMA requests)
  853. * Don't disable GPIO[7:6] as they are needed for wake-up.
  854. */
  855. musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
  856. /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
  857. musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
  858. /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
  859. musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
  860. /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
  861. * de-assertion time 2 system clocks p 62 */
  862. musb_writel(tbase, TUSB_DMA_REQ_CONF,
  863. TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
  864. TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
  865. TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
  866. /* Set 0 wait count for synchronous burst access */
  867. musb_writel(tbase, TUSB_WAIT_COUNT, 1);
  868. }
  869. static int __init tusb_start(struct musb *musb)
  870. {
  871. void __iomem *tbase = musb->ctrl_base;
  872. int ret = 0;
  873. unsigned long flags;
  874. u32 reg;
  875. if (musb->board_set_power)
  876. ret = musb->board_set_power(1);
  877. if (ret != 0) {
  878. printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
  879. return ret;
  880. }
  881. spin_lock_irqsave(&musb->lock, flags);
  882. if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
  883. TUSB_PROD_TEST_RESET_VAL) {
  884. printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
  885. goto err;
  886. }
  887. ret = tusb_print_revision(musb);
  888. if (ret < 2) {
  889. printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
  890. ret);
  891. goto err;
  892. }
  893. /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
  894. * NOR FLASH interface is used */
  895. musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
  896. /* Select PHY free running 60MHz as a system clock */
  897. tusb_set_clock_source(musb, 1);
  898. /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
  899. * power saving, enable VBus detect and session end comparators,
  900. * enable IDpullup, enable VBus charging */
  901. musb_writel(tbase, TUSB_PRCM_MNGMT,
  902. TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
  903. TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
  904. TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
  905. TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
  906. TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
  907. tusb_setup_cpu_interface(musb);
  908. /* simplify: always sense/pullup ID pins, as if in OTG mode */
  909. reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  910. reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  911. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
  912. reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  913. reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  914. musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
  915. spin_unlock_irqrestore(&musb->lock, flags);
  916. return 0;
  917. err:
  918. spin_unlock_irqrestore(&musb->lock, flags);
  919. if (musb->board_set_power)
  920. musb->board_set_power(0);
  921. return -ENODEV;
  922. }
  923. int __init musb_platform_init(struct musb *musb)
  924. {
  925. struct platform_device *pdev;
  926. struct resource *mem;
  927. void __iomem *sync;
  928. int ret;
  929. pdev = to_platform_device(musb->controller);
  930. /* dma address for async dma */
  931. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  932. musb->async = mem->start;
  933. /* dma address for sync dma */
  934. mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  935. if (!mem) {
  936. pr_debug("no sync dma resource?\n");
  937. return -ENODEV;
  938. }
  939. musb->sync = mem->start;
  940. sync = ioremap(mem->start, mem->end - mem->start + 1);
  941. if (!sync) {
  942. pr_debug("ioremap for sync failed\n");
  943. return -ENOMEM;
  944. }
  945. musb->sync_va = sync;
  946. /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
  947. * FIFOs at 0x600, TUSB at 0x800
  948. */
  949. musb->mregs += TUSB_BASE_OFFSET;
  950. ret = tusb_start(musb);
  951. if (ret) {
  952. printk(KERN_ERR "Could not start tusb6010 (%d)\n",
  953. ret);
  954. return -ENODEV;
  955. }
  956. musb->isr = tusb_interrupt;
  957. if (is_host_enabled(musb))
  958. musb->board_set_vbus = tusb_source_power;
  959. if (is_peripheral_enabled(musb))
  960. musb->xceiv.set_power = tusb_draw_power;
  961. setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
  962. return ret;
  963. }
  964. int musb_platform_exit(struct musb *musb)
  965. {
  966. del_timer_sync(&musb_idle_timer);
  967. if (musb->board_set_power)
  968. musb->board_set_power(0);
  969. iounmap(musb->sync_va);
  970. return 0;
  971. }