hfc_pci.c 54 KB

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  1. /* $Id: hfc_pci.c,v 1.48.2.4 2004/02/11 13:21:33 keil Exp $
  2. *
  3. * low level driver for CCD's hfc-pci based cards
  4. *
  5. * Author Werner Cornelius
  6. * based on existing driver for CCD hfc ISA cards
  7. * Copyright by Werner Cornelius <werner@isdn4linux.de>
  8. * by Karsten Keil <keil@isdn4linux.de>
  9. *
  10. * This software may be used and distributed according to the terms
  11. * of the GNU General Public License, incorporated herein by reference.
  12. *
  13. * For changes and modifications please read
  14. * Documentation/isdn/HiSax.cert
  15. *
  16. */
  17. #include <linux/init.h>
  18. #include "hisax.h"
  19. #include "hfc_pci.h"
  20. #include "isdnl1.h"
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. static const char *hfcpci_revision = "$Revision: 1.48.2.4 $";
  24. /* table entry in the PCI devices list */
  25. typedef struct {
  26. int vendor_id;
  27. int device_id;
  28. char *vendor_name;
  29. char *card_name;
  30. } PCI_ENTRY;
  31. #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
  32. #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
  33. #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
  34. static const PCI_ENTRY id_list[] =
  35. {
  36. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0, "CCD/Billion/Asuscom", "2BD0"},
  37. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000, "Billion", "B000"},
  38. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006, "Billion", "B006"},
  39. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007, "Billion", "B007"},
  40. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008, "Billion", "B008"},
  41. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009, "Billion", "B009"},
  42. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A, "Billion", "B00A"},
  43. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B, "Billion", "B00B"},
  44. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C, "Billion", "B00C"},
  45. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100, "Seyeon", "B100"},
  46. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B700, "Primux II S0", "B700"},
  47. {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B701, "Primux II S0 NT", "B701"},
  48. {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1, "Abocom/Magitek", "2BD1"},
  49. {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675, "Asuscom/Askey", "675"},
  50. {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT, "German telekom", "T-Concept"},
  51. {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T, "German telekom", "A1T"},
  52. {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575, "Motorola MC145575", "MC145575"},
  53. {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0, "Zoltrix", "2BD0"},
  54. {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,"Digi International", "Digi DataFire Micro V IOM2 (Europe)"},
  55. {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,"Digi International", "Digi DataFire Micro V (Europe)"},
  56. {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,"Digi International", "Digi DataFire Micro V IOM2 (North America)"},
  57. {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,"Digi International", "Digi DataFire Micro V (North America)"},
  58. {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2, "Sitecom Europe", "DC-105 ISDN PCI"},
  59. {0, 0, NULL, NULL},
  60. };
  61. /******************************************/
  62. /* free hardware resources used by driver */
  63. /******************************************/
  64. static void
  65. release_io_hfcpci(struct IsdnCardState *cs)
  66. {
  67. printk(KERN_INFO "HiSax: release hfcpci at %p\n",
  68. cs->hw.hfcpci.pci_io);
  69. cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
  70. Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
  71. Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
  72. mdelay(10);
  73. Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
  74. mdelay(10);
  75. Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
  76. pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */
  77. del_timer(&cs->hw.hfcpci.timer);
  78. pci_free_consistent(cs->hw.hfcpci.dev, 0x8000,
  79. cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma);
  80. cs->hw.hfcpci.fifos = NULL;
  81. iounmap((void *)cs->hw.hfcpci.pci_io);
  82. }
  83. /********************************************************************************/
  84. /* function called to reset the HFC PCI chip. A complete software reset of chip */
  85. /* and fifos is done. */
  86. /********************************************************************************/
  87. static void
  88. reset_hfcpci(struct IsdnCardState *cs)
  89. {
  90. pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
  91. cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
  92. Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
  93. printk(KERN_INFO "HFC_PCI: resetting card\n");
  94. pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable memory ports + busmaster */
  95. Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
  96. mdelay(10);
  97. Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
  98. mdelay(10);
  99. if (Read_hfc(cs, HFCPCI_STATUS) & 2)
  100. printk(KERN_WARNING "HFC-PCI init bit busy\n");
  101. cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */
  102. Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
  103. cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
  104. Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
  105. Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */
  106. cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE;
  107. Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */
  108. cs->hw.hfcpci.bswapped = 0; /* no exchange */
  109. cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */
  110. cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
  111. Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
  112. cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
  113. HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
  114. Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
  115. /* Clear already pending ints */
  116. if (Read_hfc(cs, HFCPCI_INT_S1));
  117. Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */
  118. udelay(10);
  119. Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */
  120. cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */
  121. Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
  122. cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
  123. Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
  124. cs->hw.hfcpci.sctrl_r = 0;
  125. Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
  126. /* Init GCI/IOM2 in master mode */
  127. /* Slots 0 and 1 are set for B-chan 1 and 2 */
  128. /* D- and monitor/CI channel are not enabled */
  129. /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
  130. /* STIO2 is used as data input, B1+B2 from IOM->ST */
  131. /* ST B-channel send disabled -> continous 1s */
  132. /* The IOM slots are always enabled */
  133. cs->hw.hfcpci.conn = 0x36; /* set data flow directions */
  134. Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
  135. Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
  136. Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
  137. Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
  138. Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
  139. /* Finally enable IRQ output */
  140. cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE;
  141. Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
  142. if (Read_hfc(cs, HFCPCI_INT_S1));
  143. }
  144. /***************************************************/
  145. /* Timer function called when kernel timer expires */
  146. /***************************************************/
  147. static void
  148. hfcpci_Timer(struct IsdnCardState *cs)
  149. {
  150. cs->hw.hfcpci.timer.expires = jiffies + 75;
  151. /* WD RESET */
  152. /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
  153. add_timer(&cs->hw.hfcpci.timer);
  154. */
  155. }
  156. /*********************************/
  157. /* schedule a new D-channel task */
  158. /*********************************/
  159. static void
  160. sched_event_D_pci(struct IsdnCardState *cs, int event)
  161. {
  162. test_and_set_bit(event, &cs->event);
  163. schedule_work(&cs->tqueue);
  164. }
  165. /*********************************/
  166. /* schedule a new b_channel task */
  167. /*********************************/
  168. static void
  169. hfcpci_sched_event(struct BCState *bcs, int event)
  170. {
  171. test_and_set_bit(event, &bcs->event);
  172. schedule_work(&bcs->tqueue);
  173. }
  174. /************************************************/
  175. /* select a b-channel entry matching and active */
  176. /************************************************/
  177. static
  178. struct BCState *
  179. Sel_BCS(struct IsdnCardState *cs, int channel)
  180. {
  181. if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
  182. return (&cs->bcs[0]);
  183. else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
  184. return (&cs->bcs[1]);
  185. else
  186. return (NULL);
  187. }
  188. /***************************************/
  189. /* clear the desired B-channel rx fifo */
  190. /***************************************/
  191. static void hfcpci_clear_fifo_rx(struct IsdnCardState *cs, int fifo)
  192. { u_char fifo_state;
  193. bzfifo_type *bzr;
  194. if (fifo) {
  195. bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
  196. fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX;
  197. } else {
  198. bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
  199. fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX;
  200. }
  201. if (fifo_state)
  202. cs->hw.hfcpci.fifo_en ^= fifo_state;
  203. Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
  204. cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0;
  205. bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
  206. bzr->za[MAX_B_FRAMES].z2 = bzr->za[MAX_B_FRAMES].z1;
  207. bzr->f1 = MAX_B_FRAMES;
  208. bzr->f2 = bzr->f1; /* init F pointers to remain constant */
  209. if (fifo_state)
  210. cs->hw.hfcpci.fifo_en |= fifo_state;
  211. Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
  212. }
  213. /***************************************/
  214. /* clear the desired B-channel tx fifo */
  215. /***************************************/
  216. static void hfcpci_clear_fifo_tx(struct IsdnCardState *cs, int fifo)
  217. { u_char fifo_state;
  218. bzfifo_type *bzt;
  219. if (fifo) {
  220. bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
  221. fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX;
  222. } else {
  223. bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
  224. fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX;
  225. }
  226. if (fifo_state)
  227. cs->hw.hfcpci.fifo_en ^= fifo_state;
  228. Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
  229. bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
  230. bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1;
  231. bzt->f1 = MAX_B_FRAMES;
  232. bzt->f2 = bzt->f1; /* init F pointers to remain constant */
  233. if (fifo_state)
  234. cs->hw.hfcpci.fifo_en |= fifo_state;
  235. Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
  236. }
  237. /*********************************************/
  238. /* read a complete B-frame out of the buffer */
  239. /*********************************************/
  240. static struct sk_buff
  241. *
  242. hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type * bz, u_char * bdata, int count)
  243. {
  244. u_char *ptr, *ptr1, new_f2;
  245. struct sk_buff *skb;
  246. struct IsdnCardState *cs = bcs->cs;
  247. int total, maxlen, new_z2;
  248. z_type *zp;
  249. if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
  250. debugl1(cs, "hfcpci_empty_fifo");
  251. zp = &bz->za[bz->f2]; /* point to Z-Regs */
  252. new_z2 = zp->z2 + count; /* new position in fifo */
  253. if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
  254. new_z2 -= B_FIFO_SIZE; /* buffer wrap */
  255. new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
  256. if ((count > HSCX_BUFMAX + 3) || (count < 4) ||
  257. (*(bdata + (zp->z1 - B_SUB_VAL)))) {
  258. if (cs->debug & L1_DEB_WARN)
  259. debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count);
  260. #ifdef ERROR_STATISTIC
  261. bcs->err_inv++;
  262. #endif
  263. bz->za[new_f2].z2 = new_z2;
  264. bz->f2 = new_f2; /* next buffer */
  265. skb = NULL;
  266. } else if (!(skb = dev_alloc_skb(count - 3)))
  267. printk(KERN_WARNING "HFCPCI: receive out of memory\n");
  268. else {
  269. total = count;
  270. count -= 3;
  271. ptr = skb_put(skb, count);
  272. if (zp->z2 + count <= B_FIFO_SIZE + B_SUB_VAL)
  273. maxlen = count; /* complete transfer */
  274. else
  275. maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
  276. ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
  277. memcpy(ptr, ptr1, maxlen); /* copy data */
  278. count -= maxlen;
  279. if (count) { /* rest remaining */
  280. ptr += maxlen;
  281. ptr1 = bdata; /* start of buffer */
  282. memcpy(ptr, ptr1, count); /* rest */
  283. }
  284. bz->za[new_f2].z2 = new_z2;
  285. bz->f2 = new_f2; /* next buffer */
  286. }
  287. return (skb);
  288. }
  289. /*******************************/
  290. /* D-channel receive procedure */
  291. /*******************************/
  292. static
  293. int
  294. receive_dmsg(struct IsdnCardState *cs)
  295. {
  296. struct sk_buff *skb;
  297. int maxlen;
  298. int rcnt, total;
  299. int count = 5;
  300. u_char *ptr, *ptr1;
  301. dfifo_type *df;
  302. z_type *zp;
  303. df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx;
  304. if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  305. debugl1(cs, "rec_dmsg blocked");
  306. return (1);
  307. }
  308. while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
  309. zp = &df->za[df->f2 & D_FREG_MASK];
  310. rcnt = zp->z1 - zp->z2;
  311. if (rcnt < 0)
  312. rcnt += D_FIFO_SIZE;
  313. rcnt++;
  314. if (cs->debug & L1_DEB_ISAC)
  315. debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
  316. df->f1, df->f2, zp->z1, zp->z2, rcnt);
  317. if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
  318. (df->data[zp->z1])) {
  319. if (cs->debug & L1_DEB_WARN)
  320. debugl1(cs, "empty_fifo hfcpci paket inv. len %d or crc %d", rcnt, df->data[zp->z1]);
  321. #ifdef ERROR_STATISTIC
  322. cs->err_rx++;
  323. #endif
  324. df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
  325. df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + rcnt) & (D_FIFO_SIZE - 1);
  326. } else if ((skb = dev_alloc_skb(rcnt - 3))) {
  327. total = rcnt;
  328. rcnt -= 3;
  329. ptr = skb_put(skb, rcnt);
  330. if (zp->z2 + rcnt <= D_FIFO_SIZE)
  331. maxlen = rcnt; /* complete transfer */
  332. else
  333. maxlen = D_FIFO_SIZE - zp->z2; /* maximum */
  334. ptr1 = df->data + zp->z2; /* start of data */
  335. memcpy(ptr, ptr1, maxlen); /* copy data */
  336. rcnt -= maxlen;
  337. if (rcnt) { /* rest remaining */
  338. ptr += maxlen;
  339. ptr1 = df->data; /* start of buffer */
  340. memcpy(ptr, ptr1, rcnt); /* rest */
  341. }
  342. df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
  343. df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + total) & (D_FIFO_SIZE - 1);
  344. skb_queue_tail(&cs->rq, skb);
  345. sched_event_D_pci(cs, D_RCVBUFREADY);
  346. } else
  347. printk(KERN_WARNING "HFC-PCI: D receive out of memory\n");
  348. }
  349. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  350. return (1);
  351. }
  352. /*******************************************************************************/
  353. /* check for transparent receive data and read max one threshold size if avail */
  354. /*******************************************************************************/
  355. static int
  356. hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type * bz, u_char * bdata)
  357. {
  358. unsigned short *z1r, *z2r;
  359. int new_z2, fcnt, maxlen;
  360. struct sk_buff *skb;
  361. u_char *ptr, *ptr1;
  362. z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
  363. z2r = z1r + 1;
  364. if (!(fcnt = *z1r - *z2r))
  365. return (0); /* no data avail */
  366. if (fcnt <= 0)
  367. fcnt += B_FIFO_SIZE; /* bytes actually buffered */
  368. if (fcnt > HFCPCI_BTRANS_THRESHOLD)
  369. fcnt = HFCPCI_BTRANS_THRESHOLD; /* limit size */
  370. new_z2 = *z2r + fcnt; /* new position in fifo */
  371. if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
  372. new_z2 -= B_FIFO_SIZE; /* buffer wrap */
  373. if (!(skb = dev_alloc_skb(fcnt)))
  374. printk(KERN_WARNING "HFCPCI: receive out of memory\n");
  375. else {
  376. ptr = skb_put(skb, fcnt);
  377. if (*z2r + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
  378. maxlen = fcnt; /* complete transfer */
  379. else
  380. maxlen = B_FIFO_SIZE + B_SUB_VAL - *z2r; /* maximum */
  381. ptr1 = bdata + (*z2r - B_SUB_VAL); /* start of data */
  382. memcpy(ptr, ptr1, maxlen); /* copy data */
  383. fcnt -= maxlen;
  384. if (fcnt) { /* rest remaining */
  385. ptr += maxlen;
  386. ptr1 = bdata; /* start of buffer */
  387. memcpy(ptr, ptr1, fcnt); /* rest */
  388. }
  389. skb_queue_tail(&bcs->rqueue, skb);
  390. hfcpci_sched_event(bcs, B_RCVBUFREADY);
  391. }
  392. *z2r = new_z2; /* new position */
  393. return (1);
  394. } /* hfcpci_empty_fifo_trans */
  395. /**********************************/
  396. /* B-channel main receive routine */
  397. /**********************************/
  398. static void
  399. main_rec_hfcpci(struct BCState *bcs)
  400. {
  401. struct IsdnCardState *cs = bcs->cs;
  402. int rcnt, real_fifo;
  403. int receive, count = 5;
  404. struct sk_buff *skb;
  405. bzfifo_type *bz;
  406. u_char *bdata;
  407. z_type *zp;
  408. if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
  409. bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
  410. bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
  411. real_fifo = 1;
  412. } else {
  413. bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
  414. bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
  415. real_fifo = 0;
  416. }
  417. Begin:
  418. count--;
  419. if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  420. debugl1(cs, "rec_data %d blocked", bcs->channel);
  421. return;
  422. }
  423. if (bz->f1 != bz->f2) {
  424. if (cs->debug & L1_DEB_HSCX)
  425. debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)",
  426. bcs->channel, bz->f1, bz->f2);
  427. zp = &bz->za[bz->f2];
  428. rcnt = zp->z1 - zp->z2;
  429. if (rcnt < 0)
  430. rcnt += B_FIFO_SIZE;
  431. rcnt++;
  432. if (cs->debug & L1_DEB_HSCX)
  433. debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)",
  434. bcs->channel, zp->z1, zp->z2, rcnt);
  435. if ((skb = hfcpci_empty_fifo(bcs, bz, bdata, rcnt))) {
  436. skb_queue_tail(&bcs->rqueue, skb);
  437. hfcpci_sched_event(bcs, B_RCVBUFREADY);
  438. }
  439. rcnt = bz->f1 - bz->f2;
  440. if (rcnt < 0)
  441. rcnt += MAX_B_FRAMES + 1;
  442. if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) {
  443. rcnt = 0;
  444. hfcpci_clear_fifo_rx(cs, real_fifo);
  445. }
  446. cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt;
  447. if (rcnt > 1)
  448. receive = 1;
  449. else
  450. receive = 0;
  451. } else if (bcs->mode == L1_MODE_TRANS)
  452. receive = hfcpci_empty_fifo_trans(bcs, bz, bdata);
  453. else
  454. receive = 0;
  455. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  456. if (count && receive)
  457. goto Begin;
  458. }
  459. /**************************/
  460. /* D-channel send routine */
  461. /**************************/
  462. static void
  463. hfcpci_fill_dfifo(struct IsdnCardState *cs)
  464. {
  465. int fcnt;
  466. int count, new_z1, maxlen;
  467. dfifo_type *df;
  468. u_char *src, *dst, new_f1;
  469. if (!cs->tx_skb)
  470. return;
  471. if (cs->tx_skb->len <= 0)
  472. return;
  473. df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx;
  474. if (cs->debug & L1_DEB_ISAC)
  475. debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)",
  476. df->f1, df->f2,
  477. df->za[df->f1 & D_FREG_MASK].z1);
  478. fcnt = df->f1 - df->f2; /* frame count actually buffered */
  479. if (fcnt < 0)
  480. fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
  481. if (fcnt > (MAX_D_FRAMES - 1)) {
  482. if (cs->debug & L1_DEB_ISAC)
  483. debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames");
  484. #ifdef ERROR_STATISTIC
  485. cs->err_tx++;
  486. #endif
  487. return;
  488. }
  489. /* now determine free bytes in FIFO buffer */
  490. count = df->za[df->f2 & D_FREG_MASK].z2 - df->za[df->f1 & D_FREG_MASK].z1 - 1;
  491. if (count <= 0)
  492. count += D_FIFO_SIZE; /* count now contains available bytes */
  493. if (cs->debug & L1_DEB_ISAC)
  494. debugl1(cs, "hfcpci_fill_Dfifo count(%ld/%d)",
  495. cs->tx_skb->len, count);
  496. if (count < cs->tx_skb->len) {
  497. if (cs->debug & L1_DEB_ISAC)
  498. debugl1(cs, "hfcpci_fill_Dfifo no fifo mem");
  499. return;
  500. }
  501. count = cs->tx_skb->len; /* get frame len */
  502. new_z1 = (df->za[df->f1 & D_FREG_MASK].z1 + count) & (D_FIFO_SIZE - 1);
  503. new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
  504. src = cs->tx_skb->data; /* source pointer */
  505. dst = df->data + df->za[df->f1 & D_FREG_MASK].z1;
  506. maxlen = D_FIFO_SIZE - df->za[df->f1 & D_FREG_MASK].z1; /* end fifo */
  507. if (maxlen > count)
  508. maxlen = count; /* limit size */
  509. memcpy(dst, src, maxlen); /* first copy */
  510. count -= maxlen; /* remaining bytes */
  511. if (count) {
  512. dst = df->data; /* start of buffer */
  513. src += maxlen; /* new position */
  514. memcpy(dst, src, count);
  515. }
  516. df->za[new_f1 & D_FREG_MASK].z1 = new_z1; /* for next buffer */
  517. df->za[df->f1 & D_FREG_MASK].z1 = new_z1; /* new pos actual buffer */
  518. df->f1 = new_f1; /* next frame */
  519. dev_kfree_skb_any(cs->tx_skb);
  520. cs->tx_skb = NULL;
  521. }
  522. /**************************/
  523. /* B-channel send routine */
  524. /**************************/
  525. static void
  526. hfcpci_fill_fifo(struct BCState *bcs)
  527. {
  528. struct IsdnCardState *cs = bcs->cs;
  529. int maxlen, fcnt;
  530. int count, new_z1;
  531. bzfifo_type *bz;
  532. u_char *bdata;
  533. u_char new_f1, *src, *dst;
  534. unsigned short *z1t, *z2t;
  535. if (!bcs->tx_skb)
  536. return;
  537. if (bcs->tx_skb->len <= 0)
  538. return;
  539. if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
  540. bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
  541. bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2;
  542. } else {
  543. bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
  544. bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1;
  545. }
  546. if (bcs->mode == L1_MODE_TRANS) {
  547. z1t = &bz->za[MAX_B_FRAMES].z1;
  548. z2t = z1t + 1;
  549. if (cs->debug & L1_DEB_HSCX)
  550. debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)",
  551. bcs->channel, *z1t, *z2t);
  552. fcnt = *z2t - *z1t;
  553. if (fcnt <= 0)
  554. fcnt += B_FIFO_SIZE; /* fcnt contains available bytes in fifo */
  555. fcnt = B_FIFO_SIZE - fcnt; /* remaining bytes to send */
  556. while ((fcnt < 2 * HFCPCI_BTRANS_THRESHOLD) && (bcs->tx_skb)) {
  557. if (bcs->tx_skb->len < B_FIFO_SIZE - fcnt) {
  558. /* data is suitable for fifo */
  559. count = bcs->tx_skb->len;
  560. new_z1 = *z1t + count; /* new buffer Position */
  561. if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
  562. new_z1 -= B_FIFO_SIZE; /* buffer wrap */
  563. src = bcs->tx_skb->data; /* source pointer */
  564. dst = bdata + (*z1t - B_SUB_VAL);
  565. maxlen = (B_FIFO_SIZE + B_SUB_VAL) - *z1t; /* end of fifo */
  566. if (maxlen > count)
  567. maxlen = count; /* limit size */
  568. memcpy(dst, src, maxlen); /* first copy */
  569. count -= maxlen; /* remaining bytes */
  570. if (count) {
  571. dst = bdata; /* start of buffer */
  572. src += maxlen; /* new position */
  573. memcpy(dst, src, count);
  574. }
  575. bcs->tx_cnt -= bcs->tx_skb->len;
  576. fcnt += bcs->tx_skb->len;
  577. *z1t = new_z1; /* now send data */
  578. } else if (cs->debug & L1_DEB_HSCX)
  579. debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded",
  580. bcs->channel, bcs->tx_skb->len);
  581. if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
  582. (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
  583. u_long flags;
  584. spin_lock_irqsave(&bcs->aclock, flags);
  585. bcs->ackcnt += bcs->tx_skb->len;
  586. spin_unlock_irqrestore(&bcs->aclock, flags);
  587. schedule_event(bcs, B_ACKPENDING);
  588. }
  589. dev_kfree_skb_any(bcs->tx_skb);
  590. bcs->tx_skb = skb_dequeue(&bcs->squeue); /* fetch next data */
  591. }
  592. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  593. return;
  594. }
  595. if (cs->debug & L1_DEB_HSCX)
  596. debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)",
  597. bcs->channel, bz->f1, bz->f2,
  598. bz->za[bz->f1].z1);
  599. fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
  600. if (fcnt < 0)
  601. fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
  602. if (fcnt > (MAX_B_FRAMES - 1)) {
  603. if (cs->debug & L1_DEB_HSCX)
  604. debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames");
  605. return;
  606. }
  607. /* now determine free bytes in FIFO buffer */
  608. count = bz->za[bz->f2].z2 - bz->za[bz->f1].z1 - 1;
  609. if (count <= 0)
  610. count += B_FIFO_SIZE; /* count now contains available bytes */
  611. if (cs->debug & L1_DEB_HSCX)
  612. debugl1(cs, "hfcpci_fill_fifo %d count(%ld/%d),%lx",
  613. bcs->channel, bcs->tx_skb->len,
  614. count, current->state);
  615. if (count < bcs->tx_skb->len) {
  616. if (cs->debug & L1_DEB_HSCX)
  617. debugl1(cs, "hfcpci_fill_fifo no fifo mem");
  618. return;
  619. }
  620. count = bcs->tx_skb->len; /* get frame len */
  621. new_z1 = bz->za[bz->f1].z1 + count; /* new buffer Position */
  622. if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
  623. new_z1 -= B_FIFO_SIZE; /* buffer wrap */
  624. new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
  625. src = bcs->tx_skb->data; /* source pointer */
  626. dst = bdata + (bz->za[bz->f1].z1 - B_SUB_VAL);
  627. maxlen = (B_FIFO_SIZE + B_SUB_VAL) - bz->za[bz->f1].z1; /* end fifo */
  628. if (maxlen > count)
  629. maxlen = count; /* limit size */
  630. memcpy(dst, src, maxlen); /* first copy */
  631. count -= maxlen; /* remaining bytes */
  632. if (count) {
  633. dst = bdata; /* start of buffer */
  634. src += maxlen; /* new position */
  635. memcpy(dst, src, count);
  636. }
  637. bcs->tx_cnt -= bcs->tx_skb->len;
  638. if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
  639. (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
  640. u_long flags;
  641. spin_lock_irqsave(&bcs->aclock, flags);
  642. bcs->ackcnt += bcs->tx_skb->len;
  643. spin_unlock_irqrestore(&bcs->aclock, flags);
  644. schedule_event(bcs, B_ACKPENDING);
  645. }
  646. bz->za[new_f1].z1 = new_z1; /* for next buffer */
  647. bz->f1 = new_f1; /* next frame */
  648. dev_kfree_skb_any(bcs->tx_skb);
  649. bcs->tx_skb = NULL;
  650. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  651. }
  652. /**********************************************/
  653. /* D-channel l1 state call for leased NT-mode */
  654. /**********************************************/
  655. static void
  656. dch_nt_l2l1(struct PStack *st, int pr, void *arg)
  657. {
  658. struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
  659. switch (pr) {
  660. case (PH_DATA | REQUEST):
  661. case (PH_PULL | REQUEST):
  662. case (PH_PULL | INDICATION):
  663. st->l1.l1hw(st, pr, arg);
  664. break;
  665. case (PH_ACTIVATE | REQUEST):
  666. st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
  667. break;
  668. case (PH_TESTLOOP | REQUEST):
  669. if (1 & (long) arg)
  670. debugl1(cs, "PH_TEST_LOOP B1");
  671. if (2 & (long) arg)
  672. debugl1(cs, "PH_TEST_LOOP B2");
  673. if (!(3 & (long) arg))
  674. debugl1(cs, "PH_TEST_LOOP DISABLED");
  675. st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
  676. break;
  677. default:
  678. if (cs->debug)
  679. debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
  680. break;
  681. }
  682. }
  683. /***********************/
  684. /* set/reset echo mode */
  685. /***********************/
  686. static int
  687. hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
  688. {
  689. u_long flags;
  690. int i = *(unsigned int *) ic->parm.num;
  691. if ((ic->arg == 98) &&
  692. (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
  693. spin_lock_irqsave(&cs->lock, flags);
  694. Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */
  695. Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */
  696. udelay(10);
  697. cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT;
  698. Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */
  699. udelay(10);
  700. Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */
  701. udelay(10);
  702. Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
  703. cs->dc.hfcpci.ph_state = 1;
  704. cs->hw.hfcpci.nt_mode = 1;
  705. cs->hw.hfcpci.nt_timer = 0;
  706. cs->stlist->l2.l2l1 = dch_nt_l2l1;
  707. spin_unlock_irqrestore(&cs->lock, flags);
  708. debugl1(cs, "NT mode activated");
  709. return (0);
  710. }
  711. if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) ||
  712. (cs->hw.hfcpci.nt_mode) || (ic->arg != 12))
  713. return (-EINVAL);
  714. spin_lock_irqsave(&cs->lock, flags);
  715. if (i) {
  716. cs->logecho = 1;
  717. cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */
  718. cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC;
  719. cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX;
  720. } else {
  721. cs->logecho = 0;
  722. cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */
  723. cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC;
  724. cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX;
  725. }
  726. cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
  727. cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
  728. cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */
  729. cs->hw.hfcpci.ctmt &= ~2;
  730. Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
  731. Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
  732. Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
  733. Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
  734. Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
  735. Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
  736. Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
  737. spin_unlock_irqrestore(&cs->lock, flags);
  738. return (0);
  739. } /* hfcpci_auxcmd */
  740. /*****************************/
  741. /* E-channel receive routine */
  742. /*****************************/
  743. static void
  744. receive_emsg(struct IsdnCardState *cs)
  745. {
  746. int rcnt;
  747. int receive, count = 5;
  748. bzfifo_type *bz;
  749. u_char *bdata;
  750. z_type *zp;
  751. u_char *ptr, *ptr1, new_f2;
  752. int total, maxlen, new_z2;
  753. u_char e_buffer[256];
  754. bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
  755. bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
  756. Begin:
  757. count--;
  758. if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  759. debugl1(cs, "echo_rec_data blocked");
  760. return;
  761. }
  762. if (bz->f1 != bz->f2) {
  763. if (cs->debug & L1_DEB_ISAC)
  764. debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)",
  765. bz->f1, bz->f2);
  766. zp = &bz->za[bz->f2];
  767. rcnt = zp->z1 - zp->z2;
  768. if (rcnt < 0)
  769. rcnt += B_FIFO_SIZE;
  770. rcnt++;
  771. if (cs->debug & L1_DEB_ISAC)
  772. debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)",
  773. zp->z1, zp->z2, rcnt);
  774. new_z2 = zp->z2 + rcnt; /* new position in fifo */
  775. if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
  776. new_z2 -= B_FIFO_SIZE; /* buffer wrap */
  777. new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
  778. if ((rcnt > 256 + 3) || (count < 4) ||
  779. (*(bdata + (zp->z1 - B_SUB_VAL)))) {
  780. if (cs->debug & L1_DEB_WARN)
  781. debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt);
  782. bz->za[new_f2].z2 = new_z2;
  783. bz->f2 = new_f2; /* next buffer */
  784. } else {
  785. total = rcnt;
  786. rcnt -= 3;
  787. ptr = e_buffer;
  788. if (zp->z2 <= B_FIFO_SIZE + B_SUB_VAL)
  789. maxlen = rcnt; /* complete transfer */
  790. else
  791. maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
  792. ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
  793. memcpy(ptr, ptr1, maxlen); /* copy data */
  794. rcnt -= maxlen;
  795. if (rcnt) { /* rest remaining */
  796. ptr += maxlen;
  797. ptr1 = bdata; /* start of buffer */
  798. memcpy(ptr, ptr1, rcnt); /* rest */
  799. }
  800. bz->za[new_f2].z2 = new_z2;
  801. bz->f2 = new_f2; /* next buffer */
  802. if (cs->debug & DEB_DLOG_HEX) {
  803. ptr = cs->dlog;
  804. if ((total - 3) < MAX_DLOG_SPACE / 3 - 10) {
  805. *ptr++ = 'E';
  806. *ptr++ = 'C';
  807. *ptr++ = 'H';
  808. *ptr++ = 'O';
  809. *ptr++ = ':';
  810. ptr += QuickHex(ptr, e_buffer, total - 3);
  811. ptr--;
  812. *ptr++ = '\n';
  813. *ptr = 0;
  814. HiSax_putstatus(cs, NULL, cs->dlog);
  815. } else
  816. HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);
  817. }
  818. }
  819. rcnt = bz->f1 - bz->f2;
  820. if (rcnt < 0)
  821. rcnt += MAX_B_FRAMES + 1;
  822. if (rcnt > 1)
  823. receive = 1;
  824. else
  825. receive = 0;
  826. } else
  827. receive = 0;
  828. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  829. if (count && receive)
  830. goto Begin;
  831. } /* receive_emsg */
  832. /*********************/
  833. /* Interrupt handler */
  834. /*********************/
  835. static irqreturn_t
  836. hfcpci_interrupt(int intno, void *dev_id)
  837. {
  838. u_long flags;
  839. struct IsdnCardState *cs = dev_id;
  840. u_char exval;
  841. struct BCState *bcs;
  842. int count = 15;
  843. u_char val, stat;
  844. if (!(cs->hw.hfcpci.int_m2 & 0x08)) {
  845. debugl1(cs, "HFC-PCI: int_m2 %x not initialised", cs->hw.hfcpci.int_m2);
  846. return IRQ_NONE; /* not initialised */
  847. }
  848. spin_lock_irqsave(&cs->lock, flags);
  849. if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) {
  850. val = Read_hfc(cs, HFCPCI_INT_S1);
  851. if (cs->debug & L1_DEB_ISAC)
  852. debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val);
  853. } else {
  854. spin_unlock_irqrestore(&cs->lock, flags);
  855. return IRQ_NONE;
  856. }
  857. if (cs->debug & L1_DEB_ISAC)
  858. debugl1(cs, "HFC-PCI irq %x %s", val,
  859. test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
  860. "locked" : "unlocked");
  861. val &= cs->hw.hfcpci.int_m1;
  862. if (val & 0x40) { /* state machine irq */
  863. exval = Read_hfc(cs, HFCPCI_STATES) & 0xf;
  864. if (cs->debug & L1_DEB_ISAC)
  865. debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state,
  866. exval);
  867. cs->dc.hfcpci.ph_state = exval;
  868. sched_event_D_pci(cs, D_L1STATECHANGE);
  869. val &= ~0x40;
  870. }
  871. if (val & 0x80) { /* timer irq */
  872. if (cs->hw.hfcpci.nt_mode) {
  873. if ((--cs->hw.hfcpci.nt_timer) < 0)
  874. sched_event_D_pci(cs, D_L1STATECHANGE);
  875. }
  876. val &= ~0x80;
  877. Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
  878. }
  879. while (val) {
  880. if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  881. cs->hw.hfcpci.int_s1 |= val;
  882. spin_unlock_irqrestore(&cs->lock, flags);
  883. return IRQ_HANDLED;
  884. }
  885. if (cs->hw.hfcpci.int_s1 & 0x18) {
  886. exval = val;
  887. val = cs->hw.hfcpci.int_s1;
  888. cs->hw.hfcpci.int_s1 = exval;
  889. }
  890. if (val & 0x08) {
  891. if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
  892. if (cs->debug)
  893. debugl1(cs, "hfcpci spurious 0x08 IRQ");
  894. } else
  895. main_rec_hfcpci(bcs);
  896. }
  897. if (val & 0x10) {
  898. if (cs->logecho)
  899. receive_emsg(cs);
  900. else if (!(bcs = Sel_BCS(cs, 1))) {
  901. if (cs->debug)
  902. debugl1(cs, "hfcpci spurious 0x10 IRQ");
  903. } else
  904. main_rec_hfcpci(bcs);
  905. }
  906. if (val & 0x01) {
  907. if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
  908. if (cs->debug)
  909. debugl1(cs, "hfcpci spurious 0x01 IRQ");
  910. } else {
  911. if (bcs->tx_skb) {
  912. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  913. hfcpci_fill_fifo(bcs);
  914. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  915. } else
  916. debugl1(cs, "fill_data %d blocked", bcs->channel);
  917. } else {
  918. if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
  919. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  920. hfcpci_fill_fifo(bcs);
  921. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  922. } else
  923. debugl1(cs, "fill_data %d blocked", bcs->channel);
  924. } else {
  925. hfcpci_sched_event(bcs, B_XMTBUFREADY);
  926. }
  927. }
  928. }
  929. }
  930. if (val & 0x02) {
  931. if (!(bcs = Sel_BCS(cs, 1))) {
  932. if (cs->debug)
  933. debugl1(cs, "hfcpci spurious 0x02 IRQ");
  934. } else {
  935. if (bcs->tx_skb) {
  936. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  937. hfcpci_fill_fifo(bcs);
  938. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  939. } else
  940. debugl1(cs, "fill_data %d blocked", bcs->channel);
  941. } else {
  942. if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
  943. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  944. hfcpci_fill_fifo(bcs);
  945. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  946. } else
  947. debugl1(cs, "fill_data %d blocked", bcs->channel);
  948. } else {
  949. hfcpci_sched_event(bcs, B_XMTBUFREADY);
  950. }
  951. }
  952. }
  953. }
  954. if (val & 0x20) { /* receive dframe */
  955. receive_dmsg(cs);
  956. }
  957. if (val & 0x04) { /* dframe transmitted */
  958. if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
  959. del_timer(&cs->dbusytimer);
  960. if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
  961. sched_event_D_pci(cs, D_CLEARBUSY);
  962. if (cs->tx_skb) {
  963. if (cs->tx_skb->len) {
  964. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  965. hfcpci_fill_dfifo(cs);
  966. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  967. } else {
  968. debugl1(cs, "hfcpci_fill_dfifo irq blocked");
  969. }
  970. goto afterXPR;
  971. } else {
  972. dev_kfree_skb_irq(cs->tx_skb);
  973. cs->tx_cnt = 0;
  974. cs->tx_skb = NULL;
  975. }
  976. }
  977. if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
  978. cs->tx_cnt = 0;
  979. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  980. hfcpci_fill_dfifo(cs);
  981. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  982. } else {
  983. debugl1(cs, "hfcpci_fill_dfifo irq blocked");
  984. }
  985. } else
  986. sched_event_D_pci(cs, D_XMTBUFREADY);
  987. }
  988. afterXPR:
  989. if (cs->hw.hfcpci.int_s1 && count--) {
  990. val = cs->hw.hfcpci.int_s1;
  991. cs->hw.hfcpci.int_s1 = 0;
  992. if (cs->debug & L1_DEB_ISAC)
  993. debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count);
  994. } else
  995. val = 0;
  996. }
  997. spin_unlock_irqrestore(&cs->lock, flags);
  998. return IRQ_HANDLED;
  999. }
  1000. /********************************************************************/
  1001. /* timer callback for D-chan busy resolution. Currently no function */
  1002. /********************************************************************/
  1003. static void
  1004. hfcpci_dbusy_timer(struct IsdnCardState *cs)
  1005. {
  1006. }
  1007. /*************************************/
  1008. /* Layer 1 D-channel hardware access */
  1009. /*************************************/
  1010. static void
  1011. HFCPCI_l1hw(struct PStack *st, int pr, void *arg)
  1012. {
  1013. u_long flags;
  1014. struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
  1015. struct sk_buff *skb = arg;
  1016. switch (pr) {
  1017. case (PH_DATA | REQUEST):
  1018. if (cs->debug & DEB_DLOG_HEX)
  1019. LogFrame(cs, skb->data, skb->len);
  1020. if (cs->debug & DEB_DLOG_VERBOSE)
  1021. dlogframe(cs, skb, 0);
  1022. spin_lock_irqsave(&cs->lock, flags);
  1023. if (cs->tx_skb) {
  1024. skb_queue_tail(&cs->sq, skb);
  1025. #ifdef L2FRAME_DEBUG /* psa */
  1026. if (cs->debug & L1_DEB_LAPD)
  1027. Logl2Frame(cs, skb, "PH_DATA Queued", 0);
  1028. #endif
  1029. } else {
  1030. cs->tx_skb = skb;
  1031. cs->tx_cnt = 0;
  1032. #ifdef L2FRAME_DEBUG /* psa */
  1033. if (cs->debug & L1_DEB_LAPD)
  1034. Logl2Frame(cs, skb, "PH_DATA", 0);
  1035. #endif
  1036. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  1037. hfcpci_fill_dfifo(cs);
  1038. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  1039. } else
  1040. debugl1(cs, "hfcpci_fill_dfifo blocked");
  1041. }
  1042. spin_unlock_irqrestore(&cs->lock, flags);
  1043. break;
  1044. case (PH_PULL | INDICATION):
  1045. spin_lock_irqsave(&cs->lock, flags);
  1046. if (cs->tx_skb) {
  1047. if (cs->debug & L1_DEB_WARN)
  1048. debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
  1049. skb_queue_tail(&cs->sq, skb);
  1050. spin_unlock_irqrestore(&cs->lock, flags);
  1051. break;
  1052. }
  1053. if (cs->debug & DEB_DLOG_HEX)
  1054. LogFrame(cs, skb->data, skb->len);
  1055. if (cs->debug & DEB_DLOG_VERBOSE)
  1056. dlogframe(cs, skb, 0);
  1057. cs->tx_skb = skb;
  1058. cs->tx_cnt = 0;
  1059. #ifdef L2FRAME_DEBUG /* psa */
  1060. if (cs->debug & L1_DEB_LAPD)
  1061. Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
  1062. #endif
  1063. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  1064. hfcpci_fill_dfifo(cs);
  1065. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  1066. } else
  1067. debugl1(cs, "hfcpci_fill_dfifo blocked");
  1068. spin_unlock_irqrestore(&cs->lock, flags);
  1069. break;
  1070. case (PH_PULL | REQUEST):
  1071. #ifdef L2FRAME_DEBUG /* psa */
  1072. if (cs->debug & L1_DEB_LAPD)
  1073. debugl1(cs, "-> PH_REQUEST_PULL");
  1074. #endif
  1075. if (!cs->tx_skb) {
  1076. test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1077. st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
  1078. } else
  1079. test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1080. break;
  1081. case (HW_RESET | REQUEST):
  1082. spin_lock_irqsave(&cs->lock, flags);
  1083. Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */
  1084. udelay(6);
  1085. Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */
  1086. cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
  1087. Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
  1088. Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
  1089. spin_unlock_irqrestore(&cs->lock, flags);
  1090. l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
  1091. break;
  1092. case (HW_ENABLE | REQUEST):
  1093. spin_lock_irqsave(&cs->lock, flags);
  1094. Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION);
  1095. spin_unlock_irqrestore(&cs->lock, flags);
  1096. break;
  1097. case (HW_DEACTIVATE | REQUEST):
  1098. spin_lock_irqsave(&cs->lock, flags);
  1099. cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
  1100. Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
  1101. spin_unlock_irqrestore(&cs->lock, flags);
  1102. break;
  1103. case (HW_INFO3 | REQUEST):
  1104. spin_lock_irqsave(&cs->lock, flags);
  1105. cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
  1106. Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
  1107. spin_unlock_irqrestore(&cs->lock, flags);
  1108. break;
  1109. case (HW_TESTLOOP | REQUEST):
  1110. spin_lock_irqsave(&cs->lock, flags);
  1111. switch ((long) arg) {
  1112. case (1):
  1113. Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */
  1114. Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */
  1115. cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
  1116. Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
  1117. break;
  1118. case (2):
  1119. Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */
  1120. Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */
  1121. cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
  1122. Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
  1123. break;
  1124. default:
  1125. spin_unlock_irqrestore(&cs->lock, flags);
  1126. if (cs->debug & L1_DEB_WARN)
  1127. debugl1(cs, "hfcpci_l1hw loop invalid %4lx", (long) arg);
  1128. return;
  1129. }
  1130. cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */
  1131. Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
  1132. spin_unlock_irqrestore(&cs->lock, flags);
  1133. break;
  1134. default:
  1135. if (cs->debug & L1_DEB_WARN)
  1136. debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
  1137. break;
  1138. }
  1139. }
  1140. /***********************************************/
  1141. /* called during init setting l1 stack pointer */
  1142. /***********************************************/
  1143. static void
  1144. setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs)
  1145. {
  1146. st->l1.l1hw = HFCPCI_l1hw;
  1147. }
  1148. /**************************************/
  1149. /* send B-channel data if not blocked */
  1150. /**************************************/
  1151. static void
  1152. hfcpci_send_data(struct BCState *bcs)
  1153. {
  1154. struct IsdnCardState *cs = bcs->cs;
  1155. if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
  1156. hfcpci_fill_fifo(bcs);
  1157. test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
  1158. } else
  1159. debugl1(cs, "send_data %d blocked", bcs->channel);
  1160. }
  1161. /***************************************************************/
  1162. /* activate/deactivate hardware for selected channels and mode */
  1163. /***************************************************************/
  1164. static void
  1165. mode_hfcpci(struct BCState *bcs, int mode, int bc)
  1166. {
  1167. struct IsdnCardState *cs = bcs->cs;
  1168. int fifo2;
  1169. if (cs->debug & L1_DEB_HSCX)
  1170. debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d",
  1171. mode, bc, bcs->channel);
  1172. bcs->mode = mode;
  1173. bcs->channel = bc;
  1174. fifo2 = bc;
  1175. if (cs->chanlimit > 1) {
  1176. cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
  1177. cs->hw.hfcpci.sctrl_e &= ~0x80;
  1178. } else {
  1179. if (bc) {
  1180. if (mode != L1_MODE_NULL) {
  1181. cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */
  1182. cs->hw.hfcpci.sctrl_e |= 0x80;
  1183. } else {
  1184. cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
  1185. cs->hw.hfcpci.sctrl_e &= ~0x80;
  1186. }
  1187. fifo2 = 0;
  1188. } else {
  1189. cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
  1190. cs->hw.hfcpci.sctrl_e &= ~0x80;
  1191. }
  1192. }
  1193. switch (mode) {
  1194. case (L1_MODE_NULL):
  1195. if (bc) {
  1196. cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
  1197. cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
  1198. } else {
  1199. cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
  1200. cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
  1201. }
  1202. if (fifo2) {
  1203. cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
  1204. cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
  1205. } else {
  1206. cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
  1207. cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
  1208. }
  1209. break;
  1210. case (L1_MODE_TRANS):
  1211. hfcpci_clear_fifo_rx(cs, fifo2);
  1212. hfcpci_clear_fifo_tx(cs, fifo2);
  1213. if (bc) {
  1214. cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
  1215. cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
  1216. } else {
  1217. cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
  1218. cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
  1219. }
  1220. if (fifo2) {
  1221. cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
  1222. cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
  1223. cs->hw.hfcpci.ctmt |= 2;
  1224. cs->hw.hfcpci.conn &= ~0x18;
  1225. } else {
  1226. cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
  1227. cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
  1228. cs->hw.hfcpci.ctmt |= 1;
  1229. cs->hw.hfcpci.conn &= ~0x03;
  1230. }
  1231. break;
  1232. case (L1_MODE_HDLC):
  1233. hfcpci_clear_fifo_rx(cs, fifo2);
  1234. hfcpci_clear_fifo_tx(cs, fifo2);
  1235. if (bc) {
  1236. cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
  1237. cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
  1238. } else {
  1239. cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
  1240. cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
  1241. }
  1242. if (fifo2) {
  1243. cs->hw.hfcpci.last_bfifo_cnt[1] = 0;
  1244. cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
  1245. cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
  1246. cs->hw.hfcpci.ctmt &= ~2;
  1247. cs->hw.hfcpci.conn &= ~0x18;
  1248. } else {
  1249. cs->hw.hfcpci.last_bfifo_cnt[0] = 0;
  1250. cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
  1251. cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
  1252. cs->hw.hfcpci.ctmt &= ~1;
  1253. cs->hw.hfcpci.conn &= ~0x03;
  1254. }
  1255. break;
  1256. case (L1_MODE_EXTRN):
  1257. if (bc) {
  1258. cs->hw.hfcpci.conn |= 0x10;
  1259. cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
  1260. cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
  1261. cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
  1262. cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
  1263. } else {
  1264. cs->hw.hfcpci.conn |= 0x02;
  1265. cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
  1266. cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
  1267. cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
  1268. cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
  1269. }
  1270. break;
  1271. }
  1272. Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
  1273. Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
  1274. Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
  1275. Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
  1276. Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
  1277. Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
  1278. Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
  1279. }
  1280. /******************************/
  1281. /* Layer2 -> Layer 1 Transfer */
  1282. /******************************/
  1283. static void
  1284. hfcpci_l2l1(struct PStack *st, int pr, void *arg)
  1285. {
  1286. struct BCState *bcs = st->l1.bcs;
  1287. u_long flags;
  1288. struct sk_buff *skb = arg;
  1289. switch (pr) {
  1290. case (PH_DATA | REQUEST):
  1291. spin_lock_irqsave(&bcs->cs->lock, flags);
  1292. if (bcs->tx_skb) {
  1293. skb_queue_tail(&bcs->squeue, skb);
  1294. } else {
  1295. bcs->tx_skb = skb;
  1296. // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  1297. bcs->cs->BC_Send_Data(bcs);
  1298. }
  1299. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1300. break;
  1301. case (PH_PULL | INDICATION):
  1302. spin_lock_irqsave(&bcs->cs->lock, flags);
  1303. if (bcs->tx_skb) {
  1304. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1305. printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
  1306. break;
  1307. }
  1308. // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  1309. bcs->tx_skb = skb;
  1310. bcs->cs->BC_Send_Data(bcs);
  1311. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1312. break;
  1313. case (PH_PULL | REQUEST):
  1314. if (!bcs->tx_skb) {
  1315. test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1316. st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
  1317. } else
  1318. test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1319. break;
  1320. case (PH_ACTIVATE | REQUEST):
  1321. spin_lock_irqsave(&bcs->cs->lock, flags);
  1322. test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
  1323. mode_hfcpci(bcs, st->l1.mode, st->l1.bc);
  1324. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1325. l1_msg_b(st, pr, arg);
  1326. break;
  1327. case (PH_DEACTIVATE | REQUEST):
  1328. l1_msg_b(st, pr, arg);
  1329. break;
  1330. case (PH_DEACTIVATE | CONFIRM):
  1331. spin_lock_irqsave(&bcs->cs->lock, flags);
  1332. test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
  1333. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1334. mode_hfcpci(bcs, 0, st->l1.bc);
  1335. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1336. st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
  1337. break;
  1338. }
  1339. }
  1340. /******************************************/
  1341. /* deactivate B-channel access and queues */
  1342. /******************************************/
  1343. static void
  1344. close_hfcpci(struct BCState *bcs)
  1345. {
  1346. mode_hfcpci(bcs, 0, bcs->channel);
  1347. if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
  1348. skb_queue_purge(&bcs->rqueue);
  1349. skb_queue_purge(&bcs->squeue);
  1350. if (bcs->tx_skb) {
  1351. dev_kfree_skb_any(bcs->tx_skb);
  1352. bcs->tx_skb = NULL;
  1353. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1354. }
  1355. }
  1356. }
  1357. /*************************************/
  1358. /* init B-channel queues and control */
  1359. /*************************************/
  1360. static int
  1361. open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs)
  1362. {
  1363. if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
  1364. skb_queue_head_init(&bcs->rqueue);
  1365. skb_queue_head_init(&bcs->squeue);
  1366. }
  1367. bcs->tx_skb = NULL;
  1368. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1369. bcs->event = 0;
  1370. bcs->tx_cnt = 0;
  1371. return (0);
  1372. }
  1373. /*********************************/
  1374. /* inits the stack for B-channel */
  1375. /*********************************/
  1376. static int
  1377. setstack_2b(struct PStack *st, struct BCState *bcs)
  1378. {
  1379. bcs->channel = st->l1.bc;
  1380. if (open_hfcpcistate(st->l1.hardware, bcs))
  1381. return (-1);
  1382. st->l1.bcs = bcs;
  1383. st->l2.l2l1 = hfcpci_l2l1;
  1384. setstack_manager(st);
  1385. bcs->st = st;
  1386. setstack_l1_B(st);
  1387. return (0);
  1388. }
  1389. /***************************/
  1390. /* handle L1 state changes */
  1391. /***************************/
  1392. static void
  1393. hfcpci_bh(struct work_struct *work)
  1394. {
  1395. struct IsdnCardState *cs =
  1396. container_of(work, struct IsdnCardState, tqueue);
  1397. u_long flags;
  1398. // struct PStack *stptr;
  1399. if (!cs)
  1400. return;
  1401. if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
  1402. if (!cs->hw.hfcpci.nt_mode)
  1403. switch (cs->dc.hfcpci.ph_state) {
  1404. case (0):
  1405. l1_msg(cs, HW_RESET | INDICATION, NULL);
  1406. break;
  1407. case (3):
  1408. l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
  1409. break;
  1410. case (8):
  1411. l1_msg(cs, HW_RSYNC | INDICATION, NULL);
  1412. break;
  1413. case (6):
  1414. l1_msg(cs, HW_INFO2 | INDICATION, NULL);
  1415. break;
  1416. case (7):
  1417. l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
  1418. break;
  1419. default:
  1420. break;
  1421. } else {
  1422. spin_lock_irqsave(&cs->lock, flags);
  1423. switch (cs->dc.hfcpci.ph_state) {
  1424. case (2):
  1425. if (cs->hw.hfcpci.nt_timer < 0) {
  1426. cs->hw.hfcpci.nt_timer = 0;
  1427. cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
  1428. Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
  1429. /* Clear already pending ints */
  1430. if (Read_hfc(cs, HFCPCI_INT_S1));
  1431. Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
  1432. udelay(10);
  1433. Write_hfc(cs, HFCPCI_STATES, 4);
  1434. cs->dc.hfcpci.ph_state = 4;
  1435. } else {
  1436. cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
  1437. Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
  1438. cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
  1439. cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
  1440. Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
  1441. Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
  1442. cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
  1443. Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */
  1444. }
  1445. break;
  1446. case (1):
  1447. case (3):
  1448. case (4):
  1449. cs->hw.hfcpci.nt_timer = 0;
  1450. cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
  1451. Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
  1452. break;
  1453. default:
  1454. break;
  1455. }
  1456. spin_unlock_irqrestore(&cs->lock, flags);
  1457. }
  1458. }
  1459. if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
  1460. DChannel_proc_rcv(cs);
  1461. if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
  1462. DChannel_proc_xmt(cs);
  1463. }
  1464. /********************************/
  1465. /* called for card init message */
  1466. /********************************/
  1467. static void
  1468. inithfcpci(struct IsdnCardState *cs)
  1469. {
  1470. cs->bcs[0].BC_SetStack = setstack_2b;
  1471. cs->bcs[1].BC_SetStack = setstack_2b;
  1472. cs->bcs[0].BC_Close = close_hfcpci;
  1473. cs->bcs[1].BC_Close = close_hfcpci;
  1474. cs->dbusytimer.function = (void *) hfcpci_dbusy_timer;
  1475. cs->dbusytimer.data = (long) cs;
  1476. init_timer(&cs->dbusytimer);
  1477. mode_hfcpci(cs->bcs, 0, 0);
  1478. mode_hfcpci(cs->bcs + 1, 0, 1);
  1479. }
  1480. /*******************************************/
  1481. /* handle card messages from control layer */
  1482. /*******************************************/
  1483. static int
  1484. hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg)
  1485. {
  1486. u_long flags;
  1487. if (cs->debug & L1_DEB_ISAC)
  1488. debugl1(cs, "HFCPCI: card_msg %x", mt);
  1489. switch (mt) {
  1490. case CARD_RESET:
  1491. spin_lock_irqsave(&cs->lock, flags);
  1492. reset_hfcpci(cs);
  1493. spin_unlock_irqrestore(&cs->lock, flags);
  1494. return (0);
  1495. case CARD_RELEASE:
  1496. release_io_hfcpci(cs);
  1497. return (0);
  1498. case CARD_INIT:
  1499. spin_lock_irqsave(&cs->lock, flags);
  1500. inithfcpci(cs);
  1501. reset_hfcpci(cs);
  1502. spin_unlock_irqrestore(&cs->lock, flags);
  1503. msleep(80); /* Timeout 80ms */
  1504. /* now switch timer interrupt off */
  1505. spin_lock_irqsave(&cs->lock, flags);
  1506. cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
  1507. Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
  1508. /* reinit mode reg */
  1509. Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
  1510. spin_unlock_irqrestore(&cs->lock, flags);
  1511. return (0);
  1512. case CARD_TEST:
  1513. return (0);
  1514. }
  1515. return (0);
  1516. }
  1517. /* this variable is used as card index when more than one cards are present */
  1518. static struct pci_dev *dev_hfcpci __devinitdata = NULL;
  1519. int __devinit
  1520. setup_hfcpci(struct IsdnCard *card)
  1521. {
  1522. u_long flags;
  1523. struct IsdnCardState *cs = card->cs;
  1524. char tmp[64];
  1525. int i;
  1526. struct pci_dev *tmp_hfcpci = NULL;
  1527. #ifdef __BIG_ENDIAN
  1528. #error "not running on big endian machines now"
  1529. #endif
  1530. strcpy(tmp, hfcpci_revision);
  1531. printk(KERN_INFO "HiSax: HFC-PCI driver Rev. %s\n", HiSax_getrev(tmp));
  1532. cs->hw.hfcpci.int_s1 = 0;
  1533. cs->dc.hfcpci.ph_state = 0;
  1534. cs->hw.hfcpci.fifo = 255;
  1535. if (cs->typ != ISDN_CTYPE_HFC_PCI)
  1536. return(0);
  1537. i = 0;
  1538. while (id_list[i].vendor_id) {
  1539. tmp_hfcpci = pci_find_device(id_list[i].vendor_id,
  1540. id_list[i].device_id,
  1541. dev_hfcpci);
  1542. i++;
  1543. if (tmp_hfcpci) {
  1544. dma_addr_t dma_mask = DMA_BIT_MASK(32) & ~0x7fffUL;
  1545. if (pci_enable_device(tmp_hfcpci))
  1546. continue;
  1547. if (pci_set_dma_mask(tmp_hfcpci, dma_mask)) {
  1548. printk(KERN_WARNING
  1549. "HiSax hfc_pci: No suitable DMA available.\n");
  1550. continue;
  1551. }
  1552. if (pci_set_consistent_dma_mask(tmp_hfcpci, dma_mask)) {
  1553. printk(KERN_WARNING
  1554. "HiSax hfc_pci: No suitable consistent DMA available.\n");
  1555. continue;
  1556. }
  1557. pci_set_master(tmp_hfcpci);
  1558. if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK)))
  1559. continue;
  1560. else
  1561. break;
  1562. }
  1563. }
  1564. if (!tmp_hfcpci) {
  1565. printk(KERN_WARNING "HFC-PCI: No PCI card found\n");
  1566. return (0);
  1567. }
  1568. i--;
  1569. dev_hfcpci = tmp_hfcpci; /* old device */
  1570. cs->hw.hfcpci.dev = dev_hfcpci;
  1571. cs->irq = dev_hfcpci->irq;
  1572. if (!cs->irq) {
  1573. printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
  1574. return (0);
  1575. }
  1576. cs->hw.hfcpci.pci_io = (char *)(unsigned long)dev_hfcpci->resource[1].start;
  1577. printk(KERN_INFO "HiSax: HFC-PCI card manufacturer: %s card name: %s\n", id_list[i].vendor_name, id_list[i].card_name);
  1578. if (!cs->hw.hfcpci.pci_io) {
  1579. printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
  1580. return (0);
  1581. }
  1582. /* Allocate memory for FIFOS */
  1583. cs->hw.hfcpci.fifos = pci_alloc_consistent(cs->hw.hfcpci.dev,
  1584. 0x8000, &cs->hw.hfcpci.dma);
  1585. if (!cs->hw.hfcpci.fifos) {
  1586. printk(KERN_WARNING "HFC-PCI: Error allocating FIFO memory!\n");
  1587. return 0;
  1588. }
  1589. if (cs->hw.hfcpci.dma & 0x7fff) {
  1590. printk(KERN_WARNING
  1591. "HFC-PCI: Error DMA memory not on 32K boundary (%lx)\n",
  1592. (u_long)cs->hw.hfcpci.dma);
  1593. pci_free_consistent(cs->hw.hfcpci.dev, 0x8000,
  1594. cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma);
  1595. return 0;
  1596. }
  1597. pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u32)cs->hw.hfcpci.dma);
  1598. cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256);
  1599. printk(KERN_INFO
  1600. "HFC-PCI: defined at mem %p fifo %p(%lx) IRQ %d HZ %d\n",
  1601. cs->hw.hfcpci.pci_io,
  1602. cs->hw.hfcpci.fifos,
  1603. (u_long)cs->hw.hfcpci.dma,
  1604. cs->irq, HZ);
  1605. spin_lock_irqsave(&cs->lock, flags);
  1606. pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
  1607. cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */
  1608. cs->hw.hfcpci.int_m1 = 0;
  1609. Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
  1610. Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
  1611. /* At this point the needed PCI config is done */
  1612. /* fifos are still not enabled */
  1613. INIT_WORK(&cs->tqueue, hfcpci_bh);
  1614. cs->setstack_d = setstack_hfcpci;
  1615. cs->BC_Send_Data = &hfcpci_send_data;
  1616. cs->readisac = NULL;
  1617. cs->writeisac = NULL;
  1618. cs->readisacfifo = NULL;
  1619. cs->writeisacfifo = NULL;
  1620. cs->BC_Read_Reg = NULL;
  1621. cs->BC_Write_Reg = NULL;
  1622. cs->irq_func = &hfcpci_interrupt;
  1623. cs->irq_flags |= IRQF_SHARED;
  1624. cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer;
  1625. cs->hw.hfcpci.timer.data = (long) cs;
  1626. init_timer(&cs->hw.hfcpci.timer);
  1627. cs->cardmsg = &hfcpci_card_msg;
  1628. cs->auxcmd = &hfcpci_auxcmd;
  1629. spin_unlock_irqrestore(&cs->lock, flags);
  1630. return (1);
  1631. }