intel_sdvo.c 57 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/delay.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "drm_crtc.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include "intel_sdvo_regs.h"
  37. #undef SDVO_DEBUG
  38. #define I915_SDVO "i915_sdvo"
  39. struct intel_sdvo_priv {
  40. struct intel_i2c_chan *i2c_bus;
  41. int slaveaddr;
  42. /* Register for the SDVO device: SDVOB or SDVOC */
  43. int output_device;
  44. /* Active outputs controlled by this SDVO output */
  45. uint16_t controlled_output;
  46. /*
  47. * Capabilities of the SDVO device returned by
  48. * i830_sdvo_get_capabilities()
  49. */
  50. struct intel_sdvo_caps caps;
  51. /* Pixel clock limitations reported by the SDVO device, in kHz */
  52. int pixel_clock_min, pixel_clock_max;
  53. /**
  54. * This is set if we're going to treat the device as TV-out.
  55. *
  56. * While we have these nice friendly flags for output types that ought
  57. * to decide this for us, the S-Video output on our HDMI+S-Video card
  58. * shows up as RGB1 (VGA).
  59. */
  60. bool is_tv;
  61. /**
  62. * This is set if we treat the device as HDMI, instead of DVI.
  63. */
  64. bool is_hdmi;
  65. /**
  66. * This is set if we detect output of sdvo device as LVDS.
  67. */
  68. bool is_lvds;
  69. /**
  70. * Returned SDTV resolutions allowed for the current format, if the
  71. * device reported it.
  72. */
  73. struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
  74. /**
  75. * Current selected TV format.
  76. *
  77. * This is stored in the same structure that's passed to the device, for
  78. * convenience.
  79. */
  80. struct intel_sdvo_tv_format tv_format;
  81. /*
  82. * supported encoding mode, used to determine whether HDMI is
  83. * supported
  84. */
  85. struct intel_sdvo_encode encode;
  86. /* DDC bus used by this SDVO output */
  87. uint8_t ddc_bus;
  88. int save_sdvo_mult;
  89. u16 save_active_outputs;
  90. struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
  91. struct intel_sdvo_dtd save_output_dtd[16];
  92. u32 save_SDVOX;
  93. };
  94. /**
  95. * Writes the SDVOB or SDVOC with the given value, but always writes both
  96. * SDVOB and SDVOC to work around apparent hardware issues (according to
  97. * comments in the BIOS).
  98. */
  99. static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
  100. {
  101. struct drm_device *dev = intel_output->base.dev;
  102. struct drm_i915_private *dev_priv = dev->dev_private;
  103. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  104. u32 bval = val, cval = val;
  105. int i;
  106. if (sdvo_priv->output_device == SDVOB) {
  107. cval = I915_READ(SDVOC);
  108. } else {
  109. bval = I915_READ(SDVOB);
  110. }
  111. /*
  112. * Write the registers twice for luck. Sometimes,
  113. * writing them only once doesn't appear to 'stick'.
  114. * The BIOS does this too. Yay, magic
  115. */
  116. for (i = 0; i < 2; i++)
  117. {
  118. I915_WRITE(SDVOB, bval);
  119. I915_READ(SDVOB);
  120. I915_WRITE(SDVOC, cval);
  121. I915_READ(SDVOC);
  122. }
  123. }
  124. static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
  125. u8 *ch)
  126. {
  127. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  128. u8 out_buf[2];
  129. u8 buf[2];
  130. int ret;
  131. struct i2c_msg msgs[] = {
  132. {
  133. .addr = sdvo_priv->i2c_bus->slave_addr,
  134. .flags = 0,
  135. .len = 1,
  136. .buf = out_buf,
  137. },
  138. {
  139. .addr = sdvo_priv->i2c_bus->slave_addr,
  140. .flags = I2C_M_RD,
  141. .len = 1,
  142. .buf = buf,
  143. }
  144. };
  145. out_buf[0] = addr;
  146. out_buf[1] = 0;
  147. if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
  148. {
  149. *ch = buf[0];
  150. return true;
  151. }
  152. DRM_DEBUG("i2c transfer returned %d\n", ret);
  153. return false;
  154. }
  155. static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
  156. u8 ch)
  157. {
  158. u8 out_buf[2];
  159. struct i2c_msg msgs[] = {
  160. {
  161. .addr = intel_output->i2c_bus->slave_addr,
  162. .flags = 0,
  163. .len = 2,
  164. .buf = out_buf,
  165. }
  166. };
  167. out_buf[0] = addr;
  168. out_buf[1] = ch;
  169. if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
  170. {
  171. return true;
  172. }
  173. return false;
  174. }
  175. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  176. /** Mapping of command numbers to names, for debug output */
  177. static const struct _sdvo_cmd_name {
  178. u8 cmd;
  179. char *name;
  180. } sdvo_cmd_names[] = {
  181. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  182. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  183. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  184. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  185. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  186. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  187. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  188. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  189. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  190. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  191. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  192. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  193. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  194. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  195. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  196. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  197. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  198. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  199. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  200. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  201. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  202. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  203. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  204. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  205. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  206. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  207. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  208. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  209. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  210. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  211. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  212. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  213. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  214. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  215. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  216. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  217. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  218. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  219. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  220. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  221. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  222. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  223. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  224. /* HDMI op code */
  225. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  226. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  227. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  228. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  229. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  230. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  231. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  232. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  233. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  234. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  235. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  236. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  237. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  238. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  239. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  240. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  241. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  242. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  243. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  244. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  245. };
  246. #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
  247. #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
  248. #ifdef SDVO_DEBUG
  249. static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
  250. void *args, int args_len)
  251. {
  252. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  253. int i;
  254. DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ",
  255. SDVO_NAME(sdvo_priv), cmd);
  256. for (i = 0; i < args_len; i++)
  257. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  258. for (; i < 8; i++)
  259. DRM_LOG_KMS(" ");
  260. for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
  261. if (cmd == sdvo_cmd_names[i].cmd) {
  262. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  263. break;
  264. }
  265. }
  266. if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
  267. DRM_LOG_KMS("(%02X)", cmd);
  268. DRM_LOG_KMS("\n");
  269. }
  270. #else
  271. #define intel_sdvo_debug_write(o, c, a, l)
  272. #endif
  273. static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
  274. void *args, int args_len)
  275. {
  276. int i;
  277. intel_sdvo_debug_write(intel_output, cmd, args, args_len);
  278. for (i = 0; i < args_len; i++) {
  279. intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
  280. ((u8*)args)[i]);
  281. }
  282. intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
  283. }
  284. #ifdef SDVO_DEBUG
  285. static const char *cmd_status_names[] = {
  286. "Power on",
  287. "Success",
  288. "Not supported",
  289. "Invalid arg",
  290. "Pending",
  291. "Target not specified",
  292. "Scaling not supported"
  293. };
  294. static void intel_sdvo_debug_response(struct intel_output *intel_output,
  295. void *response, int response_len,
  296. u8 status)
  297. {
  298. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  299. int i;
  300. DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv));
  301. for (i = 0; i < response_len; i++)
  302. DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
  303. for (; i < 8; i++)
  304. DRM_LOG_KMS(" ");
  305. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  306. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  307. else
  308. DRM_LOG_KMS("(??? %d)", status);
  309. DRM_LOG_KMS("\n");
  310. }
  311. #else
  312. #define intel_sdvo_debug_response(o, r, l, s)
  313. #endif
  314. static u8 intel_sdvo_read_response(struct intel_output *intel_output,
  315. void *response, int response_len)
  316. {
  317. int i;
  318. u8 status;
  319. u8 retry = 50;
  320. while (retry--) {
  321. /* Read the command response */
  322. for (i = 0; i < response_len; i++) {
  323. intel_sdvo_read_byte(intel_output,
  324. SDVO_I2C_RETURN_0 + i,
  325. &((u8 *)response)[i]);
  326. }
  327. /* read the return status */
  328. intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
  329. &status);
  330. intel_sdvo_debug_response(intel_output, response, response_len,
  331. status);
  332. if (status != SDVO_CMD_STATUS_PENDING)
  333. return status;
  334. mdelay(50);
  335. }
  336. return status;
  337. }
  338. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  339. {
  340. if (mode->clock >= 100000)
  341. return 1;
  342. else if (mode->clock >= 50000)
  343. return 2;
  344. else
  345. return 4;
  346. }
  347. /**
  348. * Don't check status code from this as it switches the bus back to the
  349. * SDVO chips which defeats the purpose of doing a bus switch in the first
  350. * place.
  351. */
  352. static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
  353. u8 target)
  354. {
  355. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
  356. }
  357. static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
  358. {
  359. struct intel_sdvo_set_target_input_args targets = {0};
  360. u8 status;
  361. if (target_0 && target_1)
  362. return SDVO_CMD_STATUS_NOTSUPP;
  363. if (target_1)
  364. targets.target_1 = 1;
  365. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
  366. sizeof(targets));
  367. status = intel_sdvo_read_response(intel_output, NULL, 0);
  368. return (status == SDVO_CMD_STATUS_SUCCESS);
  369. }
  370. /**
  371. * Return whether each input is trained.
  372. *
  373. * This function is making an assumption about the layout of the response,
  374. * which should be checked against the docs.
  375. */
  376. static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
  377. {
  378. struct intel_sdvo_get_trained_inputs_response response;
  379. u8 status;
  380. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
  381. status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
  382. if (status != SDVO_CMD_STATUS_SUCCESS)
  383. return false;
  384. *input_1 = response.input0_trained;
  385. *input_2 = response.input1_trained;
  386. return true;
  387. }
  388. static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
  389. u16 *outputs)
  390. {
  391. u8 status;
  392. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
  393. status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
  394. return (status == SDVO_CMD_STATUS_SUCCESS);
  395. }
  396. static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
  397. u16 outputs)
  398. {
  399. u8 status;
  400. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
  401. sizeof(outputs));
  402. status = intel_sdvo_read_response(intel_output, NULL, 0);
  403. return (status == SDVO_CMD_STATUS_SUCCESS);
  404. }
  405. static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
  406. int mode)
  407. {
  408. u8 status, state = SDVO_ENCODER_STATE_ON;
  409. switch (mode) {
  410. case DRM_MODE_DPMS_ON:
  411. state = SDVO_ENCODER_STATE_ON;
  412. break;
  413. case DRM_MODE_DPMS_STANDBY:
  414. state = SDVO_ENCODER_STATE_STANDBY;
  415. break;
  416. case DRM_MODE_DPMS_SUSPEND:
  417. state = SDVO_ENCODER_STATE_SUSPEND;
  418. break;
  419. case DRM_MODE_DPMS_OFF:
  420. state = SDVO_ENCODER_STATE_OFF;
  421. break;
  422. }
  423. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
  424. sizeof(state));
  425. status = intel_sdvo_read_response(intel_output, NULL, 0);
  426. return (status == SDVO_CMD_STATUS_SUCCESS);
  427. }
  428. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
  429. int *clock_min,
  430. int *clock_max)
  431. {
  432. struct intel_sdvo_pixel_clock_range clocks;
  433. u8 status;
  434. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  435. NULL, 0);
  436. status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
  437. if (status != SDVO_CMD_STATUS_SUCCESS)
  438. return false;
  439. /* Convert the values from units of 10 kHz to kHz. */
  440. *clock_min = clocks.min * 10;
  441. *clock_max = clocks.max * 10;
  442. return true;
  443. }
  444. static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
  445. u16 outputs)
  446. {
  447. u8 status;
  448. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
  449. sizeof(outputs));
  450. status = intel_sdvo_read_response(intel_output, NULL, 0);
  451. return (status == SDVO_CMD_STATUS_SUCCESS);
  452. }
  453. static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
  454. struct intel_sdvo_dtd *dtd)
  455. {
  456. u8 status;
  457. intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
  458. status = intel_sdvo_read_response(intel_output, &dtd->part1,
  459. sizeof(dtd->part1));
  460. if (status != SDVO_CMD_STATUS_SUCCESS)
  461. return false;
  462. intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
  463. status = intel_sdvo_read_response(intel_output, &dtd->part2,
  464. sizeof(dtd->part2));
  465. if (status != SDVO_CMD_STATUS_SUCCESS)
  466. return false;
  467. return true;
  468. }
  469. static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
  470. struct intel_sdvo_dtd *dtd)
  471. {
  472. return intel_sdvo_get_timing(intel_output,
  473. SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
  474. }
  475. static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
  476. struct intel_sdvo_dtd *dtd)
  477. {
  478. return intel_sdvo_get_timing(intel_output,
  479. SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
  480. }
  481. static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
  482. struct intel_sdvo_dtd *dtd)
  483. {
  484. u8 status;
  485. intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
  486. status = intel_sdvo_read_response(intel_output, NULL, 0);
  487. if (status != SDVO_CMD_STATUS_SUCCESS)
  488. return false;
  489. intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  490. status = intel_sdvo_read_response(intel_output, NULL, 0);
  491. if (status != SDVO_CMD_STATUS_SUCCESS)
  492. return false;
  493. return true;
  494. }
  495. static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
  496. struct intel_sdvo_dtd *dtd)
  497. {
  498. return intel_sdvo_set_timing(intel_output,
  499. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  500. }
  501. static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
  502. struct intel_sdvo_dtd *dtd)
  503. {
  504. return intel_sdvo_set_timing(intel_output,
  505. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  506. }
  507. static bool
  508. intel_sdvo_create_preferred_input_timing(struct intel_output *output,
  509. uint16_t clock,
  510. uint16_t width,
  511. uint16_t height)
  512. {
  513. struct intel_sdvo_preferred_input_timing_args args;
  514. uint8_t status;
  515. memset(&args, 0, sizeof(args));
  516. args.clock = clock;
  517. args.width = width;
  518. args.height = height;
  519. args.interlace = 0;
  520. args.scaled = 0;
  521. intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  522. &args, sizeof(args));
  523. status = intel_sdvo_read_response(output, NULL, 0);
  524. if (status != SDVO_CMD_STATUS_SUCCESS)
  525. return false;
  526. return true;
  527. }
  528. static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
  529. struct intel_sdvo_dtd *dtd)
  530. {
  531. bool status;
  532. intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  533. NULL, 0);
  534. status = intel_sdvo_read_response(output, &dtd->part1,
  535. sizeof(dtd->part1));
  536. if (status != SDVO_CMD_STATUS_SUCCESS)
  537. return false;
  538. intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  539. NULL, 0);
  540. status = intel_sdvo_read_response(output, &dtd->part2,
  541. sizeof(dtd->part2));
  542. if (status != SDVO_CMD_STATUS_SUCCESS)
  543. return false;
  544. return false;
  545. }
  546. static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
  547. {
  548. u8 response, status;
  549. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
  550. status = intel_sdvo_read_response(intel_output, &response, 1);
  551. if (status != SDVO_CMD_STATUS_SUCCESS) {
  552. DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
  553. return SDVO_CLOCK_RATE_MULT_1X;
  554. } else {
  555. DRM_DEBUG("Current clock rate multiplier: %d\n", response);
  556. }
  557. return response;
  558. }
  559. static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
  560. {
  561. u8 status;
  562. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  563. status = intel_sdvo_read_response(intel_output, NULL, 0);
  564. if (status != SDVO_CMD_STATUS_SUCCESS)
  565. return false;
  566. return true;
  567. }
  568. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  569. struct drm_display_mode *mode)
  570. {
  571. uint16_t width, height;
  572. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  573. uint16_t h_sync_offset, v_sync_offset;
  574. width = mode->crtc_hdisplay;
  575. height = mode->crtc_vdisplay;
  576. /* do some mode translations */
  577. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  578. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  579. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  580. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  581. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  582. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  583. dtd->part1.clock = mode->clock / 10;
  584. dtd->part1.h_active = width & 0xff;
  585. dtd->part1.h_blank = h_blank_len & 0xff;
  586. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  587. ((h_blank_len >> 8) & 0xf);
  588. dtd->part1.v_active = height & 0xff;
  589. dtd->part1.v_blank = v_blank_len & 0xff;
  590. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  591. ((v_blank_len >> 8) & 0xf);
  592. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  593. dtd->part2.h_sync_width = h_sync_len & 0xff;
  594. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  595. (v_sync_len & 0xf);
  596. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  597. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  598. ((v_sync_len & 0x30) >> 4);
  599. dtd->part2.dtd_flags = 0x18;
  600. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  601. dtd->part2.dtd_flags |= 0x2;
  602. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  603. dtd->part2.dtd_flags |= 0x4;
  604. dtd->part2.sdvo_flags = 0;
  605. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  606. dtd->part2.reserved = 0;
  607. }
  608. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  609. struct intel_sdvo_dtd *dtd)
  610. {
  611. mode->hdisplay = dtd->part1.h_active;
  612. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  613. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  614. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  615. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  616. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  617. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  618. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  619. mode->vdisplay = dtd->part1.v_active;
  620. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  621. mode->vsync_start = mode->vdisplay;
  622. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  623. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  624. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  625. mode->vsync_end = mode->vsync_start +
  626. (dtd->part2.v_sync_off_width & 0xf);
  627. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  628. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  629. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  630. mode->clock = dtd->part1.clock * 10;
  631. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  632. if (dtd->part2.dtd_flags & 0x2)
  633. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  634. if (dtd->part2.dtd_flags & 0x4)
  635. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  636. }
  637. static bool intel_sdvo_get_supp_encode(struct intel_output *output,
  638. struct intel_sdvo_encode *encode)
  639. {
  640. uint8_t status;
  641. intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
  642. status = intel_sdvo_read_response(output, encode, sizeof(*encode));
  643. if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
  644. memset(encode, 0, sizeof(*encode));
  645. return false;
  646. }
  647. return true;
  648. }
  649. static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
  650. {
  651. uint8_t status;
  652. intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
  653. status = intel_sdvo_read_response(output, NULL, 0);
  654. return (status == SDVO_CMD_STATUS_SUCCESS);
  655. }
  656. static bool intel_sdvo_set_colorimetry(struct intel_output *output,
  657. uint8_t mode)
  658. {
  659. uint8_t status;
  660. intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  661. status = intel_sdvo_read_response(output, NULL, 0);
  662. return (status == SDVO_CMD_STATUS_SUCCESS);
  663. }
  664. #if 0
  665. static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
  666. {
  667. int i, j;
  668. uint8_t set_buf_index[2];
  669. uint8_t av_split;
  670. uint8_t buf_size;
  671. uint8_t buf[48];
  672. uint8_t *pos;
  673. intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
  674. intel_sdvo_read_response(output, &av_split, 1);
  675. for (i = 0; i <= av_split; i++) {
  676. set_buf_index[0] = i; set_buf_index[1] = 0;
  677. intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
  678. set_buf_index, 2);
  679. intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  680. intel_sdvo_read_response(output, &buf_size, 1);
  681. pos = buf;
  682. for (j = 0; j <= buf_size; j += 8) {
  683. intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
  684. NULL, 0);
  685. intel_sdvo_read_response(output, pos, 8);
  686. pos += 8;
  687. }
  688. }
  689. }
  690. #endif
  691. static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
  692. uint8_t *data, int8_t size, uint8_t tx_rate)
  693. {
  694. uint8_t set_buf_index[2];
  695. set_buf_index[0] = index;
  696. set_buf_index[1] = 0;
  697. intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
  698. for (; size > 0; size -= 8) {
  699. intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
  700. data += 8;
  701. }
  702. intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
  703. }
  704. static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
  705. {
  706. uint8_t csum = 0;
  707. int i;
  708. for (i = 0; i < size; i++)
  709. csum += data[i];
  710. return 0x100 - csum;
  711. }
  712. #define DIP_TYPE_AVI 0x82
  713. #define DIP_VERSION_AVI 0x2
  714. #define DIP_LEN_AVI 13
  715. struct dip_infoframe {
  716. uint8_t type;
  717. uint8_t version;
  718. uint8_t len;
  719. uint8_t checksum;
  720. union {
  721. struct {
  722. /* Packet Byte #1 */
  723. uint8_t S:2;
  724. uint8_t B:2;
  725. uint8_t A:1;
  726. uint8_t Y:2;
  727. uint8_t rsvd1:1;
  728. /* Packet Byte #2 */
  729. uint8_t R:4;
  730. uint8_t M:2;
  731. uint8_t C:2;
  732. /* Packet Byte #3 */
  733. uint8_t SC:2;
  734. uint8_t Q:2;
  735. uint8_t EC:3;
  736. uint8_t ITC:1;
  737. /* Packet Byte #4 */
  738. uint8_t VIC:7;
  739. uint8_t rsvd2:1;
  740. /* Packet Byte #5 */
  741. uint8_t PR:4;
  742. uint8_t rsvd3:4;
  743. /* Packet Byte #6~13 */
  744. uint16_t top_bar_end;
  745. uint16_t bottom_bar_start;
  746. uint16_t left_bar_end;
  747. uint16_t right_bar_start;
  748. } avi;
  749. struct {
  750. /* Packet Byte #1 */
  751. uint8_t channel_count:3;
  752. uint8_t rsvd1:1;
  753. uint8_t coding_type:4;
  754. /* Packet Byte #2 */
  755. uint8_t sample_size:2; /* SS0, SS1 */
  756. uint8_t sample_frequency:3;
  757. uint8_t rsvd2:3;
  758. /* Packet Byte #3 */
  759. uint8_t coding_type_private:5;
  760. uint8_t rsvd3:3;
  761. /* Packet Byte #4 */
  762. uint8_t channel_allocation;
  763. /* Packet Byte #5 */
  764. uint8_t rsvd4:3;
  765. uint8_t level_shift:4;
  766. uint8_t downmix_inhibit:1;
  767. } audio;
  768. uint8_t payload[28];
  769. } __attribute__ ((packed)) u;
  770. } __attribute__((packed));
  771. static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
  772. struct drm_display_mode * mode)
  773. {
  774. struct dip_infoframe avi_if = {
  775. .type = DIP_TYPE_AVI,
  776. .version = DIP_VERSION_AVI,
  777. .len = DIP_LEN_AVI,
  778. };
  779. avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
  780. 4 + avi_if.len);
  781. intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
  782. SDVO_HBUF_TX_VSYNC);
  783. }
  784. static void intel_sdvo_set_tv_format(struct intel_output *output)
  785. {
  786. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  787. struct intel_sdvo_tv_format *format, unset;
  788. u8 status;
  789. format = &sdvo_priv->tv_format;
  790. memset(&unset, 0, sizeof(unset));
  791. if (memcmp(format, &unset, sizeof(*format))) {
  792. DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
  793. SDVO_NAME(sdvo_priv));
  794. format->ntsc_m = 1;
  795. intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
  796. sizeof(*format));
  797. status = intel_sdvo_read_response(output, NULL, 0);
  798. if (status != SDVO_CMD_STATUS_SUCCESS)
  799. DRM_DEBUG("%s: Failed to set TV format\n",
  800. SDVO_NAME(sdvo_priv));
  801. }
  802. }
  803. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  804. struct drm_display_mode *mode,
  805. struct drm_display_mode *adjusted_mode)
  806. {
  807. struct intel_output *output = enc_to_intel_output(encoder);
  808. struct intel_sdvo_priv *dev_priv = output->dev_priv;
  809. if (!dev_priv->is_tv) {
  810. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  811. * SDVO device will be told of the multiplier during mode_set.
  812. */
  813. adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
  814. } else {
  815. struct intel_sdvo_dtd output_dtd;
  816. bool success;
  817. /* We need to construct preferred input timings based on our
  818. * output timings. To do that, we have to set the output
  819. * timings, even though this isn't really the right place in
  820. * the sequence to do it. Oh well.
  821. */
  822. /* Set output timings */
  823. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  824. intel_sdvo_set_target_output(output,
  825. dev_priv->controlled_output);
  826. intel_sdvo_set_output_timing(output, &output_dtd);
  827. /* Set the input timing to the screen. Assume always input 0. */
  828. intel_sdvo_set_target_input(output, true, false);
  829. success = intel_sdvo_create_preferred_input_timing(output,
  830. mode->clock / 10,
  831. mode->hdisplay,
  832. mode->vdisplay);
  833. if (success) {
  834. struct intel_sdvo_dtd input_dtd;
  835. intel_sdvo_get_preferred_input_timing(output,
  836. &input_dtd);
  837. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  838. drm_mode_set_crtcinfo(adjusted_mode, 0);
  839. mode->clock = adjusted_mode->clock;
  840. adjusted_mode->clock *=
  841. intel_sdvo_get_pixel_multiplier(mode);
  842. } else {
  843. return false;
  844. }
  845. }
  846. return true;
  847. }
  848. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  849. struct drm_display_mode *mode,
  850. struct drm_display_mode *adjusted_mode)
  851. {
  852. struct drm_device *dev = encoder->dev;
  853. struct drm_i915_private *dev_priv = dev->dev_private;
  854. struct drm_crtc *crtc = encoder->crtc;
  855. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  856. struct intel_output *output = enc_to_intel_output(encoder);
  857. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  858. u32 sdvox = 0;
  859. int sdvo_pixel_multiply;
  860. struct intel_sdvo_in_out_map in_out;
  861. struct intel_sdvo_dtd input_dtd;
  862. u8 status;
  863. if (!mode)
  864. return;
  865. /* First, set the input mapping for the first input to our controlled
  866. * output. This is only correct if we're a single-input device, in
  867. * which case the first input is the output from the appropriate SDVO
  868. * channel on the motherboard. In a two-input device, the first input
  869. * will be SDVOB and the second SDVOC.
  870. */
  871. in_out.in0 = sdvo_priv->controlled_output;
  872. in_out.in1 = 0;
  873. intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
  874. &in_out, sizeof(in_out));
  875. status = intel_sdvo_read_response(output, NULL, 0);
  876. if (sdvo_priv->is_hdmi) {
  877. intel_sdvo_set_avi_infoframe(output, mode);
  878. sdvox |= SDVO_AUDIO_ENABLE;
  879. }
  880. /* We have tried to get input timing in mode_fixup, and filled into
  881. adjusted_mode */
  882. if (sdvo_priv->is_tv)
  883. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  884. else
  885. intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
  886. /* If it's a TV, we already set the output timing in mode_fixup.
  887. * Otherwise, the output timing is equal to the input timing.
  888. */
  889. if (!sdvo_priv->is_tv) {
  890. /* Set the output timing to the screen */
  891. intel_sdvo_set_target_output(output,
  892. sdvo_priv->controlled_output);
  893. intel_sdvo_set_output_timing(output, &input_dtd);
  894. }
  895. /* Set the input timing to the screen. Assume always input 0. */
  896. intel_sdvo_set_target_input(output, true, false);
  897. if (sdvo_priv->is_tv)
  898. intel_sdvo_set_tv_format(output);
  899. /* We would like to use intel_sdvo_create_preferred_input_timing() to
  900. * provide the device with a timing it can support, if it supports that
  901. * feature. However, presumably we would need to adjust the CRTC to
  902. * output the preferred timing, and we don't support that currently.
  903. */
  904. #if 0
  905. success = intel_sdvo_create_preferred_input_timing(output, clock,
  906. width, height);
  907. if (success) {
  908. struct intel_sdvo_dtd *input_dtd;
  909. intel_sdvo_get_preferred_input_timing(output, &input_dtd);
  910. intel_sdvo_set_input_timing(output, &input_dtd);
  911. }
  912. #else
  913. intel_sdvo_set_input_timing(output, &input_dtd);
  914. #endif
  915. switch (intel_sdvo_get_pixel_multiplier(mode)) {
  916. case 1:
  917. intel_sdvo_set_clock_rate_mult(output,
  918. SDVO_CLOCK_RATE_MULT_1X);
  919. break;
  920. case 2:
  921. intel_sdvo_set_clock_rate_mult(output,
  922. SDVO_CLOCK_RATE_MULT_2X);
  923. break;
  924. case 4:
  925. intel_sdvo_set_clock_rate_mult(output,
  926. SDVO_CLOCK_RATE_MULT_4X);
  927. break;
  928. }
  929. /* Set the SDVO control regs. */
  930. if (IS_I965G(dev)) {
  931. sdvox |= SDVO_BORDER_ENABLE |
  932. SDVO_VSYNC_ACTIVE_HIGH |
  933. SDVO_HSYNC_ACTIVE_HIGH;
  934. } else {
  935. sdvox |= I915_READ(sdvo_priv->output_device);
  936. switch (sdvo_priv->output_device) {
  937. case SDVOB:
  938. sdvox &= SDVOB_PRESERVE_MASK;
  939. break;
  940. case SDVOC:
  941. sdvox &= SDVOC_PRESERVE_MASK;
  942. break;
  943. }
  944. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  945. }
  946. if (intel_crtc->pipe == 1)
  947. sdvox |= SDVO_PIPE_B_SELECT;
  948. sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
  949. if (IS_I965G(dev)) {
  950. /* done in crtc_mode_set as the dpll_md reg must be written early */
  951. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  952. /* done in crtc_mode_set as it lives inside the dpll register */
  953. } else {
  954. sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  955. }
  956. intel_sdvo_write_sdvox(output, sdvox);
  957. }
  958. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  959. {
  960. struct drm_device *dev = encoder->dev;
  961. struct drm_i915_private *dev_priv = dev->dev_private;
  962. struct intel_output *intel_output = enc_to_intel_output(encoder);
  963. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  964. u32 temp;
  965. if (mode != DRM_MODE_DPMS_ON) {
  966. intel_sdvo_set_active_outputs(intel_output, 0);
  967. if (0)
  968. intel_sdvo_set_encoder_power_state(intel_output, mode);
  969. if (mode == DRM_MODE_DPMS_OFF) {
  970. temp = I915_READ(sdvo_priv->output_device);
  971. if ((temp & SDVO_ENABLE) != 0) {
  972. intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
  973. }
  974. }
  975. } else {
  976. bool input1, input2;
  977. int i;
  978. u8 status;
  979. temp = I915_READ(sdvo_priv->output_device);
  980. if ((temp & SDVO_ENABLE) == 0)
  981. intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
  982. for (i = 0; i < 2; i++)
  983. intel_wait_for_vblank(dev);
  984. status = intel_sdvo_get_trained_inputs(intel_output, &input1,
  985. &input2);
  986. /* Warn if the device reported failure to sync.
  987. * A lot of SDVO devices fail to notify of sync, but it's
  988. * a given it the status is a success, we succeeded.
  989. */
  990. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  991. DRM_DEBUG("First %s output reported failure to sync\n",
  992. SDVO_NAME(sdvo_priv));
  993. }
  994. if (0)
  995. intel_sdvo_set_encoder_power_state(intel_output, mode);
  996. intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
  997. }
  998. return;
  999. }
  1000. static void intel_sdvo_save(struct drm_connector *connector)
  1001. {
  1002. struct drm_device *dev = connector->dev;
  1003. struct drm_i915_private *dev_priv = dev->dev_private;
  1004. struct intel_output *intel_output = to_intel_output(connector);
  1005. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1006. int o;
  1007. sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
  1008. intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
  1009. if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
  1010. intel_sdvo_set_target_input(intel_output, true, false);
  1011. intel_sdvo_get_input_timing(intel_output,
  1012. &sdvo_priv->save_input_dtd_1);
  1013. }
  1014. if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
  1015. intel_sdvo_set_target_input(intel_output, false, true);
  1016. intel_sdvo_get_input_timing(intel_output,
  1017. &sdvo_priv->save_input_dtd_2);
  1018. }
  1019. for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
  1020. {
  1021. u16 this_output = (1 << o);
  1022. if (sdvo_priv->caps.output_flags & this_output)
  1023. {
  1024. intel_sdvo_set_target_output(intel_output, this_output);
  1025. intel_sdvo_get_output_timing(intel_output,
  1026. &sdvo_priv->save_output_dtd[o]);
  1027. }
  1028. }
  1029. if (sdvo_priv->is_tv) {
  1030. /* XXX: Save TV format/enhancements. */
  1031. }
  1032. sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
  1033. }
  1034. static void intel_sdvo_restore(struct drm_connector *connector)
  1035. {
  1036. struct drm_device *dev = connector->dev;
  1037. struct intel_output *intel_output = to_intel_output(connector);
  1038. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1039. int o;
  1040. int i;
  1041. bool input1, input2;
  1042. u8 status;
  1043. intel_sdvo_set_active_outputs(intel_output, 0);
  1044. for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
  1045. {
  1046. u16 this_output = (1 << o);
  1047. if (sdvo_priv->caps.output_flags & this_output) {
  1048. intel_sdvo_set_target_output(intel_output, this_output);
  1049. intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
  1050. }
  1051. }
  1052. if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
  1053. intel_sdvo_set_target_input(intel_output, true, false);
  1054. intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
  1055. }
  1056. if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
  1057. intel_sdvo_set_target_input(intel_output, false, true);
  1058. intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
  1059. }
  1060. intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
  1061. if (sdvo_priv->is_tv) {
  1062. /* XXX: Restore TV format/enhancements. */
  1063. }
  1064. intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
  1065. if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
  1066. {
  1067. for (i = 0; i < 2; i++)
  1068. intel_wait_for_vblank(dev);
  1069. status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
  1070. if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
  1071. DRM_DEBUG("First %s output reported failure to sync\n",
  1072. SDVO_NAME(sdvo_priv));
  1073. }
  1074. intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
  1075. }
  1076. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1077. struct drm_display_mode *mode)
  1078. {
  1079. struct intel_output *intel_output = to_intel_output(connector);
  1080. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1081. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1082. return MODE_NO_DBLESCAN;
  1083. if (sdvo_priv->pixel_clock_min > mode->clock)
  1084. return MODE_CLOCK_LOW;
  1085. if (sdvo_priv->pixel_clock_max < mode->clock)
  1086. return MODE_CLOCK_HIGH;
  1087. return MODE_OK;
  1088. }
  1089. static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
  1090. {
  1091. u8 status;
  1092. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
  1093. status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
  1094. if (status != SDVO_CMD_STATUS_SUCCESS)
  1095. return false;
  1096. return true;
  1097. }
  1098. struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1099. {
  1100. struct drm_connector *connector = NULL;
  1101. struct intel_output *iout = NULL;
  1102. struct intel_sdvo_priv *sdvo;
  1103. /* find the sdvo connector */
  1104. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1105. iout = to_intel_output(connector);
  1106. if (iout->type != INTEL_OUTPUT_SDVO)
  1107. continue;
  1108. sdvo = iout->dev_priv;
  1109. if (sdvo->output_device == SDVOB && sdvoB)
  1110. return connector;
  1111. if (sdvo->output_device == SDVOC && !sdvoB)
  1112. return connector;
  1113. }
  1114. return NULL;
  1115. }
  1116. int intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1117. {
  1118. u8 response[2];
  1119. u8 status;
  1120. struct intel_output *intel_output;
  1121. DRM_DEBUG("\n");
  1122. if (!connector)
  1123. return 0;
  1124. intel_output = to_intel_output(connector);
  1125. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1126. status = intel_sdvo_read_response(intel_output, &response, 2);
  1127. if (response[0] !=0)
  1128. return 1;
  1129. return 0;
  1130. }
  1131. void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1132. {
  1133. u8 response[2];
  1134. u8 status;
  1135. struct intel_output *intel_output = to_intel_output(connector);
  1136. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1137. intel_sdvo_read_response(intel_output, &response, 2);
  1138. if (on) {
  1139. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1140. status = intel_sdvo_read_response(intel_output, &response, 2);
  1141. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1142. } else {
  1143. response[0] = 0;
  1144. response[1] = 0;
  1145. intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1146. }
  1147. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1148. intel_sdvo_read_response(intel_output, &response, 2);
  1149. }
  1150. static void
  1151. intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1152. {
  1153. struct intel_output *intel_output = to_intel_output(connector);
  1154. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1155. struct edid *edid = NULL;
  1156. intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
  1157. edid = drm_get_edid(&intel_output->base,
  1158. &intel_output->ddc_bus->adapter);
  1159. if (edid != NULL) {
  1160. sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
  1161. kfree(edid);
  1162. intel_output->base.display_info.raw_edid = NULL;
  1163. }
  1164. }
  1165. static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
  1166. {
  1167. u8 response[2];
  1168. u8 status;
  1169. struct intel_output *intel_output = to_intel_output(connector);
  1170. intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
  1171. status = intel_sdvo_read_response(intel_output, &response, 2);
  1172. DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
  1173. if (status != SDVO_CMD_STATUS_SUCCESS)
  1174. return connector_status_unknown;
  1175. if ((response[0] != 0) || (response[1] != 0)) {
  1176. intel_sdvo_hdmi_sink_detect(connector);
  1177. return connector_status_connected;
  1178. } else
  1179. return connector_status_disconnected;
  1180. }
  1181. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1182. {
  1183. struct intel_output *intel_output = to_intel_output(connector);
  1184. /* set the bus switch and get the modes */
  1185. intel_ddc_get_modes(intel_output);
  1186. #if 0
  1187. struct drm_device *dev = encoder->dev;
  1188. struct drm_i915_private *dev_priv = dev->dev_private;
  1189. /* Mac mini hack. On this device, I get DDC through the analog, which
  1190. * load-detects as disconnected. I fail to DDC through the SDVO DDC,
  1191. * but it does load-detect as connected. So, just steal the DDC bits
  1192. * from analog when we fail at finding it the right way.
  1193. */
  1194. crt = xf86_config->output[0];
  1195. intel_output = crt->driver_private;
  1196. if (intel_output->type == I830_OUTPUT_ANALOG &&
  1197. crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
  1198. I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
  1199. edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
  1200. xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
  1201. }
  1202. if (edid_mon) {
  1203. xf86OutputSetEDID(output, edid_mon);
  1204. modes = xf86OutputGetEDIDModes(output);
  1205. }
  1206. #endif
  1207. }
  1208. /**
  1209. * This function checks the current TV format, and chooses a default if
  1210. * it hasn't been set.
  1211. */
  1212. static void
  1213. intel_sdvo_check_tv_format(struct intel_output *output)
  1214. {
  1215. struct intel_sdvo_priv *dev_priv = output->dev_priv;
  1216. struct intel_sdvo_tv_format format;
  1217. uint8_t status;
  1218. intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
  1219. status = intel_sdvo_read_response(output, &format, sizeof(format));
  1220. if (status != SDVO_CMD_STATUS_SUCCESS)
  1221. return;
  1222. memcpy(&dev_priv->tv_format, &format, sizeof(format));
  1223. }
  1224. /*
  1225. * Set of SDVO TV modes.
  1226. * Note! This is in reply order (see loop in get_tv_modes).
  1227. * XXX: all 60Hz refresh?
  1228. */
  1229. struct drm_display_mode sdvo_tv_modes[] = {
  1230. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1231. 416, 0, 200, 201, 232, 233, 0,
  1232. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1233. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1234. 416, 0, 240, 241, 272, 273, 0,
  1235. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1236. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1237. 496, 0, 300, 301, 332, 333, 0,
  1238. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1239. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1240. 736, 0, 350, 351, 382, 383, 0,
  1241. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1242. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1243. 736, 0, 400, 401, 432, 433, 0,
  1244. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1245. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1246. 736, 0, 480, 481, 512, 513, 0,
  1247. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1248. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1249. 800, 0, 480, 481, 512, 513, 0,
  1250. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1251. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1252. 800, 0, 576, 577, 608, 609, 0,
  1253. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1254. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1255. 816, 0, 350, 351, 382, 383, 0,
  1256. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1257. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1258. 816, 0, 400, 401, 432, 433, 0,
  1259. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1260. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1261. 816, 0, 480, 481, 512, 513, 0,
  1262. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1263. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1264. 816, 0, 540, 541, 572, 573, 0,
  1265. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1266. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1267. 816, 0, 576, 577, 608, 609, 0,
  1268. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1269. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1270. 864, 0, 576, 577, 608, 609, 0,
  1271. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1272. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1273. 896, 0, 600, 601, 632, 633, 0,
  1274. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1275. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1276. 928, 0, 624, 625, 656, 657, 0,
  1277. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1278. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1279. 1016, 0, 766, 767, 798, 799, 0,
  1280. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1281. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1282. 1120, 0, 768, 769, 800, 801, 0,
  1283. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1284. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1285. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1286. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1287. };
  1288. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1289. {
  1290. struct intel_output *output = to_intel_output(connector);
  1291. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  1292. struct intel_sdvo_sdtv_resolution_request tv_res;
  1293. uint32_t reply = 0;
  1294. uint8_t status;
  1295. int i = 0;
  1296. intel_sdvo_check_tv_format(output);
  1297. /* Read the list of supported input resolutions for the selected TV
  1298. * format.
  1299. */
  1300. memset(&tv_res, 0, sizeof(tv_res));
  1301. memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
  1302. intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1303. &tv_res, sizeof(tv_res));
  1304. status = intel_sdvo_read_response(output, &reply, 3);
  1305. if (status != SDVO_CMD_STATUS_SUCCESS)
  1306. return;
  1307. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1308. if (reply & (1 << i)) {
  1309. struct drm_display_mode *nmode;
  1310. nmode = drm_mode_duplicate(connector->dev,
  1311. &sdvo_tv_modes[i]);
  1312. if (nmode)
  1313. drm_mode_probed_add(connector, nmode);
  1314. }
  1315. }
  1316. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1317. {
  1318. struct intel_output *intel_output = to_intel_output(connector);
  1319. struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
  1320. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1321. /*
  1322. * Attempt to get the mode list from DDC.
  1323. * Assume that the preferred modes are
  1324. * arranged in priority order.
  1325. */
  1326. /* set the bus switch and get the modes */
  1327. intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
  1328. intel_ddc_get_modes(intel_output);
  1329. if (list_empty(&connector->probed_modes) == false)
  1330. return;
  1331. /* Fetch modes from VBT */
  1332. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1333. struct drm_display_mode *newmode;
  1334. newmode = drm_mode_duplicate(connector->dev,
  1335. dev_priv->sdvo_lvds_vbt_mode);
  1336. if (newmode != NULL) {
  1337. /* Guarantee the mode is preferred */
  1338. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1339. DRM_MODE_TYPE_DRIVER);
  1340. drm_mode_probed_add(connector, newmode);
  1341. }
  1342. }
  1343. }
  1344. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1345. {
  1346. struct intel_output *output = to_intel_output(connector);
  1347. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  1348. if (sdvo_priv->is_tv)
  1349. intel_sdvo_get_tv_modes(connector);
  1350. else if (sdvo_priv->is_lvds == true)
  1351. intel_sdvo_get_lvds_modes(connector);
  1352. else
  1353. intel_sdvo_get_ddc_modes(connector);
  1354. if (list_empty(&connector->probed_modes))
  1355. return 0;
  1356. return 1;
  1357. }
  1358. static void intel_sdvo_destroy(struct drm_connector *connector)
  1359. {
  1360. struct intel_output *intel_output = to_intel_output(connector);
  1361. if (intel_output->i2c_bus)
  1362. intel_i2c_destroy(intel_output->i2c_bus);
  1363. if (intel_output->ddc_bus)
  1364. intel_i2c_destroy(intel_output->ddc_bus);
  1365. drm_sysfs_connector_remove(connector);
  1366. drm_connector_cleanup(connector);
  1367. kfree(intel_output);
  1368. }
  1369. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1370. .dpms = intel_sdvo_dpms,
  1371. .mode_fixup = intel_sdvo_mode_fixup,
  1372. .prepare = intel_encoder_prepare,
  1373. .mode_set = intel_sdvo_mode_set,
  1374. .commit = intel_encoder_commit,
  1375. };
  1376. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1377. .dpms = drm_helper_connector_dpms,
  1378. .save = intel_sdvo_save,
  1379. .restore = intel_sdvo_restore,
  1380. .detect = intel_sdvo_detect,
  1381. .fill_modes = drm_helper_probe_single_connector_modes,
  1382. .destroy = intel_sdvo_destroy,
  1383. };
  1384. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1385. .get_modes = intel_sdvo_get_modes,
  1386. .mode_valid = intel_sdvo_mode_valid,
  1387. .best_encoder = intel_best_encoder,
  1388. };
  1389. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1390. {
  1391. drm_encoder_cleanup(encoder);
  1392. }
  1393. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1394. .destroy = intel_sdvo_enc_destroy,
  1395. };
  1396. /**
  1397. * Choose the appropriate DDC bus for control bus switch command for this
  1398. * SDVO output based on the controlled output.
  1399. *
  1400. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1401. * outputs, then LVDS outputs.
  1402. */
  1403. static void
  1404. intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
  1405. {
  1406. uint16_t mask = 0;
  1407. unsigned int num_bits;
  1408. /* Make a mask of outputs less than or equal to our own priority in the
  1409. * list.
  1410. */
  1411. switch (dev_priv->controlled_output) {
  1412. case SDVO_OUTPUT_LVDS1:
  1413. mask |= SDVO_OUTPUT_LVDS1;
  1414. case SDVO_OUTPUT_LVDS0:
  1415. mask |= SDVO_OUTPUT_LVDS0;
  1416. case SDVO_OUTPUT_TMDS1:
  1417. mask |= SDVO_OUTPUT_TMDS1;
  1418. case SDVO_OUTPUT_TMDS0:
  1419. mask |= SDVO_OUTPUT_TMDS0;
  1420. case SDVO_OUTPUT_RGB1:
  1421. mask |= SDVO_OUTPUT_RGB1;
  1422. case SDVO_OUTPUT_RGB0:
  1423. mask |= SDVO_OUTPUT_RGB0;
  1424. break;
  1425. }
  1426. /* Count bits to find what number we are in the priority list. */
  1427. mask &= dev_priv->caps.output_flags;
  1428. num_bits = hweight16(mask);
  1429. if (num_bits > 3) {
  1430. /* if more than 3 outputs, default to DDC bus 3 for now */
  1431. num_bits = 3;
  1432. }
  1433. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1434. dev_priv->ddc_bus = 1 << num_bits;
  1435. }
  1436. static bool
  1437. intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
  1438. {
  1439. struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
  1440. uint8_t status;
  1441. intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
  1442. intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
  1443. status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
  1444. if (status != SDVO_CMD_STATUS_SUCCESS)
  1445. return false;
  1446. return true;
  1447. }
  1448. static struct intel_output *
  1449. intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
  1450. {
  1451. struct drm_device *dev = chan->drm_dev;
  1452. struct drm_connector *connector;
  1453. struct intel_output *intel_output = NULL;
  1454. list_for_each_entry(connector,
  1455. &dev->mode_config.connector_list, head) {
  1456. if (to_intel_output(connector)->ddc_bus == chan) {
  1457. intel_output = to_intel_output(connector);
  1458. break;
  1459. }
  1460. }
  1461. return intel_output;
  1462. }
  1463. static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
  1464. struct i2c_msg msgs[], int num)
  1465. {
  1466. struct intel_output *intel_output;
  1467. struct intel_sdvo_priv *sdvo_priv;
  1468. struct i2c_algo_bit_data *algo_data;
  1469. struct i2c_algorithm *algo;
  1470. algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
  1471. intel_output =
  1472. intel_sdvo_chan_to_intel_output(
  1473. (struct intel_i2c_chan *)(algo_data->data));
  1474. if (intel_output == NULL)
  1475. return -EINVAL;
  1476. sdvo_priv = intel_output->dev_priv;
  1477. algo = (struct i2c_algorithm *)intel_output->i2c_bus->adapter.algo;
  1478. intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
  1479. return algo->master_xfer(i2c_adap, msgs, num);
  1480. }
  1481. static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
  1482. .master_xfer = intel_sdvo_master_xfer,
  1483. };
  1484. static u8
  1485. intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
  1486. {
  1487. struct drm_i915_private *dev_priv = dev->dev_private;
  1488. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1489. if (output_device == SDVOB) {
  1490. my_mapping = &dev_priv->sdvo_mappings[0];
  1491. other_mapping = &dev_priv->sdvo_mappings[1];
  1492. } else {
  1493. my_mapping = &dev_priv->sdvo_mappings[1];
  1494. other_mapping = &dev_priv->sdvo_mappings[0];
  1495. }
  1496. /* If the BIOS described our SDVO device, take advantage of it. */
  1497. if (my_mapping->slave_addr)
  1498. return my_mapping->slave_addr;
  1499. /* If the BIOS only described a different SDVO device, use the
  1500. * address that it isn't using.
  1501. */
  1502. if (other_mapping->slave_addr) {
  1503. if (other_mapping->slave_addr == 0x70)
  1504. return 0x72;
  1505. else
  1506. return 0x70;
  1507. }
  1508. /* No SDVO device info is found for another DVO port,
  1509. * so use mapping assumption we had before BIOS parsing.
  1510. */
  1511. if (output_device == SDVOB)
  1512. return 0x70;
  1513. else
  1514. return 0x72;
  1515. }
  1516. bool intel_sdvo_init(struct drm_device *dev, int output_device)
  1517. {
  1518. struct drm_connector *connector;
  1519. struct intel_output *intel_output;
  1520. struct intel_sdvo_priv *sdvo_priv;
  1521. struct intel_i2c_chan *i2cbus = NULL;
  1522. struct intel_i2c_chan *ddcbus = NULL;
  1523. int connector_type;
  1524. u8 ch[0x40];
  1525. int i;
  1526. int encoder_type, output_id;
  1527. u8 slave_addr;
  1528. intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
  1529. if (!intel_output) {
  1530. return false;
  1531. }
  1532. sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
  1533. intel_output->type = INTEL_OUTPUT_SDVO;
  1534. /* setup the DDC bus. */
  1535. if (output_device == SDVOB)
  1536. i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
  1537. else
  1538. i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
  1539. if (!i2cbus)
  1540. goto err_inteloutput;
  1541. slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
  1542. sdvo_priv->i2c_bus = i2cbus;
  1543. if (output_device == SDVOB) {
  1544. output_id = 1;
  1545. } else {
  1546. output_id = 2;
  1547. }
  1548. sdvo_priv->i2c_bus->slave_addr = slave_addr >> 1;
  1549. sdvo_priv->output_device = output_device;
  1550. intel_output->i2c_bus = i2cbus;
  1551. intel_output->dev_priv = sdvo_priv;
  1552. /* Read the regs to test if we can talk to the device */
  1553. for (i = 0; i < 0x40; i++) {
  1554. if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
  1555. DRM_DEBUG_KMS(I915_SDVO,
  1556. "No SDVO device found on SDVO%c\n",
  1557. output_device == SDVOB ? 'B' : 'C');
  1558. goto err_i2c;
  1559. }
  1560. }
  1561. /* setup the DDC bus. */
  1562. if (output_device == SDVOB)
  1563. ddcbus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
  1564. else
  1565. ddcbus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
  1566. if (ddcbus == NULL)
  1567. goto err_i2c;
  1568. intel_sdvo_i2c_bit_algo.functionality =
  1569. intel_output->i2c_bus->adapter.algo->functionality;
  1570. ddcbus->adapter.algo = &intel_sdvo_i2c_bit_algo;
  1571. intel_output->ddc_bus = ddcbus;
  1572. /* In defaut case sdvo lvds is false */
  1573. sdvo_priv->is_lvds = false;
  1574. intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
  1575. if (sdvo_priv->caps.output_flags &
  1576. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
  1577. if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
  1578. sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
  1579. else
  1580. sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
  1581. encoder_type = DRM_MODE_ENCODER_TMDS;
  1582. connector_type = DRM_MODE_CONNECTOR_DVID;
  1583. if (intel_sdvo_get_supp_encode(intel_output,
  1584. &sdvo_priv->encode) &&
  1585. intel_sdvo_get_digital_encoding_mode(intel_output) &&
  1586. sdvo_priv->is_hdmi) {
  1587. /* enable hdmi encoding mode if supported */
  1588. intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
  1589. intel_sdvo_set_colorimetry(intel_output,
  1590. SDVO_COLORIMETRY_RGB256);
  1591. connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1592. }
  1593. }
  1594. else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
  1595. {
  1596. sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
  1597. encoder_type = DRM_MODE_ENCODER_TVDAC;
  1598. connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1599. sdvo_priv->is_tv = true;
  1600. intel_output->needs_tv_clock = true;
  1601. }
  1602. else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
  1603. {
  1604. sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
  1605. encoder_type = DRM_MODE_ENCODER_DAC;
  1606. connector_type = DRM_MODE_CONNECTOR_VGA;
  1607. }
  1608. else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
  1609. {
  1610. sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
  1611. encoder_type = DRM_MODE_ENCODER_DAC;
  1612. connector_type = DRM_MODE_CONNECTOR_VGA;
  1613. }
  1614. else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
  1615. {
  1616. sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
  1617. encoder_type = DRM_MODE_ENCODER_LVDS;
  1618. connector_type = DRM_MODE_CONNECTOR_LVDS;
  1619. sdvo_priv->is_lvds = true;
  1620. }
  1621. else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
  1622. {
  1623. sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
  1624. encoder_type = DRM_MODE_ENCODER_LVDS;
  1625. connector_type = DRM_MODE_CONNECTOR_LVDS;
  1626. sdvo_priv->is_lvds = true;
  1627. }
  1628. else
  1629. {
  1630. unsigned char bytes[2];
  1631. sdvo_priv->controlled_output = 0;
  1632. memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
  1633. DRM_DEBUG_KMS(I915_SDVO,
  1634. "%s: Unknown SDVO output type (0x%02x%02x)\n",
  1635. SDVO_NAME(sdvo_priv),
  1636. bytes[0], bytes[1]);
  1637. encoder_type = DRM_MODE_ENCODER_NONE;
  1638. connector_type = DRM_MODE_CONNECTOR_Unknown;
  1639. goto err_i2c;
  1640. }
  1641. connector = &intel_output->base;
  1642. drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
  1643. connector_type);
  1644. drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
  1645. connector->interlace_allowed = 0;
  1646. connector->doublescan_allowed = 0;
  1647. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  1648. drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
  1649. drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
  1650. drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
  1651. drm_sysfs_connector_add(connector);
  1652. intel_sdvo_select_ddc_bus(sdvo_priv);
  1653. /* Set the input timing to the screen. Assume always input 0. */
  1654. intel_sdvo_set_target_input(intel_output, true, false);
  1655. intel_sdvo_get_input_pixel_clock_range(intel_output,
  1656. &sdvo_priv->pixel_clock_min,
  1657. &sdvo_priv->pixel_clock_max);
  1658. DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, "
  1659. "clock range %dMHz - %dMHz, "
  1660. "input 1: %c, input 2: %c, "
  1661. "output 1: %c, output 2: %c\n",
  1662. SDVO_NAME(sdvo_priv),
  1663. sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
  1664. sdvo_priv->caps.device_rev_id,
  1665. sdvo_priv->pixel_clock_min / 1000,
  1666. sdvo_priv->pixel_clock_max / 1000,
  1667. (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  1668. (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  1669. /* check currently supported outputs */
  1670. sdvo_priv->caps.output_flags &
  1671. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  1672. sdvo_priv->caps.output_flags &
  1673. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  1674. return true;
  1675. err_i2c:
  1676. if (ddcbus != NULL)
  1677. intel_i2c_destroy(intel_output->ddc_bus);
  1678. intel_i2c_destroy(intel_output->i2c_bus);
  1679. err_inteloutput:
  1680. kfree(intel_output);
  1681. return false;
  1682. }