intel_display.c 78 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/i2c.h>
  27. #include "drmP.h"
  28. #include "intel_drv.h"
  29. #include "i915_drm.h"
  30. #include "i915_drv.h"
  31. #include "drm_crtc_helper.h"
  32. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  33. typedef struct {
  34. /* given values */
  35. int n;
  36. int m1, m2;
  37. int p1, p2;
  38. /* derived values */
  39. int dot;
  40. int vco;
  41. int m;
  42. int p;
  43. } intel_clock_t;
  44. typedef struct {
  45. int min, max;
  46. } intel_range_t;
  47. typedef struct {
  48. int dot_limit;
  49. int p2_slow, p2_fast;
  50. } intel_p2_t;
  51. #define INTEL_P2_NUM 2
  52. typedef struct intel_limit intel_limit_t;
  53. struct intel_limit {
  54. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  55. intel_p2_t p2;
  56. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  57. int, int, intel_clock_t *);
  58. };
  59. #define I8XX_DOT_MIN 25000
  60. #define I8XX_DOT_MAX 350000
  61. #define I8XX_VCO_MIN 930000
  62. #define I8XX_VCO_MAX 1400000
  63. #define I8XX_N_MIN 3
  64. #define I8XX_N_MAX 16
  65. #define I8XX_M_MIN 96
  66. #define I8XX_M_MAX 140
  67. #define I8XX_M1_MIN 18
  68. #define I8XX_M1_MAX 26
  69. #define I8XX_M2_MIN 6
  70. #define I8XX_M2_MAX 16
  71. #define I8XX_P_MIN 4
  72. #define I8XX_P_MAX 128
  73. #define I8XX_P1_MIN 2
  74. #define I8XX_P1_MAX 33
  75. #define I8XX_P1_LVDS_MIN 1
  76. #define I8XX_P1_LVDS_MAX 6
  77. #define I8XX_P2_SLOW 4
  78. #define I8XX_P2_FAST 2
  79. #define I8XX_P2_LVDS_SLOW 14
  80. #define I8XX_P2_LVDS_FAST 14 /* No fast option */
  81. #define I8XX_P2_SLOW_LIMIT 165000
  82. #define I9XX_DOT_MIN 20000
  83. #define I9XX_DOT_MAX 400000
  84. #define I9XX_VCO_MIN 1400000
  85. #define I9XX_VCO_MAX 2800000
  86. #define IGD_VCO_MIN 1700000
  87. #define IGD_VCO_MAX 3500000
  88. #define I9XX_N_MIN 1
  89. #define I9XX_N_MAX 6
  90. /* IGD's Ncounter is a ring counter */
  91. #define IGD_N_MIN 3
  92. #define IGD_N_MAX 6
  93. #define I9XX_M_MIN 70
  94. #define I9XX_M_MAX 120
  95. #define IGD_M_MIN 2
  96. #define IGD_M_MAX 256
  97. #define I9XX_M1_MIN 10
  98. #define I9XX_M1_MAX 22
  99. #define I9XX_M2_MIN 5
  100. #define I9XX_M2_MAX 9
  101. /* IGD M1 is reserved, and must be 0 */
  102. #define IGD_M1_MIN 0
  103. #define IGD_M1_MAX 0
  104. #define IGD_M2_MIN 0
  105. #define IGD_M2_MAX 254
  106. #define I9XX_P_SDVO_DAC_MIN 5
  107. #define I9XX_P_SDVO_DAC_MAX 80
  108. #define I9XX_P_LVDS_MIN 7
  109. #define I9XX_P_LVDS_MAX 98
  110. #define IGD_P_LVDS_MIN 7
  111. #define IGD_P_LVDS_MAX 112
  112. #define I9XX_P1_MIN 1
  113. #define I9XX_P1_MAX 8
  114. #define I9XX_P2_SDVO_DAC_SLOW 10
  115. #define I9XX_P2_SDVO_DAC_FAST 5
  116. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  117. #define I9XX_P2_LVDS_SLOW 14
  118. #define I9XX_P2_LVDS_FAST 7
  119. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  120. #define INTEL_LIMIT_I8XX_DVO_DAC 0
  121. #define INTEL_LIMIT_I8XX_LVDS 1
  122. #define INTEL_LIMIT_I9XX_SDVO_DAC 2
  123. #define INTEL_LIMIT_I9XX_LVDS 3
  124. #define INTEL_LIMIT_G4X_SDVO 4
  125. #define INTEL_LIMIT_G4X_HDMI_DAC 5
  126. #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS 6
  127. #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7
  128. #define INTEL_LIMIT_IGD_SDVO_DAC 8
  129. #define INTEL_LIMIT_IGD_LVDS 9
  130. #define INTEL_LIMIT_IGDNG_SDVO_DAC 10
  131. #define INTEL_LIMIT_IGDNG_LVDS 11
  132. /*The parameter is for SDVO on G4x platform*/
  133. #define G4X_DOT_SDVO_MIN 25000
  134. #define G4X_DOT_SDVO_MAX 270000
  135. #define G4X_VCO_MIN 1750000
  136. #define G4X_VCO_MAX 3500000
  137. #define G4X_N_SDVO_MIN 1
  138. #define G4X_N_SDVO_MAX 4
  139. #define G4X_M_SDVO_MIN 104
  140. #define G4X_M_SDVO_MAX 138
  141. #define G4X_M1_SDVO_MIN 17
  142. #define G4X_M1_SDVO_MAX 23
  143. #define G4X_M2_SDVO_MIN 5
  144. #define G4X_M2_SDVO_MAX 11
  145. #define G4X_P_SDVO_MIN 10
  146. #define G4X_P_SDVO_MAX 30
  147. #define G4X_P1_SDVO_MIN 1
  148. #define G4X_P1_SDVO_MAX 3
  149. #define G4X_P2_SDVO_SLOW 10
  150. #define G4X_P2_SDVO_FAST 10
  151. #define G4X_P2_SDVO_LIMIT 270000
  152. /*The parameter is for HDMI_DAC on G4x platform*/
  153. #define G4X_DOT_HDMI_DAC_MIN 22000
  154. #define G4X_DOT_HDMI_DAC_MAX 400000
  155. #define G4X_N_HDMI_DAC_MIN 1
  156. #define G4X_N_HDMI_DAC_MAX 4
  157. #define G4X_M_HDMI_DAC_MIN 104
  158. #define G4X_M_HDMI_DAC_MAX 138
  159. #define G4X_M1_HDMI_DAC_MIN 16
  160. #define G4X_M1_HDMI_DAC_MAX 23
  161. #define G4X_M2_HDMI_DAC_MIN 5
  162. #define G4X_M2_HDMI_DAC_MAX 11
  163. #define G4X_P_HDMI_DAC_MIN 5
  164. #define G4X_P_HDMI_DAC_MAX 80
  165. #define G4X_P1_HDMI_DAC_MIN 1
  166. #define G4X_P1_HDMI_DAC_MAX 8
  167. #define G4X_P2_HDMI_DAC_SLOW 10
  168. #define G4X_P2_HDMI_DAC_FAST 5
  169. #define G4X_P2_HDMI_DAC_LIMIT 165000
  170. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  171. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  172. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  173. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  174. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  175. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  176. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  177. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  178. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  179. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  180. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  181. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  182. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  183. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  184. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  185. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  186. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  187. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  188. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  189. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  190. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  191. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  192. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  193. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  194. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  195. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  196. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  197. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  198. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  199. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  200. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  201. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  202. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  203. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  204. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  205. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  206. /* IGDNG */
  207. /* as we calculate clock using (register_value + 2) for
  208. N/M1/M2, so here the range value for them is (actual_value-2).
  209. */
  210. #define IGDNG_DOT_MIN 25000
  211. #define IGDNG_DOT_MAX 350000
  212. #define IGDNG_VCO_MIN 1760000
  213. #define IGDNG_VCO_MAX 3510000
  214. #define IGDNG_N_MIN 1
  215. #define IGDNG_N_MAX 5
  216. #define IGDNG_M_MIN 79
  217. #define IGDNG_M_MAX 118
  218. #define IGDNG_M1_MIN 12
  219. #define IGDNG_M1_MAX 23
  220. #define IGDNG_M2_MIN 5
  221. #define IGDNG_M2_MAX 9
  222. #define IGDNG_P_SDVO_DAC_MIN 5
  223. #define IGDNG_P_SDVO_DAC_MAX 80
  224. #define IGDNG_P_LVDS_MIN 28
  225. #define IGDNG_P_LVDS_MAX 112
  226. #define IGDNG_P1_MIN 1
  227. #define IGDNG_P1_MAX 8
  228. #define IGDNG_P2_SDVO_DAC_SLOW 10
  229. #define IGDNG_P2_SDVO_DAC_FAST 5
  230. #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
  231. #define IGDNG_P2_LVDS_FAST 7 /* double channel */
  232. #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
  233. static bool
  234. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  235. int target, int refclk, intel_clock_t *best_clock);
  236. static bool
  237. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  238. int target, int refclk, intel_clock_t *best_clock);
  239. static bool
  240. intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  241. int target, int refclk, intel_clock_t *best_clock);
  242. static const intel_limit_t intel_limits[] = {
  243. { /* INTEL_LIMIT_I8XX_DVO_DAC */
  244. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  245. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  246. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  247. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  248. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  249. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  250. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  251. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  252. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  253. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  254. .find_pll = intel_find_best_PLL,
  255. },
  256. { /* INTEL_LIMIT_I8XX_LVDS */
  257. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  258. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  259. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  260. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  261. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  262. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  263. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  264. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  265. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  266. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  267. .find_pll = intel_find_best_PLL,
  268. },
  269. { /* INTEL_LIMIT_I9XX_SDVO_DAC */
  270. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  271. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  272. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  273. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  274. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  275. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  276. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  277. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  278. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  279. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  280. .find_pll = intel_find_best_PLL,
  281. },
  282. { /* INTEL_LIMIT_I9XX_LVDS */
  283. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  284. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  285. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  286. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  287. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  288. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  289. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  290. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  291. /* The single-channel range is 25-112Mhz, and dual-channel
  292. * is 80-224Mhz. Prefer single channel as much as possible.
  293. */
  294. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  295. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  296. .find_pll = intel_find_best_PLL,
  297. },
  298. /* below parameter and function is for G4X Chipset Family*/
  299. { /* INTEL_LIMIT_G4X_SDVO */
  300. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  301. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  302. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  303. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  304. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  305. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  306. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  307. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  308. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  309. .p2_slow = G4X_P2_SDVO_SLOW,
  310. .p2_fast = G4X_P2_SDVO_FAST
  311. },
  312. .find_pll = intel_g4x_find_best_PLL,
  313. },
  314. { /* INTEL_LIMIT_G4X_HDMI_DAC */
  315. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  316. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  317. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  318. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  319. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  320. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  321. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  322. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  323. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  324. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  325. .p2_fast = G4X_P2_HDMI_DAC_FAST
  326. },
  327. .find_pll = intel_g4x_find_best_PLL,
  328. },
  329. { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
  330. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  331. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  332. .vco = { .min = G4X_VCO_MIN,
  333. .max = G4X_VCO_MAX },
  334. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  335. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  336. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  337. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  338. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  339. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  340. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  341. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  342. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  343. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  344. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  345. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  346. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  347. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  348. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  349. },
  350. .find_pll = intel_g4x_find_best_PLL,
  351. },
  352. { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
  353. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  354. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  355. .vco = { .min = G4X_VCO_MIN,
  356. .max = G4X_VCO_MAX },
  357. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  358. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  359. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  360. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  361. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  362. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  363. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  364. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  365. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  366. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  367. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  368. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  369. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  370. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  371. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  372. },
  373. .find_pll = intel_g4x_find_best_PLL,
  374. },
  375. { /* INTEL_LIMIT_IGD_SDVO */
  376. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  377. .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
  378. .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
  379. .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
  380. .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
  381. .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
  382. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  383. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  384. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  385. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  386. .find_pll = intel_find_best_PLL,
  387. },
  388. { /* INTEL_LIMIT_IGD_LVDS */
  389. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  390. .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
  391. .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
  392. .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
  393. .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
  394. .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
  395. .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
  396. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  397. /* IGD only supports single-channel mode. */
  398. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  399. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  400. .find_pll = intel_find_best_PLL,
  401. },
  402. { /* INTEL_LIMIT_IGDNG_SDVO_DAC */
  403. .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
  404. .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
  405. .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
  406. .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
  407. .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
  408. .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
  409. .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
  410. .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
  411. .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
  412. .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
  413. .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
  414. .find_pll = intel_igdng_find_best_PLL,
  415. },
  416. { /* INTEL_LIMIT_IGDNG_LVDS */
  417. .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
  418. .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
  419. .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
  420. .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
  421. .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
  422. .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
  423. .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
  424. .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
  425. .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
  426. .p2_slow = IGDNG_P2_LVDS_SLOW,
  427. .p2_fast = IGDNG_P2_LVDS_FAST },
  428. .find_pll = intel_igdng_find_best_PLL,
  429. },
  430. };
  431. static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
  432. {
  433. const intel_limit_t *limit;
  434. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  435. limit = &intel_limits[INTEL_LIMIT_IGDNG_LVDS];
  436. else
  437. limit = &intel_limits[INTEL_LIMIT_IGDNG_SDVO_DAC];
  438. return limit;
  439. }
  440. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  441. {
  442. struct drm_device *dev = crtc->dev;
  443. struct drm_i915_private *dev_priv = dev->dev_private;
  444. const intel_limit_t *limit;
  445. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  446. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  447. LVDS_CLKB_POWER_UP)
  448. /* LVDS with dual channel */
  449. limit = &intel_limits
  450. [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
  451. else
  452. /* LVDS with dual channel */
  453. limit = &intel_limits
  454. [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
  455. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  456. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  457. limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
  458. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  459. limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
  460. } else /* The option is for other outputs */
  461. limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
  462. return limit;
  463. }
  464. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  465. {
  466. struct drm_device *dev = crtc->dev;
  467. const intel_limit_t *limit;
  468. if (IS_IGDNG(dev))
  469. limit = intel_igdng_limit(crtc);
  470. else if (IS_G4X(dev)) {
  471. limit = intel_g4x_limit(crtc);
  472. } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
  473. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  474. limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
  475. else
  476. limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
  477. } else if (IS_IGD(dev)) {
  478. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  479. limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
  480. else
  481. limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
  482. } else {
  483. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  484. limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
  485. else
  486. limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
  487. }
  488. return limit;
  489. }
  490. /* m1 is reserved as 0 in IGD, n is a ring counter */
  491. static void igd_clock(int refclk, intel_clock_t *clock)
  492. {
  493. clock->m = clock->m2 + 2;
  494. clock->p = clock->p1 * clock->p2;
  495. clock->vco = refclk * clock->m / clock->n;
  496. clock->dot = clock->vco / clock->p;
  497. }
  498. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  499. {
  500. if (IS_IGD(dev)) {
  501. igd_clock(refclk, clock);
  502. return;
  503. }
  504. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  505. clock->p = clock->p1 * clock->p2;
  506. clock->vco = refclk * clock->m / (clock->n + 2);
  507. clock->dot = clock->vco / clock->p;
  508. }
  509. /**
  510. * Returns whether any output on the specified pipe is of the specified type
  511. */
  512. bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
  513. {
  514. struct drm_device *dev = crtc->dev;
  515. struct drm_mode_config *mode_config = &dev->mode_config;
  516. struct drm_connector *l_entry;
  517. list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  518. if (l_entry->encoder &&
  519. l_entry->encoder->crtc == crtc) {
  520. struct intel_output *intel_output = to_intel_output(l_entry);
  521. if (intel_output->type == type)
  522. return true;
  523. }
  524. }
  525. return false;
  526. }
  527. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  528. /**
  529. * Returns whether the given set of divisors are valid for a given refclk with
  530. * the given connectors.
  531. */
  532. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  533. {
  534. const intel_limit_t *limit = intel_limit (crtc);
  535. struct drm_device *dev = crtc->dev;
  536. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  537. INTELPllInvalid ("p1 out of range\n");
  538. if (clock->p < limit->p.min || limit->p.max < clock->p)
  539. INTELPllInvalid ("p out of range\n");
  540. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  541. INTELPllInvalid ("m2 out of range\n");
  542. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  543. INTELPllInvalid ("m1 out of range\n");
  544. if (clock->m1 <= clock->m2 && !IS_IGD(dev))
  545. INTELPllInvalid ("m1 <= m2\n");
  546. if (clock->m < limit->m.min || limit->m.max < clock->m)
  547. INTELPllInvalid ("m out of range\n");
  548. if (clock->n < limit->n.min || limit->n.max < clock->n)
  549. INTELPllInvalid ("n out of range\n");
  550. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  551. INTELPllInvalid ("vco out of range\n");
  552. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  553. * connector, etc., rather than just a single range.
  554. */
  555. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  556. INTELPllInvalid ("dot out of range\n");
  557. return true;
  558. }
  559. static bool
  560. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  561. int target, int refclk, intel_clock_t *best_clock)
  562. {
  563. struct drm_device *dev = crtc->dev;
  564. struct drm_i915_private *dev_priv = dev->dev_private;
  565. intel_clock_t clock;
  566. int err = target;
  567. if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  568. (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
  569. /*
  570. * For LVDS, if the panel is on, just rely on its current
  571. * settings for dual-channel. We haven't figured out how to
  572. * reliably set up different single/dual channel state, if we
  573. * even can.
  574. */
  575. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  576. LVDS_CLKB_POWER_UP)
  577. clock.p2 = limit->p2.p2_fast;
  578. else
  579. clock.p2 = limit->p2.p2_slow;
  580. } else {
  581. if (target < limit->p2.dot_limit)
  582. clock.p2 = limit->p2.p2_slow;
  583. else
  584. clock.p2 = limit->p2.p2_fast;
  585. }
  586. memset (best_clock, 0, sizeof (*best_clock));
  587. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
  588. for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
  589. /* m1 is always 0 in IGD */
  590. if (clock.m2 >= clock.m1 && !IS_IGD(dev))
  591. break;
  592. for (clock.n = limit->n.min; clock.n <= limit->n.max;
  593. clock.n++) {
  594. for (clock.p1 = limit->p1.min;
  595. clock.p1 <= limit->p1.max; clock.p1++) {
  596. int this_err;
  597. intel_clock(dev, refclk, &clock);
  598. if (!intel_PLL_is_valid(crtc, &clock))
  599. continue;
  600. this_err = abs(clock.dot - target);
  601. if (this_err < err) {
  602. *best_clock = clock;
  603. err = this_err;
  604. }
  605. }
  606. }
  607. }
  608. }
  609. return (err != target);
  610. }
  611. static bool
  612. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  613. int target, int refclk, intel_clock_t *best_clock)
  614. {
  615. struct drm_device *dev = crtc->dev;
  616. struct drm_i915_private *dev_priv = dev->dev_private;
  617. intel_clock_t clock;
  618. int max_n;
  619. bool found;
  620. /* approximately equals target * 0.00488 */
  621. int err_most = (target >> 8) + (target >> 10);
  622. found = false;
  623. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  624. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  625. LVDS_CLKB_POWER_UP)
  626. clock.p2 = limit->p2.p2_fast;
  627. else
  628. clock.p2 = limit->p2.p2_slow;
  629. } else {
  630. if (target < limit->p2.dot_limit)
  631. clock.p2 = limit->p2.p2_slow;
  632. else
  633. clock.p2 = limit->p2.p2_fast;
  634. }
  635. memset(best_clock, 0, sizeof(*best_clock));
  636. max_n = limit->n.max;
  637. /* based on hardware requriment prefer smaller n to precision */
  638. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  639. /* based on hardware requirment prefere larger m1,m2, p1 */
  640. for (clock.m1 = limit->m1.max;
  641. clock.m1 >= limit->m1.min; clock.m1--) {
  642. for (clock.m2 = limit->m2.max;
  643. clock.m2 >= limit->m2.min; clock.m2--) {
  644. for (clock.p1 = limit->p1.max;
  645. clock.p1 >= limit->p1.min; clock.p1--) {
  646. int this_err;
  647. intel_clock(dev, refclk, &clock);
  648. if (!intel_PLL_is_valid(crtc, &clock))
  649. continue;
  650. this_err = abs(clock.dot - target) ;
  651. if (this_err < err_most) {
  652. *best_clock = clock;
  653. err_most = this_err;
  654. max_n = clock.n;
  655. found = true;
  656. }
  657. }
  658. }
  659. }
  660. }
  661. return found;
  662. }
  663. static bool
  664. intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  665. int target, int refclk, intel_clock_t *best_clock)
  666. {
  667. struct drm_device *dev = crtc->dev;
  668. struct drm_i915_private *dev_priv = dev->dev_private;
  669. intel_clock_t clock;
  670. int max_n;
  671. bool found;
  672. int err_most = 47;
  673. found = false;
  674. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  675. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  676. LVDS_CLKB_POWER_UP)
  677. clock.p2 = limit->p2.p2_fast;
  678. else
  679. clock.p2 = limit->p2.p2_slow;
  680. } else {
  681. if (target < limit->p2.dot_limit)
  682. clock.p2 = limit->p2.p2_slow;
  683. else
  684. clock.p2 = limit->p2.p2_fast;
  685. }
  686. memset(best_clock, 0, sizeof(*best_clock));
  687. max_n = limit->n.max;
  688. /* based on hardware requriment prefer smaller n to precision */
  689. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  690. /* based on hardware requirment prefere larger m1,m2, p1 */
  691. for (clock.m1 = limit->m1.max;
  692. clock.m1 >= limit->m1.min; clock.m1--) {
  693. for (clock.m2 = limit->m2.max;
  694. clock.m2 >= limit->m2.min; clock.m2--) {
  695. for (clock.p1 = limit->p1.max;
  696. clock.p1 >= limit->p1.min; clock.p1--) {
  697. int this_err;
  698. intel_clock(dev, refclk, &clock);
  699. if (!intel_PLL_is_valid(crtc, &clock))
  700. continue;
  701. this_err = abs((10000 - (target*10000/clock.dot)));
  702. if (this_err < err_most) {
  703. *best_clock = clock;
  704. err_most = this_err;
  705. max_n = clock.n;
  706. found = true;
  707. /* found on first matching */
  708. goto out;
  709. }
  710. }
  711. }
  712. }
  713. }
  714. out:
  715. return found;
  716. }
  717. void
  718. intel_wait_for_vblank(struct drm_device *dev)
  719. {
  720. /* Wait for 20ms, i.e. one cycle at 50hz. */
  721. mdelay(20);
  722. }
  723. static int
  724. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  725. struct drm_framebuffer *old_fb)
  726. {
  727. struct drm_device *dev = crtc->dev;
  728. struct drm_i915_private *dev_priv = dev->dev_private;
  729. struct drm_i915_master_private *master_priv;
  730. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  731. struct intel_framebuffer *intel_fb;
  732. struct drm_i915_gem_object *obj_priv;
  733. struct drm_gem_object *obj;
  734. int pipe = intel_crtc->pipe;
  735. unsigned long Start, Offset;
  736. int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
  737. int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
  738. int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
  739. int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
  740. int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
  741. u32 dspcntr, alignment;
  742. int ret;
  743. /* no fb bound */
  744. if (!crtc->fb) {
  745. DRM_DEBUG("No FB bound\n");
  746. return 0;
  747. }
  748. switch (pipe) {
  749. case 0:
  750. case 1:
  751. break;
  752. default:
  753. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  754. return -EINVAL;
  755. }
  756. intel_fb = to_intel_framebuffer(crtc->fb);
  757. obj = intel_fb->obj;
  758. obj_priv = obj->driver_private;
  759. switch (obj_priv->tiling_mode) {
  760. case I915_TILING_NONE:
  761. alignment = 64 * 1024;
  762. break;
  763. case I915_TILING_X:
  764. /* pin() will align the object as required by fence */
  765. alignment = 0;
  766. break;
  767. case I915_TILING_Y:
  768. /* FIXME: Is this true? */
  769. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  770. return -EINVAL;
  771. default:
  772. BUG();
  773. }
  774. mutex_lock(&dev->struct_mutex);
  775. ret = i915_gem_object_pin(intel_fb->obj, alignment);
  776. if (ret != 0) {
  777. mutex_unlock(&dev->struct_mutex);
  778. return ret;
  779. }
  780. ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
  781. if (ret != 0) {
  782. i915_gem_object_unpin(intel_fb->obj);
  783. mutex_unlock(&dev->struct_mutex);
  784. return ret;
  785. }
  786. dspcntr = I915_READ(dspcntr_reg);
  787. /* Mask out pixel format bits in case we change it */
  788. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  789. switch (crtc->fb->bits_per_pixel) {
  790. case 8:
  791. dspcntr |= DISPPLANE_8BPP;
  792. break;
  793. case 16:
  794. if (crtc->fb->depth == 15)
  795. dspcntr |= DISPPLANE_15_16BPP;
  796. else
  797. dspcntr |= DISPPLANE_16BPP;
  798. break;
  799. case 24:
  800. case 32:
  801. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  802. break;
  803. default:
  804. DRM_ERROR("Unknown color depth\n");
  805. i915_gem_object_unpin(intel_fb->obj);
  806. mutex_unlock(&dev->struct_mutex);
  807. return -EINVAL;
  808. }
  809. if (IS_I965G(dev)) {
  810. if (obj_priv->tiling_mode != I915_TILING_NONE)
  811. dspcntr |= DISPPLANE_TILED;
  812. else
  813. dspcntr &= ~DISPPLANE_TILED;
  814. }
  815. I915_WRITE(dspcntr_reg, dspcntr);
  816. Start = obj_priv->gtt_offset;
  817. Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
  818. DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
  819. I915_WRITE(dspstride, crtc->fb->pitch);
  820. if (IS_I965G(dev)) {
  821. I915_WRITE(dspbase, Offset);
  822. I915_READ(dspbase);
  823. I915_WRITE(dspsurf, Start);
  824. I915_READ(dspsurf);
  825. I915_WRITE(dsptileoff, (y << 16) | x);
  826. } else {
  827. I915_WRITE(dspbase, Start + Offset);
  828. I915_READ(dspbase);
  829. }
  830. intel_wait_for_vblank(dev);
  831. if (old_fb) {
  832. intel_fb = to_intel_framebuffer(old_fb);
  833. i915_gem_object_unpin(intel_fb->obj);
  834. }
  835. mutex_unlock(&dev->struct_mutex);
  836. if (!dev->primary->master)
  837. return 0;
  838. master_priv = dev->primary->master->driver_priv;
  839. if (!master_priv->sarea_priv)
  840. return 0;
  841. if (pipe) {
  842. master_priv->sarea_priv->pipeB_x = x;
  843. master_priv->sarea_priv->pipeB_y = y;
  844. } else {
  845. master_priv->sarea_priv->pipeA_x = x;
  846. master_priv->sarea_priv->pipeA_y = y;
  847. }
  848. return 0;
  849. }
  850. static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
  851. {
  852. struct drm_device *dev = crtc->dev;
  853. struct drm_i915_private *dev_priv = dev->dev_private;
  854. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  855. int pipe = intel_crtc->pipe;
  856. int plane = intel_crtc->pipe;
  857. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  858. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  859. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  860. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  861. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  862. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  863. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  864. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  865. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  866. int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
  867. int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  868. int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  869. int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  870. int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  871. int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  872. int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  873. int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
  874. int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
  875. int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
  876. int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
  877. int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
  878. int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  879. u32 temp;
  880. int tries = 5, j;
  881. /* XXX: When our outputs are all unaware of DPMS modes other than off
  882. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  883. */
  884. switch (mode) {
  885. case DRM_MODE_DPMS_ON:
  886. case DRM_MODE_DPMS_STANDBY:
  887. case DRM_MODE_DPMS_SUSPEND:
  888. DRM_DEBUG("crtc %d dpms on\n", pipe);
  889. /* enable PCH DPLL */
  890. temp = I915_READ(pch_dpll_reg);
  891. if ((temp & DPLL_VCO_ENABLE) == 0) {
  892. I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
  893. I915_READ(pch_dpll_reg);
  894. }
  895. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  896. temp = I915_READ(fdi_rx_reg);
  897. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
  898. FDI_SEL_PCDCLK |
  899. FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
  900. I915_READ(fdi_rx_reg);
  901. udelay(200);
  902. /* Enable CPU FDI TX PLL, always on for IGDNG */
  903. temp = I915_READ(fdi_tx_reg);
  904. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  905. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  906. I915_READ(fdi_tx_reg);
  907. udelay(100);
  908. }
  909. /* Enable CPU pipe */
  910. temp = I915_READ(pipeconf_reg);
  911. if ((temp & PIPEACONF_ENABLE) == 0) {
  912. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  913. I915_READ(pipeconf_reg);
  914. udelay(100);
  915. }
  916. /* configure and enable CPU plane */
  917. temp = I915_READ(dspcntr_reg);
  918. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  919. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  920. /* Flush the plane changes */
  921. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  922. }
  923. /* enable CPU FDI TX and PCH FDI RX */
  924. temp = I915_READ(fdi_tx_reg);
  925. temp |= FDI_TX_ENABLE;
  926. temp |= FDI_DP_PORT_WIDTH_X4; /* default */
  927. temp &= ~FDI_LINK_TRAIN_NONE;
  928. temp |= FDI_LINK_TRAIN_PATTERN_1;
  929. I915_WRITE(fdi_tx_reg, temp);
  930. I915_READ(fdi_tx_reg);
  931. temp = I915_READ(fdi_rx_reg);
  932. temp &= ~FDI_LINK_TRAIN_NONE;
  933. temp |= FDI_LINK_TRAIN_PATTERN_1;
  934. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  935. I915_READ(fdi_rx_reg);
  936. udelay(150);
  937. /* Train FDI. */
  938. /* umask FDI RX Interrupt symbol_lock and bit_lock bit
  939. for train result */
  940. temp = I915_READ(fdi_rx_imr_reg);
  941. temp &= ~FDI_RX_SYMBOL_LOCK;
  942. temp &= ~FDI_RX_BIT_LOCK;
  943. I915_WRITE(fdi_rx_imr_reg, temp);
  944. I915_READ(fdi_rx_imr_reg);
  945. udelay(150);
  946. temp = I915_READ(fdi_rx_iir_reg);
  947. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  948. if ((temp & FDI_RX_BIT_LOCK) == 0) {
  949. for (j = 0; j < tries; j++) {
  950. temp = I915_READ(fdi_rx_iir_reg);
  951. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  952. if (temp & FDI_RX_BIT_LOCK)
  953. break;
  954. udelay(200);
  955. }
  956. if (j != tries)
  957. I915_WRITE(fdi_rx_iir_reg,
  958. temp | FDI_RX_BIT_LOCK);
  959. else
  960. DRM_DEBUG("train 1 fail\n");
  961. } else {
  962. I915_WRITE(fdi_rx_iir_reg,
  963. temp | FDI_RX_BIT_LOCK);
  964. DRM_DEBUG("train 1 ok 2!\n");
  965. }
  966. temp = I915_READ(fdi_tx_reg);
  967. temp &= ~FDI_LINK_TRAIN_NONE;
  968. temp |= FDI_LINK_TRAIN_PATTERN_2;
  969. I915_WRITE(fdi_tx_reg, temp);
  970. temp = I915_READ(fdi_rx_reg);
  971. temp &= ~FDI_LINK_TRAIN_NONE;
  972. temp |= FDI_LINK_TRAIN_PATTERN_2;
  973. I915_WRITE(fdi_rx_reg, temp);
  974. udelay(150);
  975. temp = I915_READ(fdi_rx_iir_reg);
  976. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  977. if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
  978. for (j = 0; j < tries; j++) {
  979. temp = I915_READ(fdi_rx_iir_reg);
  980. DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
  981. if (temp & FDI_RX_SYMBOL_LOCK)
  982. break;
  983. udelay(200);
  984. }
  985. if (j != tries) {
  986. I915_WRITE(fdi_rx_iir_reg,
  987. temp | FDI_RX_SYMBOL_LOCK);
  988. DRM_DEBUG("train 2 ok 1!\n");
  989. } else
  990. DRM_DEBUG("train 2 fail\n");
  991. } else {
  992. I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
  993. DRM_DEBUG("train 2 ok 2!\n");
  994. }
  995. DRM_DEBUG("train done\n");
  996. /* set transcoder timing */
  997. I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
  998. I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
  999. I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
  1000. I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
  1001. I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
  1002. I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
  1003. /* enable PCH transcoder */
  1004. temp = I915_READ(transconf_reg);
  1005. I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  1006. I915_READ(transconf_reg);
  1007. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
  1008. ;
  1009. /* enable normal */
  1010. temp = I915_READ(fdi_tx_reg);
  1011. temp &= ~FDI_LINK_TRAIN_NONE;
  1012. I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
  1013. FDI_TX_ENHANCE_FRAME_ENABLE);
  1014. I915_READ(fdi_tx_reg);
  1015. temp = I915_READ(fdi_rx_reg);
  1016. temp &= ~FDI_LINK_TRAIN_NONE;
  1017. I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
  1018. FDI_RX_ENHANCE_FRAME_ENABLE);
  1019. I915_READ(fdi_rx_reg);
  1020. /* wait one idle pattern time */
  1021. udelay(100);
  1022. intel_crtc_load_lut(crtc);
  1023. break;
  1024. case DRM_MODE_DPMS_OFF:
  1025. DRM_DEBUG("crtc %d dpms off\n", pipe);
  1026. /* Disable the VGA plane that we never use */
  1027. I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
  1028. /* Disable display plane */
  1029. temp = I915_READ(dspcntr_reg);
  1030. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1031. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1032. /* Flush the plane changes */
  1033. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1034. I915_READ(dspbase_reg);
  1035. }
  1036. /* disable cpu pipe, disable after all planes disabled */
  1037. temp = I915_READ(pipeconf_reg);
  1038. if ((temp & PIPEACONF_ENABLE) != 0) {
  1039. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1040. I915_READ(pipeconf_reg);
  1041. /* wait for cpu pipe off, pipe state */
  1042. while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
  1043. ;
  1044. } else
  1045. DRM_DEBUG("crtc %d is disabled\n", pipe);
  1046. /* IGDNG-A : disable cpu panel fitter ? */
  1047. temp = I915_READ(pf_ctl_reg);
  1048. if ((temp & PF_ENABLE) != 0) {
  1049. I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
  1050. I915_READ(pf_ctl_reg);
  1051. }
  1052. /* disable CPU FDI tx and PCH FDI rx */
  1053. temp = I915_READ(fdi_tx_reg);
  1054. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
  1055. I915_READ(fdi_tx_reg);
  1056. temp = I915_READ(fdi_rx_reg);
  1057. I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  1058. I915_READ(fdi_rx_reg);
  1059. /* still set train pattern 1 */
  1060. temp = I915_READ(fdi_tx_reg);
  1061. temp &= ~FDI_LINK_TRAIN_NONE;
  1062. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1063. I915_WRITE(fdi_tx_reg, temp);
  1064. temp = I915_READ(fdi_rx_reg);
  1065. temp &= ~FDI_LINK_TRAIN_NONE;
  1066. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1067. I915_WRITE(fdi_rx_reg, temp);
  1068. /* disable PCH transcoder */
  1069. temp = I915_READ(transconf_reg);
  1070. if ((temp & TRANS_ENABLE) != 0) {
  1071. I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
  1072. I915_READ(transconf_reg);
  1073. /* wait for PCH transcoder off, transcoder state */
  1074. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
  1075. ;
  1076. }
  1077. /* disable PCH DPLL */
  1078. temp = I915_READ(pch_dpll_reg);
  1079. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1080. I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1081. I915_READ(pch_dpll_reg);
  1082. }
  1083. temp = I915_READ(fdi_rx_reg);
  1084. if ((temp & FDI_RX_PLL_ENABLE) != 0) {
  1085. temp &= ~FDI_SEL_PCDCLK;
  1086. temp &= ~FDI_RX_PLL_ENABLE;
  1087. I915_WRITE(fdi_rx_reg, temp);
  1088. I915_READ(fdi_rx_reg);
  1089. }
  1090. /* Wait for the clocks to turn off. */
  1091. udelay(150);
  1092. break;
  1093. }
  1094. }
  1095. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  1096. {
  1097. struct drm_device *dev = crtc->dev;
  1098. struct drm_i915_private *dev_priv = dev->dev_private;
  1099. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1100. int pipe = intel_crtc->pipe;
  1101. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  1102. int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
  1103. int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
  1104. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1105. u32 temp;
  1106. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1107. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1108. */
  1109. switch (mode) {
  1110. case DRM_MODE_DPMS_ON:
  1111. case DRM_MODE_DPMS_STANDBY:
  1112. case DRM_MODE_DPMS_SUSPEND:
  1113. /* Enable the DPLL */
  1114. temp = I915_READ(dpll_reg);
  1115. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1116. I915_WRITE(dpll_reg, temp);
  1117. I915_READ(dpll_reg);
  1118. /* Wait for the clocks to stabilize. */
  1119. udelay(150);
  1120. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1121. I915_READ(dpll_reg);
  1122. /* Wait for the clocks to stabilize. */
  1123. udelay(150);
  1124. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1125. I915_READ(dpll_reg);
  1126. /* Wait for the clocks to stabilize. */
  1127. udelay(150);
  1128. }
  1129. /* Enable the pipe */
  1130. temp = I915_READ(pipeconf_reg);
  1131. if ((temp & PIPEACONF_ENABLE) == 0)
  1132. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1133. /* Enable the plane */
  1134. temp = I915_READ(dspcntr_reg);
  1135. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1136. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1137. /* Flush the plane changes */
  1138. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1139. }
  1140. intel_crtc_load_lut(crtc);
  1141. /* Give the overlay scaler a chance to enable if it's on this pipe */
  1142. //intel_crtc_dpms_video(crtc, true); TODO
  1143. break;
  1144. case DRM_MODE_DPMS_OFF:
  1145. /* Give the overlay scaler a chance to disable if it's on this pipe */
  1146. //intel_crtc_dpms_video(crtc, FALSE); TODO
  1147. /* Disable the VGA plane that we never use */
  1148. I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
  1149. /* Disable display plane */
  1150. temp = I915_READ(dspcntr_reg);
  1151. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1152. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1153. /* Flush the plane changes */
  1154. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1155. I915_READ(dspbase_reg);
  1156. }
  1157. if (!IS_I9XX(dev)) {
  1158. /* Wait for vblank for the disable to take effect */
  1159. intel_wait_for_vblank(dev);
  1160. }
  1161. /* Next, disable display pipes */
  1162. temp = I915_READ(pipeconf_reg);
  1163. if ((temp & PIPEACONF_ENABLE) != 0) {
  1164. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1165. I915_READ(pipeconf_reg);
  1166. }
  1167. /* Wait for vblank for the disable to take effect. */
  1168. intel_wait_for_vblank(dev);
  1169. temp = I915_READ(dpll_reg);
  1170. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1171. I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1172. I915_READ(dpll_reg);
  1173. }
  1174. /* Wait for the clocks to turn off. */
  1175. udelay(150);
  1176. break;
  1177. }
  1178. }
  1179. /**
  1180. * Sets the power management mode of the pipe and plane.
  1181. *
  1182. * This code should probably grow support for turning the cursor off and back
  1183. * on appropriately at the same time as we're turning the pipe off/on.
  1184. */
  1185. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  1186. {
  1187. struct drm_device *dev = crtc->dev;
  1188. struct drm_i915_master_private *master_priv;
  1189. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1190. int pipe = intel_crtc->pipe;
  1191. bool enabled;
  1192. if (IS_IGDNG(dev))
  1193. igdng_crtc_dpms(crtc, mode);
  1194. else
  1195. i9xx_crtc_dpms(crtc, mode);
  1196. if (!dev->primary->master)
  1197. return;
  1198. master_priv = dev->primary->master->driver_priv;
  1199. if (!master_priv->sarea_priv)
  1200. return;
  1201. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  1202. switch (pipe) {
  1203. case 0:
  1204. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  1205. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  1206. break;
  1207. case 1:
  1208. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  1209. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  1210. break;
  1211. default:
  1212. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  1213. break;
  1214. }
  1215. intel_crtc->dpms_mode = mode;
  1216. }
  1217. static void intel_crtc_prepare (struct drm_crtc *crtc)
  1218. {
  1219. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1220. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  1221. }
  1222. static void intel_crtc_commit (struct drm_crtc *crtc)
  1223. {
  1224. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1225. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  1226. }
  1227. void intel_encoder_prepare (struct drm_encoder *encoder)
  1228. {
  1229. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1230. /* lvds has its own version of prepare see intel_lvds_prepare */
  1231. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  1232. }
  1233. void intel_encoder_commit (struct drm_encoder *encoder)
  1234. {
  1235. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1236. /* lvds has its own version of commit see intel_lvds_commit */
  1237. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  1238. }
  1239. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  1240. struct drm_display_mode *mode,
  1241. struct drm_display_mode *adjusted_mode)
  1242. {
  1243. struct drm_device *dev = crtc->dev;
  1244. if (IS_IGDNG(dev)) {
  1245. /* FDI link clock is fixed at 2.7G */
  1246. if (mode->clock * 3 > 27000 * 4)
  1247. return MODE_CLOCK_HIGH;
  1248. }
  1249. return true;
  1250. }
  1251. /** Returns the core display clock speed for i830 - i945 */
  1252. static int intel_get_core_clock_speed(struct drm_device *dev)
  1253. {
  1254. /* Core clock values taken from the published datasheets.
  1255. * The 830 may go up to 166 Mhz, which we should check.
  1256. */
  1257. if (IS_I945G(dev))
  1258. return 400000;
  1259. else if (IS_I915G(dev))
  1260. return 333000;
  1261. else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
  1262. return 200000;
  1263. else if (IS_I915GM(dev)) {
  1264. u16 gcfgc = 0;
  1265. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  1266. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  1267. return 133000;
  1268. else {
  1269. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  1270. case GC_DISPLAY_CLOCK_333_MHZ:
  1271. return 333000;
  1272. default:
  1273. case GC_DISPLAY_CLOCK_190_200_MHZ:
  1274. return 190000;
  1275. }
  1276. }
  1277. } else if (IS_I865G(dev))
  1278. return 266000;
  1279. else if (IS_I855(dev)) {
  1280. u16 hpllcc = 0;
  1281. /* Assume that the hardware is in the high speed state. This
  1282. * should be the default.
  1283. */
  1284. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  1285. case GC_CLOCK_133_200:
  1286. case GC_CLOCK_100_200:
  1287. return 200000;
  1288. case GC_CLOCK_166_250:
  1289. return 250000;
  1290. case GC_CLOCK_100_133:
  1291. return 133000;
  1292. }
  1293. } else /* 852, 830 */
  1294. return 133000;
  1295. return 0; /* Silence gcc warning */
  1296. }
  1297. /**
  1298. * Return the pipe currently connected to the panel fitter,
  1299. * or -1 if the panel fitter is not present or not in use
  1300. */
  1301. static int intel_panel_fitter_pipe (struct drm_device *dev)
  1302. {
  1303. struct drm_i915_private *dev_priv = dev->dev_private;
  1304. u32 pfit_control;
  1305. /* i830 doesn't have a panel fitter */
  1306. if (IS_I830(dev))
  1307. return -1;
  1308. pfit_control = I915_READ(PFIT_CONTROL);
  1309. /* See if the panel fitter is in use */
  1310. if ((pfit_control & PFIT_ENABLE) == 0)
  1311. return -1;
  1312. /* 965 can place panel fitter on either pipe */
  1313. if (IS_I965G(dev))
  1314. return (pfit_control >> 29) & 0x3;
  1315. /* older chips can only use pipe 1 */
  1316. return 1;
  1317. }
  1318. struct fdi_m_n {
  1319. u32 tu;
  1320. u32 gmch_m;
  1321. u32 gmch_n;
  1322. u32 link_m;
  1323. u32 link_n;
  1324. };
  1325. static void
  1326. fdi_reduce_ratio(u32 *num, u32 *den)
  1327. {
  1328. while (*num > 0xffffff || *den > 0xffffff) {
  1329. *num >>= 1;
  1330. *den >>= 1;
  1331. }
  1332. }
  1333. #define DATA_N 0x800000
  1334. #define LINK_N 0x80000
  1335. static void
  1336. igdng_compute_m_n(int bytes_per_pixel, int nlanes,
  1337. int pixel_clock, int link_clock,
  1338. struct fdi_m_n *m_n)
  1339. {
  1340. u64 temp;
  1341. m_n->tu = 64; /* default size */
  1342. temp = (u64) DATA_N * pixel_clock;
  1343. temp = div_u64(temp, link_clock);
  1344. m_n->gmch_m = (temp * bytes_per_pixel) / nlanes;
  1345. m_n->gmch_n = DATA_N;
  1346. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  1347. temp = (u64) LINK_N * pixel_clock;
  1348. m_n->link_m = div_u64(temp, link_clock);
  1349. m_n->link_n = LINK_N;
  1350. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  1351. }
  1352. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  1353. struct drm_display_mode *mode,
  1354. struct drm_display_mode *adjusted_mode,
  1355. int x, int y,
  1356. struct drm_framebuffer *old_fb)
  1357. {
  1358. struct drm_device *dev = crtc->dev;
  1359. struct drm_i915_private *dev_priv = dev->dev_private;
  1360. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1361. int pipe = intel_crtc->pipe;
  1362. int fp_reg = (pipe == 0) ? FPA0 : FPB0;
  1363. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  1364. int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
  1365. int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
  1366. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1367. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  1368. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  1369. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  1370. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  1371. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  1372. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  1373. int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
  1374. int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
  1375. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  1376. int refclk, num_outputs = 0;
  1377. intel_clock_t clock;
  1378. u32 dpll = 0, fp = 0, dspcntr, pipeconf;
  1379. bool ok, is_sdvo = false, is_dvo = false;
  1380. bool is_crt = false, is_lvds = false, is_tv = false;
  1381. struct drm_mode_config *mode_config = &dev->mode_config;
  1382. struct drm_connector *connector;
  1383. const intel_limit_t *limit;
  1384. int ret;
  1385. struct fdi_m_n m_n = {0};
  1386. int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
  1387. int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
  1388. int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
  1389. int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
  1390. int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
  1391. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1392. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1393. int lvds_reg = LVDS;
  1394. u32 temp;
  1395. int sdvo_pixel_multiply;
  1396. drm_vblank_pre_modeset(dev, pipe);
  1397. list_for_each_entry(connector, &mode_config->connector_list, head) {
  1398. struct intel_output *intel_output = to_intel_output(connector);
  1399. if (!connector->encoder || connector->encoder->crtc != crtc)
  1400. continue;
  1401. switch (intel_output->type) {
  1402. case INTEL_OUTPUT_LVDS:
  1403. is_lvds = true;
  1404. break;
  1405. case INTEL_OUTPUT_SDVO:
  1406. case INTEL_OUTPUT_HDMI:
  1407. is_sdvo = true;
  1408. if (intel_output->needs_tv_clock)
  1409. is_tv = true;
  1410. break;
  1411. case INTEL_OUTPUT_DVO:
  1412. is_dvo = true;
  1413. break;
  1414. case INTEL_OUTPUT_TVOUT:
  1415. is_tv = true;
  1416. break;
  1417. case INTEL_OUTPUT_ANALOG:
  1418. is_crt = true;
  1419. break;
  1420. }
  1421. num_outputs++;
  1422. }
  1423. if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
  1424. refclk = dev_priv->lvds_ssc_freq * 1000;
  1425. DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
  1426. } else if (IS_I9XX(dev)) {
  1427. refclk = 96000;
  1428. if (IS_IGDNG(dev))
  1429. refclk = 120000; /* 120Mhz refclk */
  1430. } else {
  1431. refclk = 48000;
  1432. }
  1433. /*
  1434. * Returns a set of divisors for the desired target clock with the given
  1435. * refclk, or FALSE. The returned values represent the clock equation:
  1436. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  1437. */
  1438. limit = intel_limit(crtc);
  1439. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  1440. if (!ok) {
  1441. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  1442. drm_vblank_post_modeset(dev, pipe);
  1443. return -EINVAL;
  1444. }
  1445. /* SDVO TV has fixed PLL values depend on its clock range,
  1446. this mirrors vbios setting. */
  1447. if (is_sdvo && is_tv) {
  1448. if (adjusted_mode->clock >= 100000
  1449. && adjusted_mode->clock < 140500) {
  1450. clock.p1 = 2;
  1451. clock.p2 = 10;
  1452. clock.n = 3;
  1453. clock.m1 = 16;
  1454. clock.m2 = 8;
  1455. } else if (adjusted_mode->clock >= 140500
  1456. && adjusted_mode->clock <= 200000) {
  1457. clock.p1 = 1;
  1458. clock.p2 = 10;
  1459. clock.n = 6;
  1460. clock.m1 = 12;
  1461. clock.m2 = 8;
  1462. }
  1463. }
  1464. /* FDI link */
  1465. if (IS_IGDNG(dev))
  1466. igdng_compute_m_n(3, 4, /* lane num 4 */
  1467. adjusted_mode->clock,
  1468. 270000, /* lane clock */
  1469. &m_n);
  1470. if (IS_IGD(dev))
  1471. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  1472. else
  1473. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  1474. if (!IS_IGDNG(dev))
  1475. dpll = DPLL_VGA_MODE_DIS;
  1476. if (IS_I9XX(dev)) {
  1477. if (is_lvds)
  1478. dpll |= DPLLB_MODE_LVDS;
  1479. else
  1480. dpll |= DPLLB_MODE_DAC_SERIAL;
  1481. if (is_sdvo) {
  1482. dpll |= DPLL_DVO_HIGH_SPEED;
  1483. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  1484. if (IS_I945G(dev) || IS_I945GM(dev))
  1485. dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  1486. else if (IS_IGDNG(dev))
  1487. dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  1488. }
  1489. /* compute bitmask from p1 value */
  1490. if (IS_IGD(dev))
  1491. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
  1492. else {
  1493. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  1494. /* also FPA1 */
  1495. if (IS_IGDNG(dev))
  1496. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  1497. }
  1498. switch (clock.p2) {
  1499. case 5:
  1500. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  1501. break;
  1502. case 7:
  1503. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  1504. break;
  1505. case 10:
  1506. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  1507. break;
  1508. case 14:
  1509. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  1510. break;
  1511. }
  1512. if (IS_I965G(dev) && !IS_IGDNG(dev))
  1513. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  1514. } else {
  1515. if (is_lvds) {
  1516. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  1517. } else {
  1518. if (clock.p1 == 2)
  1519. dpll |= PLL_P1_DIVIDE_BY_TWO;
  1520. else
  1521. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  1522. if (clock.p2 == 4)
  1523. dpll |= PLL_P2_DIVIDE_BY_4;
  1524. }
  1525. }
  1526. if (is_sdvo && is_tv)
  1527. dpll |= PLL_REF_INPUT_TVCLKINBC;
  1528. else if (is_tv)
  1529. /* XXX: just matching BIOS for now */
  1530. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  1531. dpll |= 3;
  1532. else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
  1533. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  1534. else
  1535. dpll |= PLL_REF_INPUT_DREFCLK;
  1536. /* setup pipeconf */
  1537. pipeconf = I915_READ(pipeconf_reg);
  1538. /* Set up the display plane register */
  1539. dspcntr = DISPPLANE_GAMMA_ENABLE;
  1540. /* IGDNG's plane is forced to pipe, bit 24 is to
  1541. enable color space conversion */
  1542. if (!IS_IGDNG(dev)) {
  1543. if (pipe == 0)
  1544. dspcntr |= DISPPLANE_SEL_PIPE_A;
  1545. else
  1546. dspcntr |= DISPPLANE_SEL_PIPE_B;
  1547. }
  1548. if (pipe == 0 && !IS_I965G(dev)) {
  1549. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  1550. * core speed.
  1551. *
  1552. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  1553. * pipe == 0 check?
  1554. */
  1555. if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
  1556. pipeconf |= PIPEACONF_DOUBLE_WIDE;
  1557. else
  1558. pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
  1559. }
  1560. dspcntr |= DISPLAY_PLANE_ENABLE;
  1561. pipeconf |= PIPEACONF_ENABLE;
  1562. dpll |= DPLL_VCO_ENABLE;
  1563. /* Disable the panel fitter if it was on our pipe */
  1564. if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
  1565. I915_WRITE(PFIT_CONTROL, 0);
  1566. DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  1567. drm_mode_debug_printmodeline(mode);
  1568. /* assign to IGDNG registers */
  1569. if (IS_IGDNG(dev)) {
  1570. fp_reg = pch_fp_reg;
  1571. dpll_reg = pch_dpll_reg;
  1572. }
  1573. if (dpll & DPLL_VCO_ENABLE) {
  1574. I915_WRITE(fp_reg, fp);
  1575. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  1576. I915_READ(dpll_reg);
  1577. udelay(150);
  1578. }
  1579. if (IS_IGDNG(dev)) {
  1580. /* enable PCH clock reference source */
  1581. /* XXX need to change the setting for other outputs */
  1582. u32 temp;
  1583. temp = I915_READ(PCH_DREF_CONTROL);
  1584. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  1585. temp |= DREF_NONSPREAD_CK505_ENABLE;
  1586. temp &= ~DREF_SSC_SOURCE_MASK;
  1587. temp |= DREF_SSC_SOURCE_ENABLE;
  1588. temp &= ~DREF_SSC1_ENABLE;
  1589. /* if no eDP, disable source output to CPU */
  1590. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  1591. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  1592. I915_WRITE(PCH_DREF_CONTROL, temp);
  1593. }
  1594. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  1595. * This is an exception to the general rule that mode_set doesn't turn
  1596. * things on.
  1597. */
  1598. if (is_lvds) {
  1599. u32 lvds;
  1600. if (IS_IGDNG(dev))
  1601. lvds_reg = PCH_LVDS;
  1602. lvds = I915_READ(lvds_reg);
  1603. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
  1604. /* Set the B0-B3 data pairs corresponding to whether we're going to
  1605. * set the DPLLs for dual-channel mode or not.
  1606. */
  1607. if (clock.p2 == 7)
  1608. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  1609. else
  1610. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  1611. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  1612. * appropriately here, but we need to look more thoroughly into how
  1613. * panels behave in the two modes.
  1614. */
  1615. I915_WRITE(lvds_reg, lvds);
  1616. I915_READ(lvds_reg);
  1617. }
  1618. I915_WRITE(fp_reg, fp);
  1619. I915_WRITE(dpll_reg, dpll);
  1620. I915_READ(dpll_reg);
  1621. /* Wait for the clocks to stabilize. */
  1622. udelay(150);
  1623. if (IS_I965G(dev) && !IS_IGDNG(dev)) {
  1624. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  1625. I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
  1626. ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
  1627. } else {
  1628. /* write it again -- the BIOS does, after all */
  1629. I915_WRITE(dpll_reg, dpll);
  1630. }
  1631. I915_READ(dpll_reg);
  1632. /* Wait for the clocks to stabilize. */
  1633. udelay(150);
  1634. I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
  1635. ((adjusted_mode->crtc_htotal - 1) << 16));
  1636. I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
  1637. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  1638. I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
  1639. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  1640. I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
  1641. ((adjusted_mode->crtc_vtotal - 1) << 16));
  1642. I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
  1643. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  1644. I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
  1645. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  1646. /* pipesrc and dspsize control the size that is scaled from, which should
  1647. * always be the user's requested size.
  1648. */
  1649. if (!IS_IGDNG(dev)) {
  1650. I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
  1651. (mode->hdisplay - 1));
  1652. I915_WRITE(dsppos_reg, 0);
  1653. }
  1654. I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  1655. if (IS_IGDNG(dev)) {
  1656. I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
  1657. I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
  1658. I915_WRITE(link_m1_reg, m_n.link_m);
  1659. I915_WRITE(link_n1_reg, m_n.link_n);
  1660. /* enable FDI RX PLL too */
  1661. temp = I915_READ(fdi_rx_reg);
  1662. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  1663. udelay(200);
  1664. }
  1665. I915_WRITE(pipeconf_reg, pipeconf);
  1666. I915_READ(pipeconf_reg);
  1667. intel_wait_for_vblank(dev);
  1668. I915_WRITE(dspcntr_reg, dspcntr);
  1669. /* Flush the plane changes */
  1670. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  1671. drm_vblank_post_modeset(dev, pipe);
  1672. return ret;
  1673. }
  1674. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  1675. void intel_crtc_load_lut(struct drm_crtc *crtc)
  1676. {
  1677. struct drm_device *dev = crtc->dev;
  1678. struct drm_i915_private *dev_priv = dev->dev_private;
  1679. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1680. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  1681. int i;
  1682. /* The clocks have to be on to load the palette. */
  1683. if (!crtc->enabled)
  1684. return;
  1685. /* use legacy palette for IGDNG */
  1686. if (IS_IGDNG(dev))
  1687. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  1688. LGC_PALETTE_B;
  1689. for (i = 0; i < 256; i++) {
  1690. I915_WRITE(palreg + 4 * i,
  1691. (intel_crtc->lut_r[i] << 16) |
  1692. (intel_crtc->lut_g[i] << 8) |
  1693. intel_crtc->lut_b[i]);
  1694. }
  1695. }
  1696. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  1697. struct drm_file *file_priv,
  1698. uint32_t handle,
  1699. uint32_t width, uint32_t height)
  1700. {
  1701. struct drm_device *dev = crtc->dev;
  1702. struct drm_i915_private *dev_priv = dev->dev_private;
  1703. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1704. struct drm_gem_object *bo;
  1705. struct drm_i915_gem_object *obj_priv;
  1706. int pipe = intel_crtc->pipe;
  1707. uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
  1708. uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
  1709. uint32_t temp = I915_READ(control);
  1710. size_t addr;
  1711. int ret;
  1712. DRM_DEBUG("\n");
  1713. /* if we want to turn off the cursor ignore width and height */
  1714. if (!handle) {
  1715. DRM_DEBUG("cursor off\n");
  1716. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  1717. temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  1718. temp |= CURSOR_MODE_DISABLE;
  1719. } else {
  1720. temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  1721. }
  1722. addr = 0;
  1723. bo = NULL;
  1724. mutex_lock(&dev->struct_mutex);
  1725. goto finish;
  1726. }
  1727. /* Currently we only support 64x64 cursors */
  1728. if (width != 64 || height != 64) {
  1729. DRM_ERROR("we currently only support 64x64 cursors\n");
  1730. return -EINVAL;
  1731. }
  1732. bo = drm_gem_object_lookup(dev, file_priv, handle);
  1733. if (!bo)
  1734. return -ENOENT;
  1735. obj_priv = bo->driver_private;
  1736. if (bo->size < width * height * 4) {
  1737. DRM_ERROR("buffer is to small\n");
  1738. ret = -ENOMEM;
  1739. goto fail;
  1740. }
  1741. /* we only need to pin inside GTT if cursor is non-phy */
  1742. mutex_lock(&dev->struct_mutex);
  1743. if (!dev_priv->cursor_needs_physical) {
  1744. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  1745. if (ret) {
  1746. DRM_ERROR("failed to pin cursor bo\n");
  1747. goto fail_locked;
  1748. }
  1749. addr = obj_priv->gtt_offset;
  1750. } else {
  1751. ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
  1752. if (ret) {
  1753. DRM_ERROR("failed to attach phys object\n");
  1754. goto fail_locked;
  1755. }
  1756. addr = obj_priv->phys_obj->handle->busaddr;
  1757. }
  1758. if (!IS_I9XX(dev))
  1759. I915_WRITE(CURSIZE, (height << 12) | width);
  1760. /* Hooray for CUR*CNTR differences */
  1761. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  1762. temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  1763. temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  1764. temp |= (pipe << 28); /* Connect to correct pipe */
  1765. } else {
  1766. temp &= ~(CURSOR_FORMAT_MASK);
  1767. temp |= CURSOR_ENABLE;
  1768. temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
  1769. }
  1770. finish:
  1771. I915_WRITE(control, temp);
  1772. I915_WRITE(base, addr);
  1773. if (intel_crtc->cursor_bo) {
  1774. if (dev_priv->cursor_needs_physical) {
  1775. if (intel_crtc->cursor_bo != bo)
  1776. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  1777. } else
  1778. i915_gem_object_unpin(intel_crtc->cursor_bo);
  1779. drm_gem_object_unreference(intel_crtc->cursor_bo);
  1780. }
  1781. mutex_unlock(&dev->struct_mutex);
  1782. intel_crtc->cursor_addr = addr;
  1783. intel_crtc->cursor_bo = bo;
  1784. return 0;
  1785. fail:
  1786. mutex_lock(&dev->struct_mutex);
  1787. fail_locked:
  1788. drm_gem_object_unreference(bo);
  1789. mutex_unlock(&dev->struct_mutex);
  1790. return ret;
  1791. }
  1792. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  1793. {
  1794. struct drm_device *dev = crtc->dev;
  1795. struct drm_i915_private *dev_priv = dev->dev_private;
  1796. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1797. int pipe = intel_crtc->pipe;
  1798. uint32_t temp = 0;
  1799. uint32_t adder;
  1800. if (x < 0) {
  1801. temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  1802. x = -x;
  1803. }
  1804. if (y < 0) {
  1805. temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  1806. y = -y;
  1807. }
  1808. temp |= x << CURSOR_X_SHIFT;
  1809. temp |= y << CURSOR_Y_SHIFT;
  1810. adder = intel_crtc->cursor_addr;
  1811. I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
  1812. I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
  1813. return 0;
  1814. }
  1815. /** Sets the color ramps on behalf of RandR */
  1816. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  1817. u16 blue, int regno)
  1818. {
  1819. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1820. intel_crtc->lut_r[regno] = red >> 8;
  1821. intel_crtc->lut_g[regno] = green >> 8;
  1822. intel_crtc->lut_b[regno] = blue >> 8;
  1823. }
  1824. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  1825. u16 *blue, uint32_t size)
  1826. {
  1827. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1828. int i;
  1829. if (size != 256)
  1830. return;
  1831. for (i = 0; i < 256; i++) {
  1832. intel_crtc->lut_r[i] = red[i] >> 8;
  1833. intel_crtc->lut_g[i] = green[i] >> 8;
  1834. intel_crtc->lut_b[i] = blue[i] >> 8;
  1835. }
  1836. intel_crtc_load_lut(crtc);
  1837. }
  1838. /**
  1839. * Get a pipe with a simple mode set on it for doing load-based monitor
  1840. * detection.
  1841. *
  1842. * It will be up to the load-detect code to adjust the pipe as appropriate for
  1843. * its requirements. The pipe will be connected to no other outputs.
  1844. *
  1845. * Currently this code will only succeed if there is a pipe with no outputs
  1846. * configured for it. In the future, it could choose to temporarily disable
  1847. * some outputs to free up a pipe for its use.
  1848. *
  1849. * \return crtc, or NULL if no pipes are available.
  1850. */
  1851. /* VESA 640x480x72Hz mode to set on the pipe */
  1852. static struct drm_display_mode load_detect_mode = {
  1853. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  1854. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  1855. };
  1856. struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
  1857. struct drm_display_mode *mode,
  1858. int *dpms_mode)
  1859. {
  1860. struct intel_crtc *intel_crtc;
  1861. struct drm_crtc *possible_crtc;
  1862. struct drm_crtc *supported_crtc =NULL;
  1863. struct drm_encoder *encoder = &intel_output->enc;
  1864. struct drm_crtc *crtc = NULL;
  1865. struct drm_device *dev = encoder->dev;
  1866. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1867. struct drm_crtc_helper_funcs *crtc_funcs;
  1868. int i = -1;
  1869. /*
  1870. * Algorithm gets a little messy:
  1871. * - if the connector already has an assigned crtc, use it (but make
  1872. * sure it's on first)
  1873. * - try to find the first unused crtc that can drive this connector,
  1874. * and use that if we find one
  1875. * - if there are no unused crtcs available, try to use the first
  1876. * one we found that supports the connector
  1877. */
  1878. /* See if we already have a CRTC for this connector */
  1879. if (encoder->crtc) {
  1880. crtc = encoder->crtc;
  1881. /* Make sure the crtc and connector are running */
  1882. intel_crtc = to_intel_crtc(crtc);
  1883. *dpms_mode = intel_crtc->dpms_mode;
  1884. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  1885. crtc_funcs = crtc->helper_private;
  1886. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  1887. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  1888. }
  1889. return crtc;
  1890. }
  1891. /* Find an unused one (if possible) */
  1892. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  1893. i++;
  1894. if (!(encoder->possible_crtcs & (1 << i)))
  1895. continue;
  1896. if (!possible_crtc->enabled) {
  1897. crtc = possible_crtc;
  1898. break;
  1899. }
  1900. if (!supported_crtc)
  1901. supported_crtc = possible_crtc;
  1902. }
  1903. /*
  1904. * If we didn't find an unused CRTC, don't use any.
  1905. */
  1906. if (!crtc) {
  1907. return NULL;
  1908. }
  1909. encoder->crtc = crtc;
  1910. intel_output->base.encoder = encoder;
  1911. intel_output->load_detect_temp = true;
  1912. intel_crtc = to_intel_crtc(crtc);
  1913. *dpms_mode = intel_crtc->dpms_mode;
  1914. if (!crtc->enabled) {
  1915. if (!mode)
  1916. mode = &load_detect_mode;
  1917. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  1918. } else {
  1919. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  1920. crtc_funcs = crtc->helper_private;
  1921. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  1922. }
  1923. /* Add this connector to the crtc */
  1924. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  1925. encoder_funcs->commit(encoder);
  1926. }
  1927. /* let the connector get through one full cycle before testing */
  1928. intel_wait_for_vblank(dev);
  1929. return crtc;
  1930. }
  1931. void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
  1932. {
  1933. struct drm_encoder *encoder = &intel_output->enc;
  1934. struct drm_device *dev = encoder->dev;
  1935. struct drm_crtc *crtc = encoder->crtc;
  1936. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1937. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1938. if (intel_output->load_detect_temp) {
  1939. encoder->crtc = NULL;
  1940. intel_output->base.encoder = NULL;
  1941. intel_output->load_detect_temp = false;
  1942. crtc->enabled = drm_helper_crtc_in_use(crtc);
  1943. drm_helper_disable_unused_functions(dev);
  1944. }
  1945. /* Switch crtc and output back off if necessary */
  1946. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  1947. if (encoder->crtc == crtc)
  1948. encoder_funcs->dpms(encoder, dpms_mode);
  1949. crtc_funcs->dpms(crtc, dpms_mode);
  1950. }
  1951. }
  1952. /* Returns the clock of the currently programmed mode of the given pipe. */
  1953. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  1954. {
  1955. struct drm_i915_private *dev_priv = dev->dev_private;
  1956. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1957. int pipe = intel_crtc->pipe;
  1958. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  1959. u32 fp;
  1960. intel_clock_t clock;
  1961. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  1962. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  1963. else
  1964. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  1965. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  1966. if (IS_IGD(dev)) {
  1967. clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  1968. clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
  1969. } else {
  1970. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  1971. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  1972. }
  1973. if (IS_I9XX(dev)) {
  1974. if (IS_IGD(dev))
  1975. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
  1976. DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
  1977. else
  1978. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  1979. DPLL_FPA01_P1_POST_DIV_SHIFT);
  1980. switch (dpll & DPLL_MODE_MASK) {
  1981. case DPLLB_MODE_DAC_SERIAL:
  1982. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  1983. 5 : 10;
  1984. break;
  1985. case DPLLB_MODE_LVDS:
  1986. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  1987. 7 : 14;
  1988. break;
  1989. default:
  1990. DRM_DEBUG("Unknown DPLL mode %08x in programmed "
  1991. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  1992. return 0;
  1993. }
  1994. /* XXX: Handle the 100Mhz refclk */
  1995. intel_clock(dev, 96000, &clock);
  1996. } else {
  1997. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  1998. if (is_lvds) {
  1999. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  2000. DPLL_FPA01_P1_POST_DIV_SHIFT);
  2001. clock.p2 = 14;
  2002. if ((dpll & PLL_REF_INPUT_MASK) ==
  2003. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  2004. /* XXX: might not be 66MHz */
  2005. intel_clock(dev, 66000, &clock);
  2006. } else
  2007. intel_clock(dev, 48000, &clock);
  2008. } else {
  2009. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  2010. clock.p1 = 2;
  2011. else {
  2012. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  2013. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  2014. }
  2015. if (dpll & PLL_P2_DIVIDE_BY_4)
  2016. clock.p2 = 4;
  2017. else
  2018. clock.p2 = 2;
  2019. intel_clock(dev, 48000, &clock);
  2020. }
  2021. }
  2022. /* XXX: It would be nice to validate the clocks, but we can't reuse
  2023. * i830PllIsValid() because it relies on the xf86_config connector
  2024. * configuration being accurate, which it isn't necessarily.
  2025. */
  2026. return clock.dot;
  2027. }
  2028. /** Returns the currently programmed mode of the given pipe. */
  2029. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  2030. struct drm_crtc *crtc)
  2031. {
  2032. struct drm_i915_private *dev_priv = dev->dev_private;
  2033. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2034. int pipe = intel_crtc->pipe;
  2035. struct drm_display_mode *mode;
  2036. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  2037. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  2038. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  2039. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  2040. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  2041. if (!mode)
  2042. return NULL;
  2043. mode->clock = intel_crtc_clock_get(dev, crtc);
  2044. mode->hdisplay = (htot & 0xffff) + 1;
  2045. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  2046. mode->hsync_start = (hsync & 0xffff) + 1;
  2047. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  2048. mode->vdisplay = (vtot & 0xffff) + 1;
  2049. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  2050. mode->vsync_start = (vsync & 0xffff) + 1;
  2051. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  2052. drm_mode_set_name(mode);
  2053. drm_mode_set_crtcinfo(mode, 0);
  2054. return mode;
  2055. }
  2056. static void intel_crtc_destroy(struct drm_crtc *crtc)
  2057. {
  2058. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2059. if (intel_crtc->mode_set.mode)
  2060. drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
  2061. drm_crtc_cleanup(crtc);
  2062. kfree(intel_crtc);
  2063. }
  2064. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  2065. .dpms = intel_crtc_dpms,
  2066. .mode_fixup = intel_crtc_mode_fixup,
  2067. .mode_set = intel_crtc_mode_set,
  2068. .mode_set_base = intel_pipe_set_base,
  2069. .prepare = intel_crtc_prepare,
  2070. .commit = intel_crtc_commit,
  2071. };
  2072. static const struct drm_crtc_funcs intel_crtc_funcs = {
  2073. .cursor_set = intel_crtc_cursor_set,
  2074. .cursor_move = intel_crtc_cursor_move,
  2075. .gamma_set = intel_crtc_gamma_set,
  2076. .set_config = drm_crtc_helper_set_config,
  2077. .destroy = intel_crtc_destroy,
  2078. };
  2079. static void intel_crtc_init(struct drm_device *dev, int pipe)
  2080. {
  2081. struct intel_crtc *intel_crtc;
  2082. int i;
  2083. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  2084. if (intel_crtc == NULL)
  2085. return;
  2086. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  2087. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  2088. intel_crtc->pipe = pipe;
  2089. for (i = 0; i < 256; i++) {
  2090. intel_crtc->lut_r[i] = i;
  2091. intel_crtc->lut_g[i] = i;
  2092. intel_crtc->lut_b[i] = i;
  2093. }
  2094. intel_crtc->cursor_addr = 0;
  2095. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  2096. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  2097. intel_crtc->mode_set.crtc = &intel_crtc->base;
  2098. intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
  2099. intel_crtc->mode_set.num_connectors = 0;
  2100. if (i915_fbpercrtc) {
  2101. }
  2102. }
  2103. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  2104. struct drm_file *file_priv)
  2105. {
  2106. drm_i915_private_t *dev_priv = dev->dev_private;
  2107. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  2108. struct drm_crtc *crtc = NULL;
  2109. int pipe = -1;
  2110. if (!dev_priv) {
  2111. DRM_ERROR("called with no initialization\n");
  2112. return -EINVAL;
  2113. }
  2114. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2115. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2116. if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
  2117. pipe = intel_crtc->pipe;
  2118. break;
  2119. }
  2120. }
  2121. if (pipe == -1) {
  2122. DRM_ERROR("no such CRTC id\n");
  2123. return -EINVAL;
  2124. }
  2125. pipe_from_crtc_id->pipe = pipe;
  2126. return 0;
  2127. }
  2128. struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
  2129. {
  2130. struct drm_crtc *crtc = NULL;
  2131. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2132. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2133. if (intel_crtc->pipe == pipe)
  2134. break;
  2135. }
  2136. return crtc;
  2137. }
  2138. static int intel_connector_clones(struct drm_device *dev, int type_mask)
  2139. {
  2140. int index_mask = 0;
  2141. struct drm_connector *connector;
  2142. int entry = 0;
  2143. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  2144. struct intel_output *intel_output = to_intel_output(connector);
  2145. if (type_mask & (1 << intel_output->type))
  2146. index_mask |= (1 << entry);
  2147. entry++;
  2148. }
  2149. return index_mask;
  2150. }
  2151. static void intel_setup_outputs(struct drm_device *dev)
  2152. {
  2153. struct drm_i915_private *dev_priv = dev->dev_private;
  2154. struct drm_connector *connector;
  2155. intel_crt_init(dev);
  2156. /* Set up integrated LVDS */
  2157. if (IS_MOBILE(dev) && !IS_I830(dev))
  2158. intel_lvds_init(dev);
  2159. if (IS_IGDNG(dev)) {
  2160. int found;
  2161. if (I915_READ(HDMIB) & PORT_DETECTED) {
  2162. /* check SDVOB */
  2163. /* found = intel_sdvo_init(dev, HDMIB); */
  2164. found = 0;
  2165. if (!found)
  2166. intel_hdmi_init(dev, HDMIB);
  2167. }
  2168. if (I915_READ(HDMIC) & PORT_DETECTED)
  2169. intel_hdmi_init(dev, HDMIC);
  2170. if (I915_READ(HDMID) & PORT_DETECTED)
  2171. intel_hdmi_init(dev, HDMID);
  2172. } else if (IS_I9XX(dev)) {
  2173. int found;
  2174. u32 reg;
  2175. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  2176. found = intel_sdvo_init(dev, SDVOB);
  2177. if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
  2178. intel_hdmi_init(dev, SDVOB);
  2179. }
  2180. /* Before G4X SDVOC doesn't have its own detect register */
  2181. if (IS_G4X(dev))
  2182. reg = SDVOC;
  2183. else
  2184. reg = SDVOB;
  2185. if (I915_READ(reg) & SDVO_DETECTED) {
  2186. found = intel_sdvo_init(dev, SDVOC);
  2187. if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
  2188. intel_hdmi_init(dev, SDVOC);
  2189. }
  2190. } else
  2191. intel_dvo_init(dev);
  2192. if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
  2193. intel_tv_init(dev);
  2194. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  2195. struct intel_output *intel_output = to_intel_output(connector);
  2196. struct drm_encoder *encoder = &intel_output->enc;
  2197. int crtc_mask = 0, clone_mask = 0;
  2198. /* valid crtcs */
  2199. switch(intel_output->type) {
  2200. case INTEL_OUTPUT_HDMI:
  2201. crtc_mask = ((1 << 0)|
  2202. (1 << 1));
  2203. clone_mask = ((1 << INTEL_OUTPUT_HDMI));
  2204. break;
  2205. case INTEL_OUTPUT_DVO:
  2206. case INTEL_OUTPUT_SDVO:
  2207. crtc_mask = ((1 << 0)|
  2208. (1 << 1));
  2209. clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
  2210. (1 << INTEL_OUTPUT_DVO) |
  2211. (1 << INTEL_OUTPUT_SDVO));
  2212. break;
  2213. case INTEL_OUTPUT_ANALOG:
  2214. crtc_mask = ((1 << 0)|
  2215. (1 << 1));
  2216. clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
  2217. (1 << INTEL_OUTPUT_DVO) |
  2218. (1 << INTEL_OUTPUT_SDVO));
  2219. break;
  2220. case INTEL_OUTPUT_LVDS:
  2221. crtc_mask = (1 << 1);
  2222. clone_mask = (1 << INTEL_OUTPUT_LVDS);
  2223. break;
  2224. case INTEL_OUTPUT_TVOUT:
  2225. crtc_mask = ((1 << 0) |
  2226. (1 << 1));
  2227. clone_mask = (1 << INTEL_OUTPUT_TVOUT);
  2228. break;
  2229. }
  2230. encoder->possible_crtcs = crtc_mask;
  2231. encoder->possible_clones = intel_connector_clones(dev, clone_mask);
  2232. }
  2233. }
  2234. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  2235. {
  2236. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  2237. struct drm_device *dev = fb->dev;
  2238. if (fb->fbdev)
  2239. intelfb_remove(dev, fb);
  2240. drm_framebuffer_cleanup(fb);
  2241. mutex_lock(&dev->struct_mutex);
  2242. drm_gem_object_unreference(intel_fb->obj);
  2243. mutex_unlock(&dev->struct_mutex);
  2244. kfree(intel_fb);
  2245. }
  2246. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  2247. struct drm_file *file_priv,
  2248. unsigned int *handle)
  2249. {
  2250. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  2251. struct drm_gem_object *object = intel_fb->obj;
  2252. return drm_gem_handle_create(file_priv, object, handle);
  2253. }
  2254. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  2255. .destroy = intel_user_framebuffer_destroy,
  2256. .create_handle = intel_user_framebuffer_create_handle,
  2257. };
  2258. int intel_framebuffer_create(struct drm_device *dev,
  2259. struct drm_mode_fb_cmd *mode_cmd,
  2260. struct drm_framebuffer **fb,
  2261. struct drm_gem_object *obj)
  2262. {
  2263. struct intel_framebuffer *intel_fb;
  2264. int ret;
  2265. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  2266. if (!intel_fb)
  2267. return -ENOMEM;
  2268. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  2269. if (ret) {
  2270. DRM_ERROR("framebuffer init failed %d\n", ret);
  2271. return ret;
  2272. }
  2273. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  2274. intel_fb->obj = obj;
  2275. *fb = &intel_fb->base;
  2276. return 0;
  2277. }
  2278. static struct drm_framebuffer *
  2279. intel_user_framebuffer_create(struct drm_device *dev,
  2280. struct drm_file *filp,
  2281. struct drm_mode_fb_cmd *mode_cmd)
  2282. {
  2283. struct drm_gem_object *obj;
  2284. struct drm_framebuffer *fb;
  2285. int ret;
  2286. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  2287. if (!obj)
  2288. return NULL;
  2289. ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
  2290. if (ret) {
  2291. mutex_lock(&dev->struct_mutex);
  2292. drm_gem_object_unreference(obj);
  2293. mutex_unlock(&dev->struct_mutex);
  2294. return NULL;
  2295. }
  2296. return fb;
  2297. }
  2298. static const struct drm_mode_config_funcs intel_mode_funcs = {
  2299. .fb_create = intel_user_framebuffer_create,
  2300. .fb_changed = intelfb_probe,
  2301. };
  2302. void intel_modeset_init(struct drm_device *dev)
  2303. {
  2304. int num_pipe;
  2305. int i;
  2306. drm_mode_config_init(dev);
  2307. dev->mode_config.min_width = 0;
  2308. dev->mode_config.min_height = 0;
  2309. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  2310. if (IS_I965G(dev)) {
  2311. dev->mode_config.max_width = 8192;
  2312. dev->mode_config.max_height = 8192;
  2313. } else {
  2314. dev->mode_config.max_width = 2048;
  2315. dev->mode_config.max_height = 2048;
  2316. }
  2317. /* set memory base */
  2318. if (IS_I9XX(dev))
  2319. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  2320. else
  2321. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  2322. if (IS_MOBILE(dev) || IS_I9XX(dev))
  2323. num_pipe = 2;
  2324. else
  2325. num_pipe = 1;
  2326. DRM_DEBUG("%d display pipe%s available.\n",
  2327. num_pipe, num_pipe > 1 ? "s" : "");
  2328. for (i = 0; i < num_pipe; i++) {
  2329. intel_crtc_init(dev, i);
  2330. }
  2331. intel_setup_outputs(dev);
  2332. }
  2333. void intel_modeset_cleanup(struct drm_device *dev)
  2334. {
  2335. drm_mode_config_cleanup(dev);
  2336. }
  2337. /* current intel driver doesn't take advantage of encoders
  2338. always give back the encoder for the connector
  2339. */
  2340. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  2341. {
  2342. struct intel_output *intel_output = to_intel_output(connector);
  2343. return &intel_output->enc;
  2344. }