i915_irq.c 22 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "i915_drm.h"
  31. #include "i915_drv.h"
  32. #include "intel_drv.h"
  33. #define MAX_NOPID ((u32)~0)
  34. /**
  35. * Interrupts that are always left unmasked.
  36. *
  37. * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  38. * we leave them always unmasked in IMR and then control enabling them through
  39. * PIPESTAT alone.
  40. */
  41. #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
  42. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  43. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  44. /** Interrupts that we mask and unmask at runtime. */
  45. #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  46. #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  47. PIPE_VBLANK_INTERRUPT_STATUS)
  48. #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  49. PIPE_VBLANK_INTERRUPT_ENABLE)
  50. #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
  51. DRM_I915_VBLANK_PIPE_B)
  52. void
  53. igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  54. {
  55. if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  56. dev_priv->gt_irq_mask_reg &= ~mask;
  57. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  58. (void) I915_READ(GTIMR);
  59. }
  60. }
  61. static inline void
  62. igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  63. {
  64. if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  65. dev_priv->gt_irq_mask_reg |= mask;
  66. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  67. (void) I915_READ(GTIMR);
  68. }
  69. }
  70. /* For display hotplug interrupt */
  71. void
  72. igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  73. {
  74. if ((dev_priv->irq_mask_reg & mask) != 0) {
  75. dev_priv->irq_mask_reg &= ~mask;
  76. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  77. (void) I915_READ(DEIMR);
  78. }
  79. }
  80. static inline void
  81. igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  82. {
  83. if ((dev_priv->irq_mask_reg & mask) != mask) {
  84. dev_priv->irq_mask_reg |= mask;
  85. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  86. (void) I915_READ(DEIMR);
  87. }
  88. }
  89. void
  90. i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  91. {
  92. if ((dev_priv->irq_mask_reg & mask) != 0) {
  93. dev_priv->irq_mask_reg &= ~mask;
  94. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  95. (void) I915_READ(IMR);
  96. }
  97. }
  98. static inline void
  99. i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  100. {
  101. if ((dev_priv->irq_mask_reg & mask) != mask) {
  102. dev_priv->irq_mask_reg |= mask;
  103. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  104. (void) I915_READ(IMR);
  105. }
  106. }
  107. static inline u32
  108. i915_pipestat(int pipe)
  109. {
  110. if (pipe == 0)
  111. return PIPEASTAT;
  112. if (pipe == 1)
  113. return PIPEBSTAT;
  114. BUG();
  115. }
  116. void
  117. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  118. {
  119. if ((dev_priv->pipestat[pipe] & mask) != mask) {
  120. u32 reg = i915_pipestat(pipe);
  121. dev_priv->pipestat[pipe] |= mask;
  122. /* Enable the interrupt, clear any pending status */
  123. I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  124. (void) I915_READ(reg);
  125. }
  126. }
  127. void
  128. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  129. {
  130. if ((dev_priv->pipestat[pipe] & mask) != 0) {
  131. u32 reg = i915_pipestat(pipe);
  132. dev_priv->pipestat[pipe] &= ~mask;
  133. I915_WRITE(reg, dev_priv->pipestat[pipe]);
  134. (void) I915_READ(reg);
  135. }
  136. }
  137. /**
  138. * i915_pipe_enabled - check if a pipe is enabled
  139. * @dev: DRM device
  140. * @pipe: pipe to check
  141. *
  142. * Reading certain registers when the pipe is disabled can hang the chip.
  143. * Use this routine to make sure the PLL is running and the pipe is active
  144. * before reading such registers if unsure.
  145. */
  146. static int
  147. i915_pipe_enabled(struct drm_device *dev, int pipe)
  148. {
  149. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  150. unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
  151. if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
  152. return 1;
  153. return 0;
  154. }
  155. /* Called from drm generic code, passed a 'crtc', which
  156. * we use as a pipe index
  157. */
  158. u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  159. {
  160. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  161. unsigned long high_frame;
  162. unsigned long low_frame;
  163. u32 high1, high2, low, count;
  164. high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
  165. low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
  166. if (!i915_pipe_enabled(dev, pipe)) {
  167. DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
  168. return 0;
  169. }
  170. /*
  171. * High & low register fields aren't synchronized, so make sure
  172. * we get a low value that's stable across two reads of the high
  173. * register.
  174. */
  175. do {
  176. high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
  177. PIPE_FRAME_HIGH_SHIFT);
  178. low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
  179. PIPE_FRAME_LOW_SHIFT);
  180. high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
  181. PIPE_FRAME_HIGH_SHIFT);
  182. } while (high1 != high2);
  183. count = (high1 << 8) | low;
  184. return count;
  185. }
  186. u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  187. {
  188. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  189. int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
  190. if (!i915_pipe_enabled(dev, pipe)) {
  191. DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
  192. return 0;
  193. }
  194. return I915_READ(reg);
  195. }
  196. /*
  197. * Handle hotplug events outside the interrupt handler proper.
  198. */
  199. static void i915_hotplug_work_func(struct work_struct *work)
  200. {
  201. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  202. hotplug_work);
  203. struct drm_device *dev = dev_priv->dev;
  204. /* Just fire off a uevent and let userspace tell us what to do */
  205. drm_sysfs_hotplug_event(dev);
  206. }
  207. irqreturn_t igdng_irq_handler(struct drm_device *dev)
  208. {
  209. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  210. int ret = IRQ_NONE;
  211. u32 de_iir, gt_iir;
  212. u32 new_de_iir, new_gt_iir;
  213. struct drm_i915_master_private *master_priv;
  214. de_iir = I915_READ(DEIIR);
  215. gt_iir = I915_READ(GTIIR);
  216. for (;;) {
  217. if (de_iir == 0 && gt_iir == 0)
  218. break;
  219. ret = IRQ_HANDLED;
  220. I915_WRITE(DEIIR, de_iir);
  221. new_de_iir = I915_READ(DEIIR);
  222. I915_WRITE(GTIIR, gt_iir);
  223. new_gt_iir = I915_READ(GTIIR);
  224. if (dev->primary->master) {
  225. master_priv = dev->primary->master->driver_priv;
  226. if (master_priv->sarea_priv)
  227. master_priv->sarea_priv->last_dispatch =
  228. READ_BREADCRUMB(dev_priv);
  229. }
  230. if (gt_iir & GT_USER_INTERRUPT) {
  231. dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
  232. DRM_WAKEUP(&dev_priv->irq_queue);
  233. }
  234. de_iir = new_de_iir;
  235. gt_iir = new_gt_iir;
  236. }
  237. return ret;
  238. }
  239. irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
  240. {
  241. struct drm_device *dev = (struct drm_device *) arg;
  242. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  243. struct drm_i915_master_private *master_priv;
  244. u32 iir, new_iir;
  245. u32 pipea_stats, pipeb_stats;
  246. u32 vblank_status;
  247. u32 vblank_enable;
  248. int vblank = 0;
  249. unsigned long irqflags;
  250. int irq_received;
  251. int ret = IRQ_NONE;
  252. atomic_inc(&dev_priv->irq_received);
  253. if (IS_IGDNG(dev))
  254. return igdng_irq_handler(dev);
  255. iir = I915_READ(IIR);
  256. if (IS_I965G(dev)) {
  257. vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
  258. vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
  259. } else {
  260. vblank_status = I915_VBLANK_INTERRUPT_STATUS;
  261. vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
  262. }
  263. for (;;) {
  264. irq_received = iir != 0;
  265. /* Can't rely on pipestat interrupt bit in iir as it might
  266. * have been cleared after the pipestat interrupt was received.
  267. * It doesn't set the bit in iir again, but it still produces
  268. * interrupts (for non-MSI).
  269. */
  270. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  271. pipea_stats = I915_READ(PIPEASTAT);
  272. pipeb_stats = I915_READ(PIPEBSTAT);
  273. /*
  274. * Clear the PIPE(A|B)STAT regs before the IIR
  275. */
  276. if (pipea_stats & 0x8000ffff) {
  277. I915_WRITE(PIPEASTAT, pipea_stats);
  278. irq_received = 1;
  279. }
  280. if (pipeb_stats & 0x8000ffff) {
  281. I915_WRITE(PIPEBSTAT, pipeb_stats);
  282. irq_received = 1;
  283. }
  284. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  285. if (!irq_received)
  286. break;
  287. ret = IRQ_HANDLED;
  288. /* Consume port. Then clear IIR or we'll miss events */
  289. if ((I915_HAS_HOTPLUG(dev)) &&
  290. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  291. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  292. DRM_DEBUG("hotplug event received, stat 0x%08x\n",
  293. hotplug_status);
  294. if (hotplug_status & dev_priv->hotplug_supported_mask)
  295. schedule_work(&dev_priv->hotplug_work);
  296. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  297. I915_READ(PORT_HOTPLUG_STAT);
  298. }
  299. I915_WRITE(IIR, iir);
  300. new_iir = I915_READ(IIR); /* Flush posted writes */
  301. if (dev->primary->master) {
  302. master_priv = dev->primary->master->driver_priv;
  303. if (master_priv->sarea_priv)
  304. master_priv->sarea_priv->last_dispatch =
  305. READ_BREADCRUMB(dev_priv);
  306. }
  307. if (iir & I915_USER_INTERRUPT) {
  308. dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
  309. DRM_WAKEUP(&dev_priv->irq_queue);
  310. }
  311. if (pipea_stats & vblank_status) {
  312. vblank++;
  313. drm_handle_vblank(dev, 0);
  314. }
  315. if (pipeb_stats & vblank_status) {
  316. vblank++;
  317. drm_handle_vblank(dev, 1);
  318. }
  319. if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
  320. (iir & I915_ASLE_INTERRUPT))
  321. opregion_asle_intr(dev);
  322. /* With MSI, interrupts are only generated when iir
  323. * transitions from zero to nonzero. If another bit got
  324. * set while we were handling the existing iir bits, then
  325. * we would never get another interrupt.
  326. *
  327. * This is fine on non-MSI as well, as if we hit this path
  328. * we avoid exiting the interrupt handler only to generate
  329. * another one.
  330. *
  331. * Note that for MSI this could cause a stray interrupt report
  332. * if an interrupt landed in the time between writing IIR and
  333. * the posting read. This should be rare enough to never
  334. * trigger the 99% of 100,000 interrupts test for disabling
  335. * stray interrupts.
  336. */
  337. iir = new_iir;
  338. }
  339. return ret;
  340. }
  341. static int i915_emit_irq(struct drm_device * dev)
  342. {
  343. drm_i915_private_t *dev_priv = dev->dev_private;
  344. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  345. RING_LOCALS;
  346. i915_kernel_lost_context(dev);
  347. DRM_DEBUG("\n");
  348. dev_priv->counter++;
  349. if (dev_priv->counter > 0x7FFFFFFFUL)
  350. dev_priv->counter = 1;
  351. if (master_priv->sarea_priv)
  352. master_priv->sarea_priv->last_enqueue = dev_priv->counter;
  353. BEGIN_LP_RING(4);
  354. OUT_RING(MI_STORE_DWORD_INDEX);
  355. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  356. OUT_RING(dev_priv->counter);
  357. OUT_RING(MI_USER_INTERRUPT);
  358. ADVANCE_LP_RING();
  359. return dev_priv->counter;
  360. }
  361. void i915_user_irq_get(struct drm_device *dev)
  362. {
  363. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  364. unsigned long irqflags;
  365. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  366. if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
  367. if (IS_IGDNG(dev))
  368. igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
  369. else
  370. i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
  371. }
  372. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  373. }
  374. void i915_user_irq_put(struct drm_device *dev)
  375. {
  376. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  377. unsigned long irqflags;
  378. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  379. BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
  380. if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
  381. if (IS_IGDNG(dev))
  382. igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
  383. else
  384. i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
  385. }
  386. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  387. }
  388. static int i915_wait_irq(struct drm_device * dev, int irq_nr)
  389. {
  390. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  391. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  392. int ret = 0;
  393. DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
  394. READ_BREADCRUMB(dev_priv));
  395. if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
  396. if (master_priv->sarea_priv)
  397. master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  398. return 0;
  399. }
  400. if (master_priv->sarea_priv)
  401. master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  402. i915_user_irq_get(dev);
  403. DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
  404. READ_BREADCRUMB(dev_priv) >= irq_nr);
  405. i915_user_irq_put(dev);
  406. if (ret == -EBUSY) {
  407. DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
  408. READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
  409. }
  410. return ret;
  411. }
  412. /* Needs the lock as it touches the ring.
  413. */
  414. int i915_irq_emit(struct drm_device *dev, void *data,
  415. struct drm_file *file_priv)
  416. {
  417. drm_i915_private_t *dev_priv = dev->dev_private;
  418. drm_i915_irq_emit_t *emit = data;
  419. int result;
  420. if (!dev_priv || !dev_priv->ring.virtual_start) {
  421. DRM_ERROR("called with no initialization\n");
  422. return -EINVAL;
  423. }
  424. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  425. mutex_lock(&dev->struct_mutex);
  426. result = i915_emit_irq(dev);
  427. mutex_unlock(&dev->struct_mutex);
  428. if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
  429. DRM_ERROR("copy_to_user\n");
  430. return -EFAULT;
  431. }
  432. return 0;
  433. }
  434. /* Doesn't need the hardware lock.
  435. */
  436. int i915_irq_wait(struct drm_device *dev, void *data,
  437. struct drm_file *file_priv)
  438. {
  439. drm_i915_private_t *dev_priv = dev->dev_private;
  440. drm_i915_irq_wait_t *irqwait = data;
  441. if (!dev_priv) {
  442. DRM_ERROR("called with no initialization\n");
  443. return -EINVAL;
  444. }
  445. return i915_wait_irq(dev, irqwait->irq_seq);
  446. }
  447. /* Called from drm generic code, passed 'crtc' which
  448. * we use as a pipe index
  449. */
  450. int i915_enable_vblank(struct drm_device *dev, int pipe)
  451. {
  452. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  453. unsigned long irqflags;
  454. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  455. u32 pipeconf;
  456. pipeconf = I915_READ(pipeconf_reg);
  457. if (!(pipeconf & PIPEACONF_ENABLE))
  458. return -EINVAL;
  459. if (IS_IGDNG(dev))
  460. return 0;
  461. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  462. if (IS_I965G(dev))
  463. i915_enable_pipestat(dev_priv, pipe,
  464. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  465. else
  466. i915_enable_pipestat(dev_priv, pipe,
  467. PIPE_VBLANK_INTERRUPT_ENABLE);
  468. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  469. return 0;
  470. }
  471. /* Called from drm generic code, passed 'crtc' which
  472. * we use as a pipe index
  473. */
  474. void i915_disable_vblank(struct drm_device *dev, int pipe)
  475. {
  476. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  477. unsigned long irqflags;
  478. if (IS_IGDNG(dev))
  479. return;
  480. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  481. i915_disable_pipestat(dev_priv, pipe,
  482. PIPE_VBLANK_INTERRUPT_ENABLE |
  483. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  484. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  485. }
  486. void i915_enable_interrupt (struct drm_device *dev)
  487. {
  488. struct drm_i915_private *dev_priv = dev->dev_private;
  489. if (!IS_IGDNG(dev))
  490. opregion_enable_asle(dev);
  491. dev_priv->irq_enabled = 1;
  492. }
  493. /* Set the vblank monitor pipe
  494. */
  495. int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  496. struct drm_file *file_priv)
  497. {
  498. drm_i915_private_t *dev_priv = dev->dev_private;
  499. if (!dev_priv) {
  500. DRM_ERROR("called with no initialization\n");
  501. return -EINVAL;
  502. }
  503. return 0;
  504. }
  505. int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  506. struct drm_file *file_priv)
  507. {
  508. drm_i915_private_t *dev_priv = dev->dev_private;
  509. drm_i915_vblank_pipe_t *pipe = data;
  510. if (!dev_priv) {
  511. DRM_ERROR("called with no initialization\n");
  512. return -EINVAL;
  513. }
  514. pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  515. return 0;
  516. }
  517. /**
  518. * Schedule buffer swap at given vertical blank.
  519. */
  520. int i915_vblank_swap(struct drm_device *dev, void *data,
  521. struct drm_file *file_priv)
  522. {
  523. /* The delayed swap mechanism was fundamentally racy, and has been
  524. * removed. The model was that the client requested a delayed flip/swap
  525. * from the kernel, then waited for vblank before continuing to perform
  526. * rendering. The problem was that the kernel might wake the client
  527. * up before it dispatched the vblank swap (since the lock has to be
  528. * held while touching the ringbuffer), in which case the client would
  529. * clear and start the next frame before the swap occurred, and
  530. * flicker would occur in addition to likely missing the vblank.
  531. *
  532. * In the absence of this ioctl, userland falls back to a correct path
  533. * of waiting for a vblank, then dispatching the swap on its own.
  534. * Context switching to userland and back is plenty fast enough for
  535. * meeting the requirements of vblank swapping.
  536. */
  537. return -EINVAL;
  538. }
  539. /* drm_dma.h hooks
  540. */
  541. static void igdng_irq_preinstall(struct drm_device *dev)
  542. {
  543. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  544. I915_WRITE(HWSTAM, 0xeffe);
  545. /* XXX hotplug from PCH */
  546. I915_WRITE(DEIMR, 0xffffffff);
  547. I915_WRITE(DEIER, 0x0);
  548. (void) I915_READ(DEIER);
  549. /* and GT */
  550. I915_WRITE(GTIMR, 0xffffffff);
  551. I915_WRITE(GTIER, 0x0);
  552. (void) I915_READ(GTIER);
  553. }
  554. static int igdng_irq_postinstall(struct drm_device *dev)
  555. {
  556. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  557. /* enable kind of interrupts always enabled */
  558. u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
  559. u32 render_mask = GT_USER_INTERRUPT;
  560. dev_priv->irq_mask_reg = ~display_mask;
  561. dev_priv->de_irq_enable_reg = display_mask;
  562. /* should always can generate irq */
  563. I915_WRITE(DEIIR, I915_READ(DEIIR));
  564. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  565. I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
  566. (void) I915_READ(DEIER);
  567. /* user interrupt should be enabled, but masked initial */
  568. dev_priv->gt_irq_mask_reg = 0xffffffff;
  569. dev_priv->gt_irq_enable_reg = render_mask;
  570. I915_WRITE(GTIIR, I915_READ(GTIIR));
  571. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  572. I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
  573. (void) I915_READ(GTIER);
  574. return 0;
  575. }
  576. void i915_driver_irq_preinstall(struct drm_device * dev)
  577. {
  578. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  579. atomic_set(&dev_priv->irq_received, 0);
  580. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  581. if (IS_IGDNG(dev)) {
  582. igdng_irq_preinstall(dev);
  583. return;
  584. }
  585. if (I915_HAS_HOTPLUG(dev)) {
  586. I915_WRITE(PORT_HOTPLUG_EN, 0);
  587. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  588. }
  589. I915_WRITE(HWSTAM, 0xeffe);
  590. I915_WRITE(PIPEASTAT, 0);
  591. I915_WRITE(PIPEBSTAT, 0);
  592. I915_WRITE(IMR, 0xffffffff);
  593. I915_WRITE(IER, 0x0);
  594. (void) I915_READ(IER);
  595. }
  596. int i915_driver_irq_postinstall(struct drm_device *dev)
  597. {
  598. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  599. u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
  600. DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
  601. dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  602. if (IS_IGDNG(dev))
  603. return igdng_irq_postinstall(dev);
  604. /* Unmask the interrupts that we always want on. */
  605. dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
  606. dev_priv->pipestat[0] = 0;
  607. dev_priv->pipestat[1] = 0;
  608. if (I915_HAS_HOTPLUG(dev)) {
  609. u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  610. /* Leave other bits alone */
  611. hotplug_en |= HOTPLUG_EN_MASK;
  612. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  613. dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
  614. TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
  615. SDVOB_HOTPLUG_INT_STATUS;
  616. if (IS_G4X(dev)) {
  617. dev_priv->hotplug_supported_mask |=
  618. HDMIB_HOTPLUG_INT_STATUS |
  619. HDMIC_HOTPLUG_INT_STATUS |
  620. HDMID_HOTPLUG_INT_STATUS;
  621. }
  622. /* Enable in IER... */
  623. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  624. /* and unmask in IMR */
  625. i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
  626. }
  627. /* Disable pipe interrupt enables, clear pending pipe status */
  628. I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
  629. I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
  630. /* Clear pending interrupt status */
  631. I915_WRITE(IIR, I915_READ(IIR));
  632. I915_WRITE(IER, enable_mask);
  633. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  634. (void) I915_READ(IER);
  635. opregion_enable_asle(dev);
  636. return 0;
  637. }
  638. static void igdng_irq_uninstall(struct drm_device *dev)
  639. {
  640. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  641. I915_WRITE(HWSTAM, 0xffffffff);
  642. I915_WRITE(DEIMR, 0xffffffff);
  643. I915_WRITE(DEIER, 0x0);
  644. I915_WRITE(DEIIR, I915_READ(DEIIR));
  645. I915_WRITE(GTIMR, 0xffffffff);
  646. I915_WRITE(GTIER, 0x0);
  647. I915_WRITE(GTIIR, I915_READ(GTIIR));
  648. }
  649. void i915_driver_irq_uninstall(struct drm_device * dev)
  650. {
  651. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  652. if (!dev_priv)
  653. return;
  654. dev_priv->vblank_pipe = 0;
  655. if (IS_IGDNG(dev)) {
  656. igdng_irq_uninstall(dev);
  657. return;
  658. }
  659. if (I915_HAS_HOTPLUG(dev)) {
  660. I915_WRITE(PORT_HOTPLUG_EN, 0);
  661. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  662. }
  663. I915_WRITE(HWSTAM, 0xffffffff);
  664. I915_WRITE(PIPEASTAT, 0);
  665. I915_WRITE(PIPEBSTAT, 0);
  666. I915_WRITE(IMR, 0xffffffff);
  667. I915_WRITE(IER, 0x0);
  668. I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
  669. I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
  670. I915_WRITE(IIR, I915_READ(IIR));
  671. }