i915_dma.c 36 KB

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  1. /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "drm_crtc_helper.h"
  31. #include "intel_drv.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #define I915_DRV "i915_drv"
  35. /* Really want an OS-independent resettable timer. Would like to have
  36. * this loop run for (eg) 3 sec, but have the timer reset every time
  37. * the head pointer changes, so that EBUSY only happens if the ring
  38. * actually stalls for (eg) 3 seconds.
  39. */
  40. int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  41. {
  42. drm_i915_private_t *dev_priv = dev->dev_private;
  43. drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  44. u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  45. u32 last_acthd = I915_READ(acthd_reg);
  46. u32 acthd;
  47. u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  48. int i;
  49. for (i = 0; i < 100000; i++) {
  50. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51. acthd = I915_READ(acthd_reg);
  52. ring->space = ring->head - (ring->tail + 8);
  53. if (ring->space < 0)
  54. ring->space += ring->Size;
  55. if (ring->space >= n)
  56. return 0;
  57. if (dev->primary->master) {
  58. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  59. if (master_priv->sarea_priv)
  60. master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  61. }
  62. if (ring->head != last_head)
  63. i = 0;
  64. if (acthd != last_acthd)
  65. i = 0;
  66. last_head = ring->head;
  67. last_acthd = acthd;
  68. msleep_interruptible(10);
  69. }
  70. return -EBUSY;
  71. }
  72. /**
  73. * Sets up the hardware status page for devices that need a physical address
  74. * in the register.
  75. */
  76. static int i915_init_phys_hws(struct drm_device *dev)
  77. {
  78. drm_i915_private_t *dev_priv = dev->dev_private;
  79. /* Program Hardware Status Page */
  80. dev_priv->status_page_dmah =
  81. drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  82. if (!dev_priv->status_page_dmah) {
  83. DRM_ERROR("Can not allocate hardware status page\n");
  84. return -ENOMEM;
  85. }
  86. dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
  87. dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  88. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  89. I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  90. DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n");
  91. return 0;
  92. }
  93. /**
  94. * Frees the hardware status page, whether it's a physical address or a virtual
  95. * address set up by the X Server.
  96. */
  97. static void i915_free_hws(struct drm_device *dev)
  98. {
  99. drm_i915_private_t *dev_priv = dev->dev_private;
  100. if (dev_priv->status_page_dmah) {
  101. drm_pci_free(dev, dev_priv->status_page_dmah);
  102. dev_priv->status_page_dmah = NULL;
  103. }
  104. if (dev_priv->status_gfx_addr) {
  105. dev_priv->status_gfx_addr = 0;
  106. drm_core_ioremapfree(&dev_priv->hws_map, dev);
  107. }
  108. /* Need to rewrite hardware status page */
  109. I915_WRITE(HWS_PGA, 0x1ffff000);
  110. }
  111. void i915_kernel_lost_context(struct drm_device * dev)
  112. {
  113. drm_i915_private_t *dev_priv = dev->dev_private;
  114. struct drm_i915_master_private *master_priv;
  115. drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  116. /*
  117. * We should never lose context on the ring with modesetting
  118. * as we don't expose it to userspace
  119. */
  120. if (drm_core_check_feature(dev, DRIVER_MODESET))
  121. return;
  122. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  123. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  124. ring->space = ring->head - (ring->tail + 8);
  125. if (ring->space < 0)
  126. ring->space += ring->Size;
  127. if (!dev->primary->master)
  128. return;
  129. master_priv = dev->primary->master->driver_priv;
  130. if (ring->head == ring->tail && master_priv->sarea_priv)
  131. master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  132. }
  133. static int i915_dma_cleanup(struct drm_device * dev)
  134. {
  135. drm_i915_private_t *dev_priv = dev->dev_private;
  136. /* Make sure interrupts are disabled here because the uninstall ioctl
  137. * may not have been called from userspace and after dev_private
  138. * is freed, it's too late.
  139. */
  140. if (dev->irq_enabled)
  141. drm_irq_uninstall(dev);
  142. if (dev_priv->ring.virtual_start) {
  143. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  144. dev_priv->ring.virtual_start = NULL;
  145. dev_priv->ring.map.handle = NULL;
  146. dev_priv->ring.map.size = 0;
  147. }
  148. /* Clear the HWS virtual address at teardown */
  149. if (I915_NEED_GFX_HWS(dev))
  150. i915_free_hws(dev);
  151. return 0;
  152. }
  153. static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
  154. {
  155. drm_i915_private_t *dev_priv = dev->dev_private;
  156. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  157. master_priv->sarea = drm_getsarea(dev);
  158. if (master_priv->sarea) {
  159. master_priv->sarea_priv = (drm_i915_sarea_t *)
  160. ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
  161. } else {
  162. DRM_DEBUG_DRIVER(I915_DRV,
  163. "sarea not found assuming DRI2 userspace\n");
  164. }
  165. if (init->ring_size != 0) {
  166. if (dev_priv->ring.ring_obj != NULL) {
  167. i915_dma_cleanup(dev);
  168. DRM_ERROR("Client tried to initialize ringbuffer in "
  169. "GEM mode\n");
  170. return -EINVAL;
  171. }
  172. dev_priv->ring.Size = init->ring_size;
  173. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  174. dev_priv->ring.map.offset = init->ring_start;
  175. dev_priv->ring.map.size = init->ring_size;
  176. dev_priv->ring.map.type = 0;
  177. dev_priv->ring.map.flags = 0;
  178. dev_priv->ring.map.mtrr = 0;
  179. drm_core_ioremap_wc(&dev_priv->ring.map, dev);
  180. if (dev_priv->ring.map.handle == NULL) {
  181. i915_dma_cleanup(dev);
  182. DRM_ERROR("can not ioremap virtual address for"
  183. " ring buffer\n");
  184. return -ENOMEM;
  185. }
  186. }
  187. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  188. dev_priv->cpp = init->cpp;
  189. dev_priv->back_offset = init->back_offset;
  190. dev_priv->front_offset = init->front_offset;
  191. dev_priv->current_page = 0;
  192. if (master_priv->sarea_priv)
  193. master_priv->sarea_priv->pf_current_page = 0;
  194. /* Allow hardware batchbuffers unless told otherwise.
  195. */
  196. dev_priv->allow_batchbuffer = 1;
  197. return 0;
  198. }
  199. static int i915_dma_resume(struct drm_device * dev)
  200. {
  201. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  202. DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__);
  203. if (dev_priv->ring.map.handle == NULL) {
  204. DRM_ERROR("can not ioremap virtual address for"
  205. " ring buffer\n");
  206. return -ENOMEM;
  207. }
  208. /* Program Hardware Status Page */
  209. if (!dev_priv->hw_status_page) {
  210. DRM_ERROR("Can not find hardware status page\n");
  211. return -EINVAL;
  212. }
  213. DRM_DEBUG_DRIVER(I915_DRV, "hw status page @ %p\n",
  214. dev_priv->hw_status_page);
  215. if (dev_priv->status_gfx_addr != 0)
  216. I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
  217. else
  218. I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  219. DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n");
  220. return 0;
  221. }
  222. static int i915_dma_init(struct drm_device *dev, void *data,
  223. struct drm_file *file_priv)
  224. {
  225. drm_i915_init_t *init = data;
  226. int retcode = 0;
  227. switch (init->func) {
  228. case I915_INIT_DMA:
  229. retcode = i915_initialize(dev, init);
  230. break;
  231. case I915_CLEANUP_DMA:
  232. retcode = i915_dma_cleanup(dev);
  233. break;
  234. case I915_RESUME_DMA:
  235. retcode = i915_dma_resume(dev);
  236. break;
  237. default:
  238. retcode = -EINVAL;
  239. break;
  240. }
  241. return retcode;
  242. }
  243. /* Implement basically the same security restrictions as hardware does
  244. * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
  245. *
  246. * Most of the calculations below involve calculating the size of a
  247. * particular instruction. It's important to get the size right as
  248. * that tells us where the next instruction to check is. Any illegal
  249. * instruction detected will be given a size of zero, which is a
  250. * signal to abort the rest of the buffer.
  251. */
  252. static int do_validate_cmd(int cmd)
  253. {
  254. switch (((cmd >> 29) & 0x7)) {
  255. case 0x0:
  256. switch ((cmd >> 23) & 0x3f) {
  257. case 0x0:
  258. return 1; /* MI_NOOP */
  259. case 0x4:
  260. return 1; /* MI_FLUSH */
  261. default:
  262. return 0; /* disallow everything else */
  263. }
  264. break;
  265. case 0x1:
  266. return 0; /* reserved */
  267. case 0x2:
  268. return (cmd & 0xff) + 2; /* 2d commands */
  269. case 0x3:
  270. if (((cmd >> 24) & 0x1f) <= 0x18)
  271. return 1;
  272. switch ((cmd >> 24) & 0x1f) {
  273. case 0x1c:
  274. return 1;
  275. case 0x1d:
  276. switch ((cmd >> 16) & 0xff) {
  277. case 0x3:
  278. return (cmd & 0x1f) + 2;
  279. case 0x4:
  280. return (cmd & 0xf) + 2;
  281. default:
  282. return (cmd & 0xffff) + 2;
  283. }
  284. case 0x1e:
  285. if (cmd & (1 << 23))
  286. return (cmd & 0xffff) + 1;
  287. else
  288. return 1;
  289. case 0x1f:
  290. if ((cmd & (1 << 23)) == 0) /* inline vertices */
  291. return (cmd & 0x1ffff) + 2;
  292. else if (cmd & (1 << 17)) /* indirect random */
  293. if ((cmd & 0xffff) == 0)
  294. return 0; /* unknown length, too hard */
  295. else
  296. return (((cmd & 0xffff) + 1) / 2) + 1;
  297. else
  298. return 2; /* indirect sequential */
  299. default:
  300. return 0;
  301. }
  302. default:
  303. return 0;
  304. }
  305. return 0;
  306. }
  307. static int validate_cmd(int cmd)
  308. {
  309. int ret = do_validate_cmd(cmd);
  310. /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
  311. return ret;
  312. }
  313. static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
  314. {
  315. drm_i915_private_t *dev_priv = dev->dev_private;
  316. int i;
  317. RING_LOCALS;
  318. if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
  319. return -EINVAL;
  320. BEGIN_LP_RING((dwords+1)&~1);
  321. for (i = 0; i < dwords;) {
  322. int cmd, sz;
  323. cmd = buffer[i];
  324. if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
  325. return -EINVAL;
  326. OUT_RING(cmd);
  327. while (++i, --sz) {
  328. OUT_RING(buffer[i]);
  329. }
  330. }
  331. if (dwords & 1)
  332. OUT_RING(0);
  333. ADVANCE_LP_RING();
  334. return 0;
  335. }
  336. int
  337. i915_emit_box(struct drm_device *dev,
  338. struct drm_clip_rect *boxes,
  339. int i, int DR1, int DR4)
  340. {
  341. drm_i915_private_t *dev_priv = dev->dev_private;
  342. struct drm_clip_rect box = boxes[i];
  343. RING_LOCALS;
  344. if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
  345. DRM_ERROR("Bad box %d,%d..%d,%d\n",
  346. box.x1, box.y1, box.x2, box.y2);
  347. return -EINVAL;
  348. }
  349. if (IS_I965G(dev)) {
  350. BEGIN_LP_RING(4);
  351. OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
  352. OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
  353. OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
  354. OUT_RING(DR4);
  355. ADVANCE_LP_RING();
  356. } else {
  357. BEGIN_LP_RING(6);
  358. OUT_RING(GFX_OP_DRAWRECT_INFO);
  359. OUT_RING(DR1);
  360. OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
  361. OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
  362. OUT_RING(DR4);
  363. OUT_RING(0);
  364. ADVANCE_LP_RING();
  365. }
  366. return 0;
  367. }
  368. /* XXX: Emitting the counter should really be moved to part of the IRQ
  369. * emit. For now, do it in both places:
  370. */
  371. static void i915_emit_breadcrumb(struct drm_device *dev)
  372. {
  373. drm_i915_private_t *dev_priv = dev->dev_private;
  374. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  375. RING_LOCALS;
  376. dev_priv->counter++;
  377. if (dev_priv->counter > 0x7FFFFFFFUL)
  378. dev_priv->counter = 0;
  379. if (master_priv->sarea_priv)
  380. master_priv->sarea_priv->last_enqueue = dev_priv->counter;
  381. BEGIN_LP_RING(4);
  382. OUT_RING(MI_STORE_DWORD_INDEX);
  383. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  384. OUT_RING(dev_priv->counter);
  385. OUT_RING(0);
  386. ADVANCE_LP_RING();
  387. }
  388. static int i915_dispatch_cmdbuffer(struct drm_device * dev,
  389. drm_i915_cmdbuffer_t *cmd,
  390. struct drm_clip_rect *cliprects,
  391. void *cmdbuf)
  392. {
  393. int nbox = cmd->num_cliprects;
  394. int i = 0, count, ret;
  395. if (cmd->sz & 0x3) {
  396. DRM_ERROR("alignment");
  397. return -EINVAL;
  398. }
  399. i915_kernel_lost_context(dev);
  400. count = nbox ? nbox : 1;
  401. for (i = 0; i < count; i++) {
  402. if (i < nbox) {
  403. ret = i915_emit_box(dev, cliprects, i,
  404. cmd->DR1, cmd->DR4);
  405. if (ret)
  406. return ret;
  407. }
  408. ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
  409. if (ret)
  410. return ret;
  411. }
  412. i915_emit_breadcrumb(dev);
  413. return 0;
  414. }
  415. static int i915_dispatch_batchbuffer(struct drm_device * dev,
  416. drm_i915_batchbuffer_t * batch,
  417. struct drm_clip_rect *cliprects)
  418. {
  419. drm_i915_private_t *dev_priv = dev->dev_private;
  420. int nbox = batch->num_cliprects;
  421. int i = 0, count;
  422. RING_LOCALS;
  423. if ((batch->start | batch->used) & 0x7) {
  424. DRM_ERROR("alignment");
  425. return -EINVAL;
  426. }
  427. i915_kernel_lost_context(dev);
  428. count = nbox ? nbox : 1;
  429. for (i = 0; i < count; i++) {
  430. if (i < nbox) {
  431. int ret = i915_emit_box(dev, cliprects, i,
  432. batch->DR1, batch->DR4);
  433. if (ret)
  434. return ret;
  435. }
  436. if (!IS_I830(dev) && !IS_845G(dev)) {
  437. BEGIN_LP_RING(2);
  438. if (IS_I965G(dev)) {
  439. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
  440. OUT_RING(batch->start);
  441. } else {
  442. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
  443. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  444. }
  445. ADVANCE_LP_RING();
  446. } else {
  447. BEGIN_LP_RING(4);
  448. OUT_RING(MI_BATCH_BUFFER);
  449. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  450. OUT_RING(batch->start + batch->used - 4);
  451. OUT_RING(0);
  452. ADVANCE_LP_RING();
  453. }
  454. }
  455. i915_emit_breadcrumb(dev);
  456. return 0;
  457. }
  458. static int i915_dispatch_flip(struct drm_device * dev)
  459. {
  460. drm_i915_private_t *dev_priv = dev->dev_private;
  461. struct drm_i915_master_private *master_priv =
  462. dev->primary->master->driver_priv;
  463. RING_LOCALS;
  464. if (!master_priv->sarea_priv)
  465. return -EINVAL;
  466. DRM_DEBUG_DRIVER(I915_DRV, "%s: page=%d pfCurrentPage=%d\n",
  467. __func__,
  468. dev_priv->current_page,
  469. master_priv->sarea_priv->pf_current_page);
  470. i915_kernel_lost_context(dev);
  471. BEGIN_LP_RING(2);
  472. OUT_RING(MI_FLUSH | MI_READ_FLUSH);
  473. OUT_RING(0);
  474. ADVANCE_LP_RING();
  475. BEGIN_LP_RING(6);
  476. OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
  477. OUT_RING(0);
  478. if (dev_priv->current_page == 0) {
  479. OUT_RING(dev_priv->back_offset);
  480. dev_priv->current_page = 1;
  481. } else {
  482. OUT_RING(dev_priv->front_offset);
  483. dev_priv->current_page = 0;
  484. }
  485. OUT_RING(0);
  486. ADVANCE_LP_RING();
  487. BEGIN_LP_RING(2);
  488. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
  489. OUT_RING(0);
  490. ADVANCE_LP_RING();
  491. master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
  492. BEGIN_LP_RING(4);
  493. OUT_RING(MI_STORE_DWORD_INDEX);
  494. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  495. OUT_RING(dev_priv->counter);
  496. OUT_RING(0);
  497. ADVANCE_LP_RING();
  498. master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  499. return 0;
  500. }
  501. static int i915_quiescent(struct drm_device * dev)
  502. {
  503. drm_i915_private_t *dev_priv = dev->dev_private;
  504. i915_kernel_lost_context(dev);
  505. return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
  506. }
  507. static int i915_flush_ioctl(struct drm_device *dev, void *data,
  508. struct drm_file *file_priv)
  509. {
  510. int ret;
  511. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  512. mutex_lock(&dev->struct_mutex);
  513. ret = i915_quiescent(dev);
  514. mutex_unlock(&dev->struct_mutex);
  515. return ret;
  516. }
  517. static int i915_batchbuffer(struct drm_device *dev, void *data,
  518. struct drm_file *file_priv)
  519. {
  520. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  521. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  522. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  523. master_priv->sarea_priv;
  524. drm_i915_batchbuffer_t *batch = data;
  525. int ret;
  526. struct drm_clip_rect *cliprects = NULL;
  527. if (!dev_priv->allow_batchbuffer) {
  528. DRM_ERROR("Batchbuffer ioctl disabled\n");
  529. return -EINVAL;
  530. }
  531. DRM_DEBUG_DRIVER(I915_DRV,
  532. "i915 batchbuffer, start %x used %d cliprects %d\n",
  533. batch->start, batch->used, batch->num_cliprects);
  534. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  535. if (batch->num_cliprects < 0)
  536. return -EINVAL;
  537. if (batch->num_cliprects) {
  538. cliprects = drm_calloc(batch->num_cliprects,
  539. sizeof(struct drm_clip_rect),
  540. DRM_MEM_DRIVER);
  541. if (cliprects == NULL)
  542. return -ENOMEM;
  543. ret = copy_from_user(cliprects, batch->cliprects,
  544. batch->num_cliprects *
  545. sizeof(struct drm_clip_rect));
  546. if (ret != 0)
  547. goto fail_free;
  548. }
  549. mutex_lock(&dev->struct_mutex);
  550. ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
  551. mutex_unlock(&dev->struct_mutex);
  552. if (sarea_priv)
  553. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  554. fail_free:
  555. drm_free(cliprects,
  556. batch->num_cliprects * sizeof(struct drm_clip_rect),
  557. DRM_MEM_DRIVER);
  558. return ret;
  559. }
  560. static int i915_cmdbuffer(struct drm_device *dev, void *data,
  561. struct drm_file *file_priv)
  562. {
  563. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  564. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  565. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  566. master_priv->sarea_priv;
  567. drm_i915_cmdbuffer_t *cmdbuf = data;
  568. struct drm_clip_rect *cliprects = NULL;
  569. void *batch_data;
  570. int ret;
  571. DRM_DEBUG_DRIVER(I915_DRV,
  572. "i915 cmdbuffer, buf %p sz %d cliprects %d\n",
  573. cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
  574. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  575. if (cmdbuf->num_cliprects < 0)
  576. return -EINVAL;
  577. batch_data = drm_alloc(cmdbuf->sz, DRM_MEM_DRIVER);
  578. if (batch_data == NULL)
  579. return -ENOMEM;
  580. ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
  581. if (ret != 0)
  582. goto fail_batch_free;
  583. if (cmdbuf->num_cliprects) {
  584. cliprects = drm_calloc(cmdbuf->num_cliprects,
  585. sizeof(struct drm_clip_rect),
  586. DRM_MEM_DRIVER);
  587. if (cliprects == NULL)
  588. goto fail_batch_free;
  589. ret = copy_from_user(cliprects, cmdbuf->cliprects,
  590. cmdbuf->num_cliprects *
  591. sizeof(struct drm_clip_rect));
  592. if (ret != 0)
  593. goto fail_clip_free;
  594. }
  595. mutex_lock(&dev->struct_mutex);
  596. ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
  597. mutex_unlock(&dev->struct_mutex);
  598. if (ret) {
  599. DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
  600. goto fail_clip_free;
  601. }
  602. if (sarea_priv)
  603. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  604. fail_clip_free:
  605. drm_free(cliprects,
  606. cmdbuf->num_cliprects * sizeof(struct drm_clip_rect),
  607. DRM_MEM_DRIVER);
  608. fail_batch_free:
  609. drm_free(batch_data, cmdbuf->sz, DRM_MEM_DRIVER);
  610. return ret;
  611. }
  612. static int i915_flip_bufs(struct drm_device *dev, void *data,
  613. struct drm_file *file_priv)
  614. {
  615. int ret;
  616. DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__);
  617. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  618. mutex_lock(&dev->struct_mutex);
  619. ret = i915_dispatch_flip(dev);
  620. mutex_unlock(&dev->struct_mutex);
  621. return ret;
  622. }
  623. static int i915_getparam(struct drm_device *dev, void *data,
  624. struct drm_file *file_priv)
  625. {
  626. drm_i915_private_t *dev_priv = dev->dev_private;
  627. drm_i915_getparam_t *param = data;
  628. int value;
  629. if (!dev_priv) {
  630. DRM_ERROR("called with no initialization\n");
  631. return -EINVAL;
  632. }
  633. switch (param->param) {
  634. case I915_PARAM_IRQ_ACTIVE:
  635. value = dev->pdev->irq ? 1 : 0;
  636. break;
  637. case I915_PARAM_ALLOW_BATCHBUFFER:
  638. value = dev_priv->allow_batchbuffer ? 1 : 0;
  639. break;
  640. case I915_PARAM_LAST_DISPATCH:
  641. value = READ_BREADCRUMB(dev_priv);
  642. break;
  643. case I915_PARAM_CHIPSET_ID:
  644. value = dev->pci_device;
  645. break;
  646. case I915_PARAM_HAS_GEM:
  647. value = dev_priv->has_gem;
  648. break;
  649. case I915_PARAM_NUM_FENCES_AVAIL:
  650. value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  651. break;
  652. default:
  653. DRM_DEBUG_DRIVER(I915_DRV, "Unknown parameter %d\n",
  654. param->param);
  655. return -EINVAL;
  656. }
  657. if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
  658. DRM_ERROR("DRM_COPY_TO_USER failed\n");
  659. return -EFAULT;
  660. }
  661. return 0;
  662. }
  663. static int i915_setparam(struct drm_device *dev, void *data,
  664. struct drm_file *file_priv)
  665. {
  666. drm_i915_private_t *dev_priv = dev->dev_private;
  667. drm_i915_setparam_t *param = data;
  668. if (!dev_priv) {
  669. DRM_ERROR("called with no initialization\n");
  670. return -EINVAL;
  671. }
  672. switch (param->param) {
  673. case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
  674. break;
  675. case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
  676. dev_priv->tex_lru_log_granularity = param->value;
  677. break;
  678. case I915_SETPARAM_ALLOW_BATCHBUFFER:
  679. dev_priv->allow_batchbuffer = param->value;
  680. break;
  681. case I915_SETPARAM_NUM_USED_FENCES:
  682. if (param->value > dev_priv->num_fence_regs ||
  683. param->value < 0)
  684. return -EINVAL;
  685. /* Userspace can use first N regs */
  686. dev_priv->fence_reg_start = param->value;
  687. break;
  688. default:
  689. DRM_DEBUG_DRIVER(I915_DRV, "unknown parameter %d\n",
  690. param->param);
  691. return -EINVAL;
  692. }
  693. return 0;
  694. }
  695. static int i915_set_status_page(struct drm_device *dev, void *data,
  696. struct drm_file *file_priv)
  697. {
  698. drm_i915_private_t *dev_priv = dev->dev_private;
  699. drm_i915_hws_addr_t *hws = data;
  700. if (!I915_NEED_GFX_HWS(dev))
  701. return -EINVAL;
  702. if (!dev_priv) {
  703. DRM_ERROR("called with no initialization\n");
  704. return -EINVAL;
  705. }
  706. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  707. WARN(1, "tried to set status page when mode setting active\n");
  708. return 0;
  709. }
  710. printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
  711. dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
  712. dev_priv->hws_map.offset = dev->agp->base + hws->addr;
  713. dev_priv->hws_map.size = 4*1024;
  714. dev_priv->hws_map.type = 0;
  715. dev_priv->hws_map.flags = 0;
  716. dev_priv->hws_map.mtrr = 0;
  717. drm_core_ioremap_wc(&dev_priv->hws_map, dev);
  718. if (dev_priv->hws_map.handle == NULL) {
  719. i915_dma_cleanup(dev);
  720. dev_priv->status_gfx_addr = 0;
  721. DRM_ERROR("can not ioremap virtual address for"
  722. " G33 hw status page\n");
  723. return -ENOMEM;
  724. }
  725. dev_priv->hw_status_page = dev_priv->hws_map.handle;
  726. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  727. I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
  728. DRM_DEBUG_DRIVER(I915_DRV, "load hws HWS_PGA with gfx mem 0x%x\n",
  729. dev_priv->status_gfx_addr);
  730. DRM_DEBUG_DRIVER(I915_DRV, "load hws at %p\n",
  731. dev_priv->hw_status_page);
  732. return 0;
  733. }
  734. /**
  735. * i915_probe_agp - get AGP bootup configuration
  736. * @pdev: PCI device
  737. * @aperture_size: returns AGP aperture configured size
  738. * @preallocated_size: returns size of BIOS preallocated AGP space
  739. *
  740. * Since Intel integrated graphics are UMA, the BIOS has to set aside
  741. * some RAM for the framebuffer at early boot. This code figures out
  742. * how much was set aside so we can use it for our own purposes.
  743. */
  744. static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size,
  745. unsigned long *preallocated_size)
  746. {
  747. struct pci_dev *bridge_dev;
  748. u16 tmp = 0;
  749. unsigned long overhead;
  750. unsigned long stolen;
  751. bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
  752. if (!bridge_dev) {
  753. DRM_ERROR("bridge device not found\n");
  754. return -1;
  755. }
  756. /* Get the fb aperture size and "stolen" memory amount. */
  757. pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
  758. pci_dev_put(bridge_dev);
  759. *aperture_size = 1024 * 1024;
  760. *preallocated_size = 1024 * 1024;
  761. switch (dev->pdev->device) {
  762. case PCI_DEVICE_ID_INTEL_82830_CGC:
  763. case PCI_DEVICE_ID_INTEL_82845G_IG:
  764. case PCI_DEVICE_ID_INTEL_82855GM_IG:
  765. case PCI_DEVICE_ID_INTEL_82865_IG:
  766. if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
  767. *aperture_size *= 64;
  768. else
  769. *aperture_size *= 128;
  770. break;
  771. default:
  772. /* 9xx supports large sizes, just look at the length */
  773. *aperture_size = pci_resource_len(dev->pdev, 2);
  774. break;
  775. }
  776. /*
  777. * Some of the preallocated space is taken by the GTT
  778. * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
  779. */
  780. if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev))
  781. overhead = 4096;
  782. else
  783. overhead = (*aperture_size / 1024) + 4096;
  784. switch (tmp & INTEL_GMCH_GMS_MASK) {
  785. case INTEL_855_GMCH_GMS_DISABLED:
  786. DRM_ERROR("video memory is disabled\n");
  787. return -1;
  788. case INTEL_855_GMCH_GMS_STOLEN_1M:
  789. stolen = 1 * 1024 * 1024;
  790. break;
  791. case INTEL_855_GMCH_GMS_STOLEN_4M:
  792. stolen = 4 * 1024 * 1024;
  793. break;
  794. case INTEL_855_GMCH_GMS_STOLEN_8M:
  795. stolen = 8 * 1024 * 1024;
  796. break;
  797. case INTEL_855_GMCH_GMS_STOLEN_16M:
  798. stolen = 16 * 1024 * 1024;
  799. break;
  800. case INTEL_855_GMCH_GMS_STOLEN_32M:
  801. stolen = 32 * 1024 * 1024;
  802. break;
  803. case INTEL_915G_GMCH_GMS_STOLEN_48M:
  804. stolen = 48 * 1024 * 1024;
  805. break;
  806. case INTEL_915G_GMCH_GMS_STOLEN_64M:
  807. stolen = 64 * 1024 * 1024;
  808. break;
  809. case INTEL_GMCH_GMS_STOLEN_128M:
  810. stolen = 128 * 1024 * 1024;
  811. break;
  812. case INTEL_GMCH_GMS_STOLEN_256M:
  813. stolen = 256 * 1024 * 1024;
  814. break;
  815. case INTEL_GMCH_GMS_STOLEN_96M:
  816. stolen = 96 * 1024 * 1024;
  817. break;
  818. case INTEL_GMCH_GMS_STOLEN_160M:
  819. stolen = 160 * 1024 * 1024;
  820. break;
  821. case INTEL_GMCH_GMS_STOLEN_224M:
  822. stolen = 224 * 1024 * 1024;
  823. break;
  824. case INTEL_GMCH_GMS_STOLEN_352M:
  825. stolen = 352 * 1024 * 1024;
  826. break;
  827. default:
  828. DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  829. tmp & INTEL_GMCH_GMS_MASK);
  830. return -1;
  831. }
  832. *preallocated_size = stolen - overhead;
  833. return 0;
  834. }
  835. static int i915_load_modeset_init(struct drm_device *dev)
  836. {
  837. struct drm_i915_private *dev_priv = dev->dev_private;
  838. unsigned long agp_size, prealloc_size;
  839. int fb_bar = IS_I9XX(dev) ? 2 : 0;
  840. int ret = 0;
  841. dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
  842. 0xff000000;
  843. if (IS_MOBILE(dev) || IS_I9XX(dev))
  844. dev_priv->cursor_needs_physical = true;
  845. else
  846. dev_priv->cursor_needs_physical = false;
  847. if (IS_I965G(dev) || IS_G33(dev))
  848. dev_priv->cursor_needs_physical = false;
  849. ret = i915_probe_agp(dev, &agp_size, &prealloc_size);
  850. if (ret)
  851. goto out;
  852. /* Basic memrange allocator for stolen space (aka vram) */
  853. drm_mm_init(&dev_priv->vram, 0, prealloc_size);
  854. /* Let GEM Manage from end of prealloc space to end of aperture.
  855. *
  856. * However, leave one page at the end still bound to the scratch page.
  857. * There are a number of places where the hardware apparently
  858. * prefetches past the end of the object, and we've seen multiple
  859. * hangs with the GPU head pointer stuck in a batchbuffer bound
  860. * at the last page of the aperture. One page should be enough to
  861. * keep any prefetching inside of the aperture.
  862. */
  863. i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
  864. ret = i915_gem_init_ringbuffer(dev);
  865. if (ret)
  866. goto out;
  867. /* Allow hardware batchbuffers unless told otherwise.
  868. */
  869. dev_priv->allow_batchbuffer = 1;
  870. ret = intel_init_bios(dev);
  871. if (ret)
  872. DRM_INFO("failed to find VBIOS tables\n");
  873. ret = drm_irq_install(dev);
  874. if (ret)
  875. goto destroy_ringbuffer;
  876. /* Always safe in the mode setting case. */
  877. /* FIXME: do pre/post-mode set stuff in core KMS code */
  878. dev->vblank_disable_allowed = 1;
  879. /*
  880. * Initialize the hardware status page IRQ location.
  881. */
  882. I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
  883. intel_modeset_init(dev);
  884. drm_helper_initial_config(dev);
  885. return 0;
  886. destroy_ringbuffer:
  887. i915_gem_cleanup_ringbuffer(dev);
  888. out:
  889. return ret;
  890. }
  891. int i915_master_create(struct drm_device *dev, struct drm_master *master)
  892. {
  893. struct drm_i915_master_private *master_priv;
  894. master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
  895. if (!master_priv)
  896. return -ENOMEM;
  897. master->driver_priv = master_priv;
  898. return 0;
  899. }
  900. void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
  901. {
  902. struct drm_i915_master_private *master_priv = master->driver_priv;
  903. if (!master_priv)
  904. return;
  905. drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
  906. master->driver_priv = NULL;
  907. }
  908. /**
  909. * i915_driver_load - setup chip and create an initial config
  910. * @dev: DRM device
  911. * @flags: startup flags
  912. *
  913. * The driver load routine has to do several things:
  914. * - drive output discovery via intel_modeset_init()
  915. * - initialize the memory manager
  916. * - allocate initial config memory
  917. * - setup the DRM framebuffer with the allocated memory
  918. */
  919. int i915_driver_load(struct drm_device *dev, unsigned long flags)
  920. {
  921. struct drm_i915_private *dev_priv = dev->dev_private;
  922. resource_size_t base, size;
  923. int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
  924. /* i915 has 4 more counters */
  925. dev->counters += 4;
  926. dev->types[6] = _DRM_STAT_IRQ;
  927. dev->types[7] = _DRM_STAT_PRIMARY;
  928. dev->types[8] = _DRM_STAT_SECONDARY;
  929. dev->types[9] = _DRM_STAT_DMA;
  930. dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
  931. if (dev_priv == NULL)
  932. return -ENOMEM;
  933. memset(dev_priv, 0, sizeof(drm_i915_private_t));
  934. dev->dev_private = (void *)dev_priv;
  935. dev_priv->dev = dev;
  936. /* Add register map (needed for suspend/resume) */
  937. base = drm_get_resource_start(dev, mmio_bar);
  938. size = drm_get_resource_len(dev, mmio_bar);
  939. dev_priv->regs = ioremap(base, size);
  940. if (!dev_priv->regs) {
  941. DRM_ERROR("failed to map registers\n");
  942. ret = -EIO;
  943. goto free_priv;
  944. }
  945. dev_priv->mm.gtt_mapping =
  946. io_mapping_create_wc(dev->agp->base,
  947. dev->agp->agp_info.aper_size * 1024*1024);
  948. if (dev_priv->mm.gtt_mapping == NULL) {
  949. ret = -EIO;
  950. goto out_rmmap;
  951. }
  952. /* Set up a WC MTRR for non-PAT systems. This is more common than
  953. * one would think, because the kernel disables PAT on first
  954. * generation Core chips because WC PAT gets overridden by a UC
  955. * MTRR if present. Even if a UC MTRR isn't present.
  956. */
  957. dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
  958. dev->agp->agp_info.aper_size *
  959. 1024 * 1024,
  960. MTRR_TYPE_WRCOMB, 1);
  961. if (dev_priv->mm.gtt_mtrr < 0) {
  962. DRM_INFO("MTRR allocation failed. Graphics "
  963. "performance may suffer.\n");
  964. }
  965. #ifdef CONFIG_HIGHMEM64G
  966. /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
  967. dev_priv->has_gem = 0;
  968. #else
  969. /* enable GEM by default */
  970. dev_priv->has_gem = 1;
  971. #endif
  972. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  973. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  974. if (IS_G4X(dev) || IS_IGDNG(dev)) {
  975. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  976. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  977. }
  978. i915_gem_load(dev);
  979. /* Init HWS */
  980. if (!I915_NEED_GFX_HWS(dev)) {
  981. ret = i915_init_phys_hws(dev);
  982. if (ret != 0)
  983. goto out_iomapfree;
  984. }
  985. /* On the 945G/GM, the chipset reports the MSI capability on the
  986. * integrated graphics even though the support isn't actually there
  987. * according to the published specs. It doesn't appear to function
  988. * correctly in testing on 945G.
  989. * This may be a side effect of MSI having been made available for PEG
  990. * and the registers being closely associated.
  991. *
  992. * According to chipset errata, on the 965GM, MSI interrupts may
  993. * be lost or delayed, but we use them anyways to avoid
  994. * stuck interrupts on some machines.
  995. */
  996. if (!IS_I945G(dev) && !IS_I945GM(dev))
  997. pci_enable_msi(dev->pdev);
  998. spin_lock_init(&dev_priv->user_irq_lock);
  999. dev_priv->user_irq_refcount = 0;
  1000. ret = drm_vblank_init(dev, I915_NUM_PIPE);
  1001. if (ret) {
  1002. (void) i915_driver_unload(dev);
  1003. return ret;
  1004. }
  1005. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1006. ret = i915_load_modeset_init(dev);
  1007. if (ret < 0) {
  1008. DRM_ERROR("failed to init modeset\n");
  1009. goto out_rmmap;
  1010. }
  1011. }
  1012. /* Must be done after probing outputs */
  1013. /* FIXME: verify on IGDNG */
  1014. if (!IS_IGDNG(dev))
  1015. intel_opregion_init(dev, 0);
  1016. return 0;
  1017. out_iomapfree:
  1018. io_mapping_free(dev_priv->mm.gtt_mapping);
  1019. out_rmmap:
  1020. iounmap(dev_priv->regs);
  1021. free_priv:
  1022. drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
  1023. return ret;
  1024. }
  1025. int i915_driver_unload(struct drm_device *dev)
  1026. {
  1027. struct drm_i915_private *dev_priv = dev->dev_private;
  1028. io_mapping_free(dev_priv->mm.gtt_mapping);
  1029. if (dev_priv->mm.gtt_mtrr >= 0) {
  1030. mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
  1031. dev->agp->agp_info.aper_size * 1024 * 1024);
  1032. dev_priv->mm.gtt_mtrr = -1;
  1033. }
  1034. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1035. drm_irq_uninstall(dev);
  1036. }
  1037. if (dev->pdev->msi_enabled)
  1038. pci_disable_msi(dev->pdev);
  1039. if (dev_priv->regs != NULL)
  1040. iounmap(dev_priv->regs);
  1041. if (!IS_IGDNG(dev))
  1042. intel_opregion_free(dev, 0);
  1043. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1044. intel_modeset_cleanup(dev);
  1045. i915_gem_free_all_phys_object(dev);
  1046. mutex_lock(&dev->struct_mutex);
  1047. i915_gem_cleanup_ringbuffer(dev);
  1048. mutex_unlock(&dev->struct_mutex);
  1049. drm_mm_takedown(&dev_priv->vram);
  1050. i915_gem_lastclose(dev);
  1051. }
  1052. drm_free(dev->dev_private, sizeof(drm_i915_private_t),
  1053. DRM_MEM_DRIVER);
  1054. return 0;
  1055. }
  1056. int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
  1057. {
  1058. struct drm_i915_file_private *i915_file_priv;
  1059. DRM_DEBUG_DRIVER(I915_DRV, "\n");
  1060. i915_file_priv = (struct drm_i915_file_private *)
  1061. drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
  1062. if (!i915_file_priv)
  1063. return -ENOMEM;
  1064. file_priv->driver_priv = i915_file_priv;
  1065. INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
  1066. return 0;
  1067. }
  1068. /**
  1069. * i915_driver_lastclose - clean up after all DRM clients have exited
  1070. * @dev: DRM device
  1071. *
  1072. * Take care of cleaning up after all DRM clients have exited. In the
  1073. * mode setting case, we want to restore the kernel's initial mode (just
  1074. * in case the last client left us in a bad state).
  1075. *
  1076. * Additionally, in the non-mode setting case, we'll tear down the AGP
  1077. * and DMA structures, since the kernel won't be using them, and clea
  1078. * up any GEM state.
  1079. */
  1080. void i915_driver_lastclose(struct drm_device * dev)
  1081. {
  1082. drm_i915_private_t *dev_priv = dev->dev_private;
  1083. if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
  1084. intelfb_restore();
  1085. return;
  1086. }
  1087. i915_gem_lastclose(dev);
  1088. if (dev_priv->agp_heap)
  1089. i915_mem_takedown(&(dev_priv->agp_heap));
  1090. i915_dma_cleanup(dev);
  1091. }
  1092. void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
  1093. {
  1094. drm_i915_private_t *dev_priv = dev->dev_private;
  1095. i915_gem_release(dev, file_priv);
  1096. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  1097. i915_mem_release(dev, file_priv, dev_priv->agp_heap);
  1098. }
  1099. void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
  1100. {
  1101. struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
  1102. drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
  1103. }
  1104. struct drm_ioctl_desc i915_ioctls[] = {
  1105. DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1106. DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
  1107. DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
  1108. DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
  1109. DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
  1110. DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
  1111. DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
  1112. DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1113. DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
  1114. DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
  1115. DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1116. DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
  1117. DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
  1118. DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
  1119. DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
  1120. DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
  1121. DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1122. DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1123. DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
  1124. DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
  1125. DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
  1126. DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
  1127. DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
  1128. DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1129. DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1130. DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
  1131. DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
  1132. DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
  1133. DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
  1134. DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
  1135. DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
  1136. DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
  1137. DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
  1138. DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
  1139. DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
  1140. DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
  1141. };
  1142. int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
  1143. /**
  1144. * Determine if the device really is AGP or not.
  1145. *
  1146. * All Intel graphics chipsets are treated as AGP, even if they are really
  1147. * PCI-e.
  1148. *
  1149. * \param dev The device to be tested.
  1150. *
  1151. * \returns
  1152. * A value of 1 is always retured to indictate every i9x5 is AGP.
  1153. */
  1154. int i915_driver_device_is_agp(struct drm_device * dev)
  1155. {
  1156. return 1;
  1157. }