intel-agp.c 72 KB

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  1. /*
  2. * Intel AGPGART routines.
  3. */
  4. #include <linux/module.h>
  5. #include <linux/pci.h>
  6. #include <linux/init.h>
  7. #include <linux/kernel.h>
  8. #include <linux/pagemap.h>
  9. #include <linux/agp_backend.h>
  10. #include "agp.h"
  11. #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
  12. #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
  13. #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
  14. #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
  15. #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
  16. #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
  17. #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
  18. #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
  19. #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
  20. #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
  21. #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
  22. #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
  23. #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
  24. #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
  25. #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
  26. #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
  27. #define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010
  28. #define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011
  29. #define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000
  30. #define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001
  31. #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
  32. #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
  33. #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
  34. #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
  35. #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
  36. #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
  37. #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
  38. #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
  39. #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
  40. #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
  41. #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
  42. #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
  43. #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
  44. #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
  45. #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
  46. #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
  47. #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040
  48. #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042
  49. #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044
  50. #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046
  51. /* cover 915 and 945 variants */
  52. #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  53. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  54. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  55. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  56. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  57. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  58. #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  59. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  60. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  61. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  62. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  63. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  64. #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  65. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  66. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  67. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  68. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  69. #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  70. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  71. #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
  72. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  73. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  74. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  75. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  76. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
  77. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB)
  78. extern int agp_memory_reserved;
  79. /* Intel 815 register */
  80. #define INTEL_815_APCONT 0x51
  81. #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
  82. /* Intel i820 registers */
  83. #define INTEL_I820_RDCR 0x51
  84. #define INTEL_I820_ERRSTS 0xc8
  85. /* Intel i840 registers */
  86. #define INTEL_I840_MCHCFG 0x50
  87. #define INTEL_I840_ERRSTS 0xc8
  88. /* Intel i850 registers */
  89. #define INTEL_I850_MCHCFG 0x50
  90. #define INTEL_I850_ERRSTS 0xc8
  91. /* intel 915G registers */
  92. #define I915_GMADDR 0x18
  93. #define I915_MMADDR 0x10
  94. #define I915_PTEADDR 0x1C
  95. #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
  96. #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
  97. #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
  98. #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
  99. #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
  100. #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
  101. #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
  102. #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
  103. #define I915_IFPADDR 0x60
  104. /* Intel 965G registers */
  105. #define I965_MSAC 0x62
  106. #define I965_IFPADDR 0x70
  107. /* Intel 7505 registers */
  108. #define INTEL_I7505_APSIZE 0x74
  109. #define INTEL_I7505_NCAPID 0x60
  110. #define INTEL_I7505_NISTAT 0x6c
  111. #define INTEL_I7505_ATTBASE 0x78
  112. #define INTEL_I7505_ERRSTS 0x42
  113. #define INTEL_I7505_AGPCTRL 0x70
  114. #define INTEL_I7505_MCHCFG 0x50
  115. static const struct aper_size_info_fixed intel_i810_sizes[] =
  116. {
  117. {64, 16384, 4},
  118. /* The 32M mode still requires a 64k gatt */
  119. {32, 8192, 4}
  120. };
  121. #define AGP_DCACHE_MEMORY 1
  122. #define AGP_PHYS_MEMORY 2
  123. #define INTEL_AGP_CACHED_MEMORY 3
  124. static struct gatt_mask intel_i810_masks[] =
  125. {
  126. {.mask = I810_PTE_VALID, .type = 0},
  127. {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
  128. {.mask = I810_PTE_VALID, .type = 0},
  129. {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
  130. .type = INTEL_AGP_CACHED_MEMORY}
  131. };
  132. static struct _intel_private {
  133. struct pci_dev *pcidev; /* device one */
  134. u8 __iomem *registers;
  135. u32 __iomem *gtt; /* I915G */
  136. int num_dcache_entries;
  137. /* gtt_entries is the number of gtt entries that are already mapped
  138. * to stolen memory. Stolen memory is larger than the memory mapped
  139. * through gtt_entries, as it includes some reserved space for the BIOS
  140. * popup and for the GTT.
  141. */
  142. int gtt_entries; /* i830+ */
  143. union {
  144. void __iomem *i9xx_flush_page;
  145. void *i8xx_flush_page;
  146. };
  147. struct page *i8xx_page;
  148. struct resource ifp_resource;
  149. int resource_valid;
  150. } intel_private;
  151. static int intel_i810_fetch_size(void)
  152. {
  153. u32 smram_miscc;
  154. struct aper_size_info_fixed *values;
  155. pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
  156. values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
  157. if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
  158. dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
  159. return 0;
  160. }
  161. if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
  162. agp_bridge->previous_size =
  163. agp_bridge->current_size = (void *) (values + 1);
  164. agp_bridge->aperture_size_idx = 1;
  165. return values[1].size;
  166. } else {
  167. agp_bridge->previous_size =
  168. agp_bridge->current_size = (void *) (values);
  169. agp_bridge->aperture_size_idx = 0;
  170. return values[0].size;
  171. }
  172. return 0;
  173. }
  174. static int intel_i810_configure(void)
  175. {
  176. struct aper_size_info_fixed *current_size;
  177. u32 temp;
  178. int i;
  179. current_size = A_SIZE_FIX(agp_bridge->current_size);
  180. if (!intel_private.registers) {
  181. pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
  182. temp &= 0xfff80000;
  183. intel_private.registers = ioremap(temp, 128 * 4096);
  184. if (!intel_private.registers) {
  185. dev_err(&intel_private.pcidev->dev,
  186. "can't remap memory\n");
  187. return -ENOMEM;
  188. }
  189. }
  190. if ((readl(intel_private.registers+I810_DRAM_CTL)
  191. & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
  192. /* This will need to be dynamically assigned */
  193. dev_info(&intel_private.pcidev->dev,
  194. "detected 4MB dedicated video ram\n");
  195. intel_private.num_dcache_entries = 1024;
  196. }
  197. pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
  198. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  199. writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
  200. readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
  201. if (agp_bridge->driver->needs_scratch_page) {
  202. for (i = 0; i < current_size->num_entries; i++) {
  203. writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
  204. }
  205. readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
  206. }
  207. global_cache_flush();
  208. return 0;
  209. }
  210. static void intel_i810_cleanup(void)
  211. {
  212. writel(0, intel_private.registers+I810_PGETBL_CTL);
  213. readl(intel_private.registers); /* PCI Posting. */
  214. iounmap(intel_private.registers);
  215. }
  216. static void intel_i810_tlbflush(struct agp_memory *mem)
  217. {
  218. return;
  219. }
  220. static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
  221. {
  222. return;
  223. }
  224. /* Exists to support ARGB cursors */
  225. static void *i8xx_alloc_pages(void)
  226. {
  227. struct page *page;
  228. page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
  229. if (page == NULL)
  230. return NULL;
  231. if (set_pages_uc(page, 4) < 0) {
  232. set_pages_wb(page, 4);
  233. __free_pages(page, 2);
  234. return NULL;
  235. }
  236. get_page(page);
  237. atomic_inc(&agp_bridge->current_memory_agp);
  238. return page_address(page);
  239. }
  240. static void i8xx_destroy_pages(void *addr)
  241. {
  242. struct page *page;
  243. if (addr == NULL)
  244. return;
  245. page = virt_to_page(addr);
  246. set_pages_wb(page, 4);
  247. put_page(page);
  248. __free_pages(page, 2);
  249. atomic_dec(&agp_bridge->current_memory_agp);
  250. }
  251. static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
  252. int type)
  253. {
  254. if (type < AGP_USER_TYPES)
  255. return type;
  256. else if (type == AGP_USER_CACHED_MEMORY)
  257. return INTEL_AGP_CACHED_MEMORY;
  258. else
  259. return 0;
  260. }
  261. static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
  262. int type)
  263. {
  264. int i, j, num_entries;
  265. void *temp;
  266. int ret = -EINVAL;
  267. int mask_type;
  268. if (mem->page_count == 0)
  269. goto out;
  270. temp = agp_bridge->current_size;
  271. num_entries = A_SIZE_FIX(temp)->num_entries;
  272. if ((pg_start + mem->page_count) > num_entries)
  273. goto out_err;
  274. for (j = pg_start; j < (pg_start + mem->page_count); j++) {
  275. if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
  276. ret = -EBUSY;
  277. goto out_err;
  278. }
  279. }
  280. if (type != mem->type)
  281. goto out_err;
  282. mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
  283. switch (mask_type) {
  284. case AGP_DCACHE_MEMORY:
  285. if (!mem->is_flushed)
  286. global_cache_flush();
  287. for (i = pg_start; i < (pg_start + mem->page_count); i++) {
  288. writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
  289. intel_private.registers+I810_PTE_BASE+(i*4));
  290. }
  291. readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
  292. break;
  293. case AGP_PHYS_MEMORY:
  294. case AGP_NORMAL_MEMORY:
  295. if (!mem->is_flushed)
  296. global_cache_flush();
  297. for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
  298. writel(agp_bridge->driver->mask_memory(agp_bridge,
  299. mem->memory[i],
  300. mask_type),
  301. intel_private.registers+I810_PTE_BASE+(j*4));
  302. }
  303. readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
  304. break;
  305. default:
  306. goto out_err;
  307. }
  308. agp_bridge->driver->tlb_flush(mem);
  309. out:
  310. ret = 0;
  311. out_err:
  312. mem->is_flushed = true;
  313. return ret;
  314. }
  315. static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
  316. int type)
  317. {
  318. int i;
  319. if (mem->page_count == 0)
  320. return 0;
  321. for (i = pg_start; i < (mem->page_count + pg_start); i++) {
  322. writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
  323. }
  324. readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
  325. agp_bridge->driver->tlb_flush(mem);
  326. return 0;
  327. }
  328. /*
  329. * The i810/i830 requires a physical address to program its mouse
  330. * pointer into hardware.
  331. * However the Xserver still writes to it through the agp aperture.
  332. */
  333. static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
  334. {
  335. struct agp_memory *new;
  336. void *addr;
  337. switch (pg_count) {
  338. case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
  339. break;
  340. case 4:
  341. /* kludge to get 4 physical pages for ARGB cursor */
  342. addr = i8xx_alloc_pages();
  343. break;
  344. default:
  345. return NULL;
  346. }
  347. if (addr == NULL)
  348. return NULL;
  349. new = agp_create_memory(pg_count);
  350. if (new == NULL)
  351. return NULL;
  352. new->memory[0] = virt_to_gart(addr);
  353. if (pg_count == 4) {
  354. /* kludge to get 4 physical pages for ARGB cursor */
  355. new->memory[1] = new->memory[0] + PAGE_SIZE;
  356. new->memory[2] = new->memory[1] + PAGE_SIZE;
  357. new->memory[3] = new->memory[2] + PAGE_SIZE;
  358. }
  359. new->page_count = pg_count;
  360. new->num_scratch_pages = pg_count;
  361. new->type = AGP_PHYS_MEMORY;
  362. new->physical = new->memory[0];
  363. return new;
  364. }
  365. static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
  366. {
  367. struct agp_memory *new;
  368. if (type == AGP_DCACHE_MEMORY) {
  369. if (pg_count != intel_private.num_dcache_entries)
  370. return NULL;
  371. new = agp_create_memory(1);
  372. if (new == NULL)
  373. return NULL;
  374. new->type = AGP_DCACHE_MEMORY;
  375. new->page_count = pg_count;
  376. new->num_scratch_pages = 0;
  377. agp_free_page_array(new);
  378. return new;
  379. }
  380. if (type == AGP_PHYS_MEMORY)
  381. return alloc_agpphysmem_i8xx(pg_count, type);
  382. return NULL;
  383. }
  384. static void intel_i810_free_by_type(struct agp_memory *curr)
  385. {
  386. agp_free_key(curr->key);
  387. if (curr->type == AGP_PHYS_MEMORY) {
  388. if (curr->page_count == 4)
  389. i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
  390. else {
  391. void *va = gart_to_virt(curr->memory[0]);
  392. agp_bridge->driver->agp_destroy_page(va,
  393. AGP_PAGE_DESTROY_UNMAP);
  394. agp_bridge->driver->agp_destroy_page(va,
  395. AGP_PAGE_DESTROY_FREE);
  396. }
  397. agp_free_page_array(curr);
  398. }
  399. kfree(curr);
  400. }
  401. static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
  402. unsigned long addr, int type)
  403. {
  404. /* Type checking must be done elsewhere */
  405. return addr | bridge->driver->masks[type].mask;
  406. }
  407. static struct aper_size_info_fixed intel_i830_sizes[] =
  408. {
  409. {128, 32768, 5},
  410. /* The 64M mode still requires a 128k gatt */
  411. {64, 16384, 5},
  412. {256, 65536, 6},
  413. {512, 131072, 7},
  414. };
  415. static void intel_i830_init_gtt_entries(void)
  416. {
  417. u16 gmch_ctrl;
  418. int gtt_entries;
  419. u8 rdct;
  420. int local = 0;
  421. static const int ddt[4] = { 0, 16, 32, 64 };
  422. int size; /* reserved space (in kb) at the top of stolen memory */
  423. pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
  424. if (IS_I965) {
  425. u32 pgetbl_ctl;
  426. pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
  427. /* The 965 has a field telling us the size of the GTT,
  428. * which may be larger than what is necessary to map the
  429. * aperture.
  430. */
  431. switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
  432. case I965_PGETBL_SIZE_128KB:
  433. size = 128;
  434. break;
  435. case I965_PGETBL_SIZE_256KB:
  436. size = 256;
  437. break;
  438. case I965_PGETBL_SIZE_512KB:
  439. size = 512;
  440. break;
  441. case I965_PGETBL_SIZE_1MB:
  442. size = 1024;
  443. break;
  444. case I965_PGETBL_SIZE_2MB:
  445. size = 2048;
  446. break;
  447. case I965_PGETBL_SIZE_1_5MB:
  448. size = 1024 + 512;
  449. break;
  450. default:
  451. dev_info(&intel_private.pcidev->dev,
  452. "unknown page table size, assuming 512KB\n");
  453. size = 512;
  454. }
  455. size += 4; /* add in BIOS popup space */
  456. } else if (IS_G33 && !IS_IGD) {
  457. /* G33's GTT size defined in gmch_ctrl */
  458. switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
  459. case G33_PGETBL_SIZE_1M:
  460. size = 1024;
  461. break;
  462. case G33_PGETBL_SIZE_2M:
  463. size = 2048;
  464. break;
  465. default:
  466. dev_info(&agp_bridge->dev->dev,
  467. "unknown page table size 0x%x, assuming 512KB\n",
  468. (gmch_ctrl & G33_PGETBL_SIZE_MASK));
  469. size = 512;
  470. }
  471. size += 4;
  472. } else if (IS_G4X || IS_IGD) {
  473. /* On 4 series hardware, GTT stolen is separate from graphics
  474. * stolen, ignore it in stolen gtt entries counting. However,
  475. * 4KB of the stolen memory doesn't get mapped to the GTT.
  476. */
  477. size = 4;
  478. } else {
  479. /* On previous hardware, the GTT size was just what was
  480. * required to map the aperture.
  481. */
  482. size = agp_bridge->driver->fetch_size() + 4;
  483. }
  484. if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
  485. agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
  486. switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
  487. case I830_GMCH_GMS_STOLEN_512:
  488. gtt_entries = KB(512) - KB(size);
  489. break;
  490. case I830_GMCH_GMS_STOLEN_1024:
  491. gtt_entries = MB(1) - KB(size);
  492. break;
  493. case I830_GMCH_GMS_STOLEN_8192:
  494. gtt_entries = MB(8) - KB(size);
  495. break;
  496. case I830_GMCH_GMS_LOCAL:
  497. rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
  498. gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
  499. MB(ddt[I830_RDRAM_DDT(rdct)]);
  500. local = 1;
  501. break;
  502. default:
  503. gtt_entries = 0;
  504. break;
  505. }
  506. } else {
  507. switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
  508. case I855_GMCH_GMS_STOLEN_1M:
  509. gtt_entries = MB(1) - KB(size);
  510. break;
  511. case I855_GMCH_GMS_STOLEN_4M:
  512. gtt_entries = MB(4) - KB(size);
  513. break;
  514. case I855_GMCH_GMS_STOLEN_8M:
  515. gtt_entries = MB(8) - KB(size);
  516. break;
  517. case I855_GMCH_GMS_STOLEN_16M:
  518. gtt_entries = MB(16) - KB(size);
  519. break;
  520. case I855_GMCH_GMS_STOLEN_32M:
  521. gtt_entries = MB(32) - KB(size);
  522. break;
  523. case I915_GMCH_GMS_STOLEN_48M:
  524. /* Check it's really I915G */
  525. if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
  526. gtt_entries = MB(48) - KB(size);
  527. else
  528. gtt_entries = 0;
  529. break;
  530. case I915_GMCH_GMS_STOLEN_64M:
  531. /* Check it's really I915G */
  532. if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
  533. gtt_entries = MB(64) - KB(size);
  534. else
  535. gtt_entries = 0;
  536. break;
  537. case G33_GMCH_GMS_STOLEN_128M:
  538. if (IS_G33 || IS_I965 || IS_G4X)
  539. gtt_entries = MB(128) - KB(size);
  540. else
  541. gtt_entries = 0;
  542. break;
  543. case G33_GMCH_GMS_STOLEN_256M:
  544. if (IS_G33 || IS_I965 || IS_G4X)
  545. gtt_entries = MB(256) - KB(size);
  546. else
  547. gtt_entries = 0;
  548. break;
  549. case INTEL_GMCH_GMS_STOLEN_96M:
  550. if (IS_I965 || IS_G4X)
  551. gtt_entries = MB(96) - KB(size);
  552. else
  553. gtt_entries = 0;
  554. break;
  555. case INTEL_GMCH_GMS_STOLEN_160M:
  556. if (IS_I965 || IS_G4X)
  557. gtt_entries = MB(160) - KB(size);
  558. else
  559. gtt_entries = 0;
  560. break;
  561. case INTEL_GMCH_GMS_STOLEN_224M:
  562. if (IS_I965 || IS_G4X)
  563. gtt_entries = MB(224) - KB(size);
  564. else
  565. gtt_entries = 0;
  566. break;
  567. case INTEL_GMCH_GMS_STOLEN_352M:
  568. if (IS_I965 || IS_G4X)
  569. gtt_entries = MB(352) - KB(size);
  570. else
  571. gtt_entries = 0;
  572. break;
  573. default:
  574. gtt_entries = 0;
  575. break;
  576. }
  577. }
  578. if (gtt_entries > 0) {
  579. dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
  580. gtt_entries / KB(1), local ? "local" : "stolen");
  581. gtt_entries /= KB(4);
  582. } else {
  583. dev_info(&agp_bridge->dev->dev,
  584. "no pre-allocated video memory detected\n");
  585. gtt_entries = 0;
  586. }
  587. intel_private.gtt_entries = gtt_entries;
  588. }
  589. static void intel_i830_fini_flush(void)
  590. {
  591. kunmap(intel_private.i8xx_page);
  592. intel_private.i8xx_flush_page = NULL;
  593. unmap_page_from_agp(intel_private.i8xx_page);
  594. __free_page(intel_private.i8xx_page);
  595. intel_private.i8xx_page = NULL;
  596. }
  597. static void intel_i830_setup_flush(void)
  598. {
  599. /* return if we've already set the flush mechanism up */
  600. if (intel_private.i8xx_page)
  601. return;
  602. intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
  603. if (!intel_private.i8xx_page)
  604. return;
  605. /* make page uncached */
  606. map_page_into_agp(intel_private.i8xx_page);
  607. intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
  608. if (!intel_private.i8xx_flush_page)
  609. intel_i830_fini_flush();
  610. }
  611. static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
  612. {
  613. unsigned int *pg = intel_private.i8xx_flush_page;
  614. int i;
  615. for (i = 0; i < 256; i += 2)
  616. *(pg + i) = i;
  617. wmb();
  618. }
  619. /* The intel i830 automatically initializes the agp aperture during POST.
  620. * Use the memory already set aside for in the GTT.
  621. */
  622. static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
  623. {
  624. int page_order;
  625. struct aper_size_info_fixed *size;
  626. int num_entries;
  627. u32 temp;
  628. size = agp_bridge->current_size;
  629. page_order = size->page_order;
  630. num_entries = size->num_entries;
  631. agp_bridge->gatt_table_real = NULL;
  632. pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
  633. temp &= 0xfff80000;
  634. intel_private.registers = ioremap(temp, 128 * 4096);
  635. if (!intel_private.registers)
  636. return -ENOMEM;
  637. temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
  638. global_cache_flush(); /* FIXME: ?? */
  639. /* we have to call this as early as possible after the MMIO base address is known */
  640. intel_i830_init_gtt_entries();
  641. agp_bridge->gatt_table = NULL;
  642. agp_bridge->gatt_bus_addr = temp;
  643. return 0;
  644. }
  645. /* Return the gatt table to a sane state. Use the top of stolen
  646. * memory for the GTT.
  647. */
  648. static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
  649. {
  650. return 0;
  651. }
  652. static int intel_i830_fetch_size(void)
  653. {
  654. u16 gmch_ctrl;
  655. struct aper_size_info_fixed *values;
  656. values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
  657. if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
  658. agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
  659. /* 855GM/852GM/865G has 128MB aperture size */
  660. agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
  661. agp_bridge->aperture_size_idx = 0;
  662. return values[0].size;
  663. }
  664. pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
  665. if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
  666. agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
  667. agp_bridge->aperture_size_idx = 0;
  668. return values[0].size;
  669. } else {
  670. agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
  671. agp_bridge->aperture_size_idx = 1;
  672. return values[1].size;
  673. }
  674. return 0;
  675. }
  676. static int intel_i830_configure(void)
  677. {
  678. struct aper_size_info_fixed *current_size;
  679. u32 temp;
  680. u16 gmch_ctrl;
  681. int i;
  682. current_size = A_SIZE_FIX(agp_bridge->current_size);
  683. pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
  684. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  685. pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
  686. gmch_ctrl |= I830_GMCH_ENABLED;
  687. pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
  688. writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
  689. readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
  690. if (agp_bridge->driver->needs_scratch_page) {
  691. for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
  692. writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
  693. }
  694. readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
  695. }
  696. global_cache_flush();
  697. intel_i830_setup_flush();
  698. return 0;
  699. }
  700. static void intel_i830_cleanup(void)
  701. {
  702. iounmap(intel_private.registers);
  703. }
  704. static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
  705. int type)
  706. {
  707. int i, j, num_entries;
  708. void *temp;
  709. int ret = -EINVAL;
  710. int mask_type;
  711. if (mem->page_count == 0)
  712. goto out;
  713. temp = agp_bridge->current_size;
  714. num_entries = A_SIZE_FIX(temp)->num_entries;
  715. if (pg_start < intel_private.gtt_entries) {
  716. dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
  717. "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
  718. pg_start, intel_private.gtt_entries);
  719. dev_info(&intel_private.pcidev->dev,
  720. "trying to insert into local/stolen memory\n");
  721. goto out_err;
  722. }
  723. if ((pg_start + mem->page_count) > num_entries)
  724. goto out_err;
  725. /* The i830 can't check the GTT for entries since its read only,
  726. * depend on the caller to make the correct offset decisions.
  727. */
  728. if (type != mem->type)
  729. goto out_err;
  730. mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
  731. if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
  732. mask_type != INTEL_AGP_CACHED_MEMORY)
  733. goto out_err;
  734. if (!mem->is_flushed)
  735. global_cache_flush();
  736. for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
  737. writel(agp_bridge->driver->mask_memory(agp_bridge,
  738. mem->memory[i], mask_type),
  739. intel_private.registers+I810_PTE_BASE+(j*4));
  740. }
  741. readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
  742. agp_bridge->driver->tlb_flush(mem);
  743. out:
  744. ret = 0;
  745. out_err:
  746. mem->is_flushed = true;
  747. return ret;
  748. }
  749. static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
  750. int type)
  751. {
  752. int i;
  753. if (mem->page_count == 0)
  754. return 0;
  755. if (pg_start < intel_private.gtt_entries) {
  756. dev_info(&intel_private.pcidev->dev,
  757. "trying to disable local/stolen memory\n");
  758. return -EINVAL;
  759. }
  760. for (i = pg_start; i < (mem->page_count + pg_start); i++) {
  761. writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
  762. }
  763. readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
  764. agp_bridge->driver->tlb_flush(mem);
  765. return 0;
  766. }
  767. static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
  768. {
  769. if (type == AGP_PHYS_MEMORY)
  770. return alloc_agpphysmem_i8xx(pg_count, type);
  771. /* always return NULL for other allocation types for now */
  772. return NULL;
  773. }
  774. static int intel_alloc_chipset_flush_resource(void)
  775. {
  776. int ret;
  777. ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
  778. PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
  779. pcibios_align_resource, agp_bridge->dev);
  780. return ret;
  781. }
  782. static void intel_i915_setup_chipset_flush(void)
  783. {
  784. int ret;
  785. u32 temp;
  786. pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
  787. if (!(temp & 0x1)) {
  788. intel_alloc_chipset_flush_resource();
  789. intel_private.resource_valid = 1;
  790. pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
  791. } else {
  792. temp &= ~1;
  793. intel_private.resource_valid = 1;
  794. intel_private.ifp_resource.start = temp;
  795. intel_private.ifp_resource.end = temp + PAGE_SIZE;
  796. ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
  797. /* some BIOSes reserve this area in a pnp some don't */
  798. if (ret)
  799. intel_private.resource_valid = 0;
  800. }
  801. }
  802. static void intel_i965_g33_setup_chipset_flush(void)
  803. {
  804. u32 temp_hi, temp_lo;
  805. int ret;
  806. pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
  807. pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
  808. if (!(temp_lo & 0x1)) {
  809. intel_alloc_chipset_flush_resource();
  810. intel_private.resource_valid = 1;
  811. pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
  812. upper_32_bits(intel_private.ifp_resource.start));
  813. pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
  814. } else {
  815. u64 l64;
  816. temp_lo &= ~0x1;
  817. l64 = ((u64)temp_hi << 32) | temp_lo;
  818. intel_private.resource_valid = 1;
  819. intel_private.ifp_resource.start = l64;
  820. intel_private.ifp_resource.end = l64 + PAGE_SIZE;
  821. ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
  822. /* some BIOSes reserve this area in a pnp some don't */
  823. if (ret)
  824. intel_private.resource_valid = 0;
  825. }
  826. }
  827. static void intel_i9xx_setup_flush(void)
  828. {
  829. /* return if already configured */
  830. if (intel_private.ifp_resource.start)
  831. return;
  832. /* setup a resource for this object */
  833. intel_private.ifp_resource.name = "Intel Flush Page";
  834. intel_private.ifp_resource.flags = IORESOURCE_MEM;
  835. /* Setup chipset flush for 915 */
  836. if (IS_I965 || IS_G33 || IS_G4X) {
  837. intel_i965_g33_setup_chipset_flush();
  838. } else {
  839. intel_i915_setup_chipset_flush();
  840. }
  841. if (intel_private.ifp_resource.start) {
  842. intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
  843. if (!intel_private.i9xx_flush_page)
  844. dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
  845. }
  846. }
  847. static int intel_i915_configure(void)
  848. {
  849. struct aper_size_info_fixed *current_size;
  850. u32 temp;
  851. u16 gmch_ctrl;
  852. int i;
  853. current_size = A_SIZE_FIX(agp_bridge->current_size);
  854. pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
  855. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  856. pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
  857. gmch_ctrl |= I830_GMCH_ENABLED;
  858. pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
  859. writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
  860. readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
  861. if (agp_bridge->driver->needs_scratch_page) {
  862. for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
  863. writel(agp_bridge->scratch_page, intel_private.gtt+i);
  864. }
  865. readl(intel_private.gtt+i-1); /* PCI Posting. */
  866. }
  867. global_cache_flush();
  868. intel_i9xx_setup_flush();
  869. return 0;
  870. }
  871. static void intel_i915_cleanup(void)
  872. {
  873. if (intel_private.i9xx_flush_page)
  874. iounmap(intel_private.i9xx_flush_page);
  875. if (intel_private.resource_valid)
  876. release_resource(&intel_private.ifp_resource);
  877. intel_private.ifp_resource.start = 0;
  878. intel_private.resource_valid = 0;
  879. iounmap(intel_private.gtt);
  880. iounmap(intel_private.registers);
  881. }
  882. static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
  883. {
  884. if (intel_private.i9xx_flush_page)
  885. writel(1, intel_private.i9xx_flush_page);
  886. }
  887. static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
  888. int type)
  889. {
  890. int i, j, num_entries;
  891. void *temp;
  892. int ret = -EINVAL;
  893. int mask_type;
  894. if (mem->page_count == 0)
  895. goto out;
  896. temp = agp_bridge->current_size;
  897. num_entries = A_SIZE_FIX(temp)->num_entries;
  898. if (pg_start < intel_private.gtt_entries) {
  899. dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
  900. "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
  901. pg_start, intel_private.gtt_entries);
  902. dev_info(&intel_private.pcidev->dev,
  903. "trying to insert into local/stolen memory\n");
  904. goto out_err;
  905. }
  906. if ((pg_start + mem->page_count) > num_entries)
  907. goto out_err;
  908. /* The i915 can't check the GTT for entries since its read only,
  909. * depend on the caller to make the correct offset decisions.
  910. */
  911. if (type != mem->type)
  912. goto out_err;
  913. mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
  914. if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
  915. mask_type != INTEL_AGP_CACHED_MEMORY)
  916. goto out_err;
  917. if (!mem->is_flushed)
  918. global_cache_flush();
  919. for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
  920. writel(agp_bridge->driver->mask_memory(agp_bridge,
  921. mem->memory[i], mask_type), intel_private.gtt+j);
  922. }
  923. readl(intel_private.gtt+j-1);
  924. agp_bridge->driver->tlb_flush(mem);
  925. out:
  926. ret = 0;
  927. out_err:
  928. mem->is_flushed = true;
  929. return ret;
  930. }
  931. static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
  932. int type)
  933. {
  934. int i;
  935. if (mem->page_count == 0)
  936. return 0;
  937. if (pg_start < intel_private.gtt_entries) {
  938. dev_info(&intel_private.pcidev->dev,
  939. "trying to disable local/stolen memory\n");
  940. return -EINVAL;
  941. }
  942. for (i = pg_start; i < (mem->page_count + pg_start); i++)
  943. writel(agp_bridge->scratch_page, intel_private.gtt+i);
  944. readl(intel_private.gtt+i-1);
  945. agp_bridge->driver->tlb_flush(mem);
  946. return 0;
  947. }
  948. /* Return the aperture size by just checking the resource length. The effect
  949. * described in the spec of the MSAC registers is just changing of the
  950. * resource size.
  951. */
  952. static int intel_i9xx_fetch_size(void)
  953. {
  954. int num_sizes = ARRAY_SIZE(intel_i830_sizes);
  955. int aper_size; /* size in megabytes */
  956. int i;
  957. aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
  958. for (i = 0; i < num_sizes; i++) {
  959. if (aper_size == intel_i830_sizes[i].size) {
  960. agp_bridge->current_size = intel_i830_sizes + i;
  961. agp_bridge->previous_size = agp_bridge->current_size;
  962. return aper_size;
  963. }
  964. }
  965. return 0;
  966. }
  967. /* The intel i915 automatically initializes the agp aperture during POST.
  968. * Use the memory already set aside for in the GTT.
  969. */
  970. static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
  971. {
  972. int page_order;
  973. struct aper_size_info_fixed *size;
  974. int num_entries;
  975. u32 temp, temp2;
  976. int gtt_map_size = 256 * 1024;
  977. size = agp_bridge->current_size;
  978. page_order = size->page_order;
  979. num_entries = size->num_entries;
  980. agp_bridge->gatt_table_real = NULL;
  981. pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
  982. pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
  983. if (IS_G33)
  984. gtt_map_size = 1024 * 1024; /* 1M on G33 */
  985. intel_private.gtt = ioremap(temp2, gtt_map_size);
  986. if (!intel_private.gtt)
  987. return -ENOMEM;
  988. temp &= 0xfff80000;
  989. intel_private.registers = ioremap(temp, 128 * 4096);
  990. if (!intel_private.registers) {
  991. iounmap(intel_private.gtt);
  992. return -ENOMEM;
  993. }
  994. temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
  995. global_cache_flush(); /* FIXME: ? */
  996. /* we have to call this as early as possible after the MMIO base address is known */
  997. intel_i830_init_gtt_entries();
  998. agp_bridge->gatt_table = NULL;
  999. agp_bridge->gatt_bus_addr = temp;
  1000. return 0;
  1001. }
  1002. /*
  1003. * The i965 supports 36-bit physical addresses, but to keep
  1004. * the format of the GTT the same, the bits that don't fit
  1005. * in a 32-bit word are shifted down to bits 4..7.
  1006. *
  1007. * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
  1008. * is always zero on 32-bit architectures, so no need to make
  1009. * this conditional.
  1010. */
  1011. static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
  1012. unsigned long addr, int type)
  1013. {
  1014. /* Shift high bits down */
  1015. addr |= (addr >> 28) & 0xf0;
  1016. /* Type checking must be done elsewhere */
  1017. return addr | bridge->driver->masks[type].mask;
  1018. }
  1019. static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
  1020. {
  1021. switch (agp_bridge->dev->device) {
  1022. case PCI_DEVICE_ID_INTEL_GM45_HB:
  1023. case PCI_DEVICE_ID_INTEL_IGD_E_HB:
  1024. case PCI_DEVICE_ID_INTEL_Q45_HB:
  1025. case PCI_DEVICE_ID_INTEL_G45_HB:
  1026. case PCI_DEVICE_ID_INTEL_G41_HB:
  1027. case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
  1028. case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
  1029. *gtt_offset = *gtt_size = MB(2);
  1030. break;
  1031. default:
  1032. *gtt_offset = *gtt_size = KB(512);
  1033. }
  1034. }
  1035. /* The intel i965 automatically initializes the agp aperture during POST.
  1036. * Use the memory already set aside for in the GTT.
  1037. */
  1038. static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
  1039. {
  1040. int page_order;
  1041. struct aper_size_info_fixed *size;
  1042. int num_entries;
  1043. u32 temp;
  1044. int gtt_offset, gtt_size;
  1045. size = agp_bridge->current_size;
  1046. page_order = size->page_order;
  1047. num_entries = size->num_entries;
  1048. agp_bridge->gatt_table_real = NULL;
  1049. pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
  1050. temp &= 0xfff00000;
  1051. intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
  1052. intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
  1053. if (!intel_private.gtt)
  1054. return -ENOMEM;
  1055. intel_private.registers = ioremap(temp, 128 * 4096);
  1056. if (!intel_private.registers) {
  1057. iounmap(intel_private.gtt);
  1058. return -ENOMEM;
  1059. }
  1060. temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
  1061. global_cache_flush(); /* FIXME: ? */
  1062. /* we have to call this as early as possible after the MMIO base address is known */
  1063. intel_i830_init_gtt_entries();
  1064. agp_bridge->gatt_table = NULL;
  1065. agp_bridge->gatt_bus_addr = temp;
  1066. return 0;
  1067. }
  1068. static int intel_fetch_size(void)
  1069. {
  1070. int i;
  1071. u16 temp;
  1072. struct aper_size_info_16 *values;
  1073. pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
  1074. values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
  1075. for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
  1076. if (temp == values[i].size_value) {
  1077. agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
  1078. agp_bridge->aperture_size_idx = i;
  1079. return values[i].size;
  1080. }
  1081. }
  1082. return 0;
  1083. }
  1084. static int __intel_8xx_fetch_size(u8 temp)
  1085. {
  1086. int i;
  1087. struct aper_size_info_8 *values;
  1088. values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
  1089. for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
  1090. if (temp == values[i].size_value) {
  1091. agp_bridge->previous_size =
  1092. agp_bridge->current_size = (void *) (values + i);
  1093. agp_bridge->aperture_size_idx = i;
  1094. return values[i].size;
  1095. }
  1096. }
  1097. return 0;
  1098. }
  1099. static int intel_8xx_fetch_size(void)
  1100. {
  1101. u8 temp;
  1102. pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
  1103. return __intel_8xx_fetch_size(temp);
  1104. }
  1105. static int intel_815_fetch_size(void)
  1106. {
  1107. u8 temp;
  1108. /* Intel 815 chipsets have a _weird_ APSIZE register with only
  1109. * one non-reserved bit, so mask the others out ... */
  1110. pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
  1111. temp &= (1 << 3);
  1112. return __intel_8xx_fetch_size(temp);
  1113. }
  1114. static void intel_tlbflush(struct agp_memory *mem)
  1115. {
  1116. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
  1117. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
  1118. }
  1119. static void intel_8xx_tlbflush(struct agp_memory *mem)
  1120. {
  1121. u32 temp;
  1122. pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
  1123. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
  1124. pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
  1125. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
  1126. }
  1127. static void intel_cleanup(void)
  1128. {
  1129. u16 temp;
  1130. struct aper_size_info_16 *previous_size;
  1131. previous_size = A_SIZE_16(agp_bridge->previous_size);
  1132. pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
  1133. pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
  1134. pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
  1135. }
  1136. static void intel_8xx_cleanup(void)
  1137. {
  1138. u16 temp;
  1139. struct aper_size_info_8 *previous_size;
  1140. previous_size = A_SIZE_8(agp_bridge->previous_size);
  1141. pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
  1142. pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
  1143. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
  1144. }
  1145. static int intel_configure(void)
  1146. {
  1147. u32 temp;
  1148. u16 temp2;
  1149. struct aper_size_info_16 *current_size;
  1150. current_size = A_SIZE_16(agp_bridge->current_size);
  1151. /* aperture size */
  1152. pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
  1153. /* address to map to */
  1154. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1155. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1156. /* attbase - aperture base */
  1157. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
  1158. /* agpctrl */
  1159. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
  1160. /* paccfg/nbxcfg */
  1161. pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
  1162. pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
  1163. (temp2 & ~(1 << 10)) | (1 << 9));
  1164. /* clear any possible error conditions */
  1165. pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
  1166. return 0;
  1167. }
  1168. static int intel_815_configure(void)
  1169. {
  1170. u32 temp, addr;
  1171. u8 temp2;
  1172. struct aper_size_info_8 *current_size;
  1173. /* attbase - aperture base */
  1174. /* the Intel 815 chipset spec. says that bits 29-31 in the
  1175. * ATTBASE register are reserved -> try not to write them */
  1176. if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
  1177. dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
  1178. return -EINVAL;
  1179. }
  1180. current_size = A_SIZE_8(agp_bridge->current_size);
  1181. /* aperture size */
  1182. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
  1183. current_size->size_value);
  1184. /* address to map to */
  1185. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1186. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1187. pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
  1188. addr &= INTEL_815_ATTBASE_MASK;
  1189. addr |= agp_bridge->gatt_bus_addr;
  1190. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
  1191. /* agpctrl */
  1192. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
  1193. /* apcont */
  1194. pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
  1195. pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
  1196. /* clear any possible error conditions */
  1197. /* Oddness : this chipset seems to have no ERRSTS register ! */
  1198. return 0;
  1199. }
  1200. static void intel_820_tlbflush(struct agp_memory *mem)
  1201. {
  1202. return;
  1203. }
  1204. static void intel_820_cleanup(void)
  1205. {
  1206. u8 temp;
  1207. struct aper_size_info_8 *previous_size;
  1208. previous_size = A_SIZE_8(agp_bridge->previous_size);
  1209. pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
  1210. pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
  1211. temp & ~(1 << 1));
  1212. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
  1213. previous_size->size_value);
  1214. }
  1215. static int intel_820_configure(void)
  1216. {
  1217. u32 temp;
  1218. u8 temp2;
  1219. struct aper_size_info_8 *current_size;
  1220. current_size = A_SIZE_8(agp_bridge->current_size);
  1221. /* aperture size */
  1222. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
  1223. /* address to map to */
  1224. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1225. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1226. /* attbase - aperture base */
  1227. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
  1228. /* agpctrl */
  1229. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
  1230. /* global enable aperture access */
  1231. /* This flag is not accessed through MCHCFG register as in */
  1232. /* i850 chipset. */
  1233. pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
  1234. pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
  1235. /* clear any possible AGP-related error conditions */
  1236. pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
  1237. return 0;
  1238. }
  1239. static int intel_840_configure(void)
  1240. {
  1241. u32 temp;
  1242. u16 temp2;
  1243. struct aper_size_info_8 *current_size;
  1244. current_size = A_SIZE_8(agp_bridge->current_size);
  1245. /* aperture size */
  1246. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
  1247. /* address to map to */
  1248. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1249. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1250. /* attbase - aperture base */
  1251. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
  1252. /* agpctrl */
  1253. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
  1254. /* mcgcfg */
  1255. pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
  1256. pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
  1257. /* clear any possible error conditions */
  1258. pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
  1259. return 0;
  1260. }
  1261. static int intel_845_configure(void)
  1262. {
  1263. u32 temp;
  1264. u8 temp2;
  1265. struct aper_size_info_8 *current_size;
  1266. current_size = A_SIZE_8(agp_bridge->current_size);
  1267. /* aperture size */
  1268. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
  1269. if (agp_bridge->apbase_config != 0) {
  1270. pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
  1271. agp_bridge->apbase_config);
  1272. } else {
  1273. /* address to map to */
  1274. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1275. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1276. agp_bridge->apbase_config = temp;
  1277. }
  1278. /* attbase - aperture base */
  1279. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
  1280. /* agpctrl */
  1281. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
  1282. /* agpm */
  1283. pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
  1284. pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
  1285. /* clear any possible error conditions */
  1286. pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
  1287. intel_i830_setup_flush();
  1288. return 0;
  1289. }
  1290. static int intel_850_configure(void)
  1291. {
  1292. u32 temp;
  1293. u16 temp2;
  1294. struct aper_size_info_8 *current_size;
  1295. current_size = A_SIZE_8(agp_bridge->current_size);
  1296. /* aperture size */
  1297. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
  1298. /* address to map to */
  1299. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1300. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1301. /* attbase - aperture base */
  1302. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
  1303. /* agpctrl */
  1304. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
  1305. /* mcgcfg */
  1306. pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
  1307. pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
  1308. /* clear any possible AGP-related error conditions */
  1309. pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
  1310. return 0;
  1311. }
  1312. static int intel_860_configure(void)
  1313. {
  1314. u32 temp;
  1315. u16 temp2;
  1316. struct aper_size_info_8 *current_size;
  1317. current_size = A_SIZE_8(agp_bridge->current_size);
  1318. /* aperture size */
  1319. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
  1320. /* address to map to */
  1321. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1322. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1323. /* attbase - aperture base */
  1324. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
  1325. /* agpctrl */
  1326. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
  1327. /* mcgcfg */
  1328. pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
  1329. pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
  1330. /* clear any possible AGP-related error conditions */
  1331. pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
  1332. return 0;
  1333. }
  1334. static int intel_830mp_configure(void)
  1335. {
  1336. u32 temp;
  1337. u16 temp2;
  1338. struct aper_size_info_8 *current_size;
  1339. current_size = A_SIZE_8(agp_bridge->current_size);
  1340. /* aperture size */
  1341. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
  1342. /* address to map to */
  1343. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1344. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1345. /* attbase - aperture base */
  1346. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
  1347. /* agpctrl */
  1348. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
  1349. /* gmch */
  1350. pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
  1351. pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
  1352. /* clear any possible AGP-related error conditions */
  1353. pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
  1354. return 0;
  1355. }
  1356. static int intel_7505_configure(void)
  1357. {
  1358. u32 temp;
  1359. u16 temp2;
  1360. struct aper_size_info_8 *current_size;
  1361. current_size = A_SIZE_8(agp_bridge->current_size);
  1362. /* aperture size */
  1363. pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
  1364. /* address to map to */
  1365. pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
  1366. agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
  1367. /* attbase - aperture base */
  1368. pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
  1369. /* agpctrl */
  1370. pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
  1371. /* mchcfg */
  1372. pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
  1373. pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
  1374. return 0;
  1375. }
  1376. /* Setup function */
  1377. static const struct gatt_mask intel_generic_masks[] =
  1378. {
  1379. {.mask = 0x00000017, .type = 0}
  1380. };
  1381. static const struct aper_size_info_8 intel_815_sizes[2] =
  1382. {
  1383. {64, 16384, 4, 0},
  1384. {32, 8192, 3, 8},
  1385. };
  1386. static const struct aper_size_info_8 intel_8xx_sizes[7] =
  1387. {
  1388. {256, 65536, 6, 0},
  1389. {128, 32768, 5, 32},
  1390. {64, 16384, 4, 48},
  1391. {32, 8192, 3, 56},
  1392. {16, 4096, 2, 60},
  1393. {8, 2048, 1, 62},
  1394. {4, 1024, 0, 63}
  1395. };
  1396. static const struct aper_size_info_16 intel_generic_sizes[7] =
  1397. {
  1398. {256, 65536, 6, 0},
  1399. {128, 32768, 5, 32},
  1400. {64, 16384, 4, 48},
  1401. {32, 8192, 3, 56},
  1402. {16, 4096, 2, 60},
  1403. {8, 2048, 1, 62},
  1404. {4, 1024, 0, 63}
  1405. };
  1406. static const struct aper_size_info_8 intel_830mp_sizes[4] =
  1407. {
  1408. {256, 65536, 6, 0},
  1409. {128, 32768, 5, 32},
  1410. {64, 16384, 4, 48},
  1411. {32, 8192, 3, 56}
  1412. };
  1413. static const struct agp_bridge_driver intel_generic_driver = {
  1414. .owner = THIS_MODULE,
  1415. .aperture_sizes = intel_generic_sizes,
  1416. .size_type = U16_APER_SIZE,
  1417. .num_aperture_sizes = 7,
  1418. .configure = intel_configure,
  1419. .fetch_size = intel_fetch_size,
  1420. .cleanup = intel_cleanup,
  1421. .tlb_flush = intel_tlbflush,
  1422. .mask_memory = agp_generic_mask_memory,
  1423. .masks = intel_generic_masks,
  1424. .agp_enable = agp_generic_enable,
  1425. .cache_flush = global_cache_flush,
  1426. .create_gatt_table = agp_generic_create_gatt_table,
  1427. .free_gatt_table = agp_generic_free_gatt_table,
  1428. .insert_memory = agp_generic_insert_memory,
  1429. .remove_memory = agp_generic_remove_memory,
  1430. .alloc_by_type = agp_generic_alloc_by_type,
  1431. .free_by_type = agp_generic_free_by_type,
  1432. .agp_alloc_page = agp_generic_alloc_page,
  1433. .agp_alloc_pages = agp_generic_alloc_pages,
  1434. .agp_destroy_page = agp_generic_destroy_page,
  1435. .agp_destroy_pages = agp_generic_destroy_pages,
  1436. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1437. };
  1438. static const struct agp_bridge_driver intel_810_driver = {
  1439. .owner = THIS_MODULE,
  1440. .aperture_sizes = intel_i810_sizes,
  1441. .size_type = FIXED_APER_SIZE,
  1442. .num_aperture_sizes = 2,
  1443. .needs_scratch_page = true,
  1444. .configure = intel_i810_configure,
  1445. .fetch_size = intel_i810_fetch_size,
  1446. .cleanup = intel_i810_cleanup,
  1447. .tlb_flush = intel_i810_tlbflush,
  1448. .mask_memory = intel_i810_mask_memory,
  1449. .masks = intel_i810_masks,
  1450. .agp_enable = intel_i810_agp_enable,
  1451. .cache_flush = global_cache_flush,
  1452. .create_gatt_table = agp_generic_create_gatt_table,
  1453. .free_gatt_table = agp_generic_free_gatt_table,
  1454. .insert_memory = intel_i810_insert_entries,
  1455. .remove_memory = intel_i810_remove_entries,
  1456. .alloc_by_type = intel_i810_alloc_by_type,
  1457. .free_by_type = intel_i810_free_by_type,
  1458. .agp_alloc_page = agp_generic_alloc_page,
  1459. .agp_alloc_pages = agp_generic_alloc_pages,
  1460. .agp_destroy_page = agp_generic_destroy_page,
  1461. .agp_destroy_pages = agp_generic_destroy_pages,
  1462. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1463. };
  1464. static const struct agp_bridge_driver intel_815_driver = {
  1465. .owner = THIS_MODULE,
  1466. .aperture_sizes = intel_815_sizes,
  1467. .size_type = U8_APER_SIZE,
  1468. .num_aperture_sizes = 2,
  1469. .configure = intel_815_configure,
  1470. .fetch_size = intel_815_fetch_size,
  1471. .cleanup = intel_8xx_cleanup,
  1472. .tlb_flush = intel_8xx_tlbflush,
  1473. .mask_memory = agp_generic_mask_memory,
  1474. .masks = intel_generic_masks,
  1475. .agp_enable = agp_generic_enable,
  1476. .cache_flush = global_cache_flush,
  1477. .create_gatt_table = agp_generic_create_gatt_table,
  1478. .free_gatt_table = agp_generic_free_gatt_table,
  1479. .insert_memory = agp_generic_insert_memory,
  1480. .remove_memory = agp_generic_remove_memory,
  1481. .alloc_by_type = agp_generic_alloc_by_type,
  1482. .free_by_type = agp_generic_free_by_type,
  1483. .agp_alloc_page = agp_generic_alloc_page,
  1484. .agp_alloc_pages = agp_generic_alloc_pages,
  1485. .agp_destroy_page = agp_generic_destroy_page,
  1486. .agp_destroy_pages = agp_generic_destroy_pages,
  1487. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1488. };
  1489. static const struct agp_bridge_driver intel_830_driver = {
  1490. .owner = THIS_MODULE,
  1491. .aperture_sizes = intel_i830_sizes,
  1492. .size_type = FIXED_APER_SIZE,
  1493. .num_aperture_sizes = 4,
  1494. .needs_scratch_page = true,
  1495. .configure = intel_i830_configure,
  1496. .fetch_size = intel_i830_fetch_size,
  1497. .cleanup = intel_i830_cleanup,
  1498. .tlb_flush = intel_i810_tlbflush,
  1499. .mask_memory = intel_i810_mask_memory,
  1500. .masks = intel_i810_masks,
  1501. .agp_enable = intel_i810_agp_enable,
  1502. .cache_flush = global_cache_flush,
  1503. .create_gatt_table = intel_i830_create_gatt_table,
  1504. .free_gatt_table = intel_i830_free_gatt_table,
  1505. .insert_memory = intel_i830_insert_entries,
  1506. .remove_memory = intel_i830_remove_entries,
  1507. .alloc_by_type = intel_i830_alloc_by_type,
  1508. .free_by_type = intel_i810_free_by_type,
  1509. .agp_alloc_page = agp_generic_alloc_page,
  1510. .agp_alloc_pages = agp_generic_alloc_pages,
  1511. .agp_destroy_page = agp_generic_destroy_page,
  1512. .agp_destroy_pages = agp_generic_destroy_pages,
  1513. .agp_type_to_mask_type = intel_i830_type_to_mask_type,
  1514. .chipset_flush = intel_i830_chipset_flush,
  1515. };
  1516. static const struct agp_bridge_driver intel_820_driver = {
  1517. .owner = THIS_MODULE,
  1518. .aperture_sizes = intel_8xx_sizes,
  1519. .size_type = U8_APER_SIZE,
  1520. .num_aperture_sizes = 7,
  1521. .configure = intel_820_configure,
  1522. .fetch_size = intel_8xx_fetch_size,
  1523. .cleanup = intel_820_cleanup,
  1524. .tlb_flush = intel_820_tlbflush,
  1525. .mask_memory = agp_generic_mask_memory,
  1526. .masks = intel_generic_masks,
  1527. .agp_enable = agp_generic_enable,
  1528. .cache_flush = global_cache_flush,
  1529. .create_gatt_table = agp_generic_create_gatt_table,
  1530. .free_gatt_table = agp_generic_free_gatt_table,
  1531. .insert_memory = agp_generic_insert_memory,
  1532. .remove_memory = agp_generic_remove_memory,
  1533. .alloc_by_type = agp_generic_alloc_by_type,
  1534. .free_by_type = agp_generic_free_by_type,
  1535. .agp_alloc_page = agp_generic_alloc_page,
  1536. .agp_alloc_pages = agp_generic_alloc_pages,
  1537. .agp_destroy_page = agp_generic_destroy_page,
  1538. .agp_destroy_pages = agp_generic_destroy_pages,
  1539. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1540. };
  1541. static const struct agp_bridge_driver intel_830mp_driver = {
  1542. .owner = THIS_MODULE,
  1543. .aperture_sizes = intel_830mp_sizes,
  1544. .size_type = U8_APER_SIZE,
  1545. .num_aperture_sizes = 4,
  1546. .configure = intel_830mp_configure,
  1547. .fetch_size = intel_8xx_fetch_size,
  1548. .cleanup = intel_8xx_cleanup,
  1549. .tlb_flush = intel_8xx_tlbflush,
  1550. .mask_memory = agp_generic_mask_memory,
  1551. .masks = intel_generic_masks,
  1552. .agp_enable = agp_generic_enable,
  1553. .cache_flush = global_cache_flush,
  1554. .create_gatt_table = agp_generic_create_gatt_table,
  1555. .free_gatt_table = agp_generic_free_gatt_table,
  1556. .insert_memory = agp_generic_insert_memory,
  1557. .remove_memory = agp_generic_remove_memory,
  1558. .alloc_by_type = agp_generic_alloc_by_type,
  1559. .free_by_type = agp_generic_free_by_type,
  1560. .agp_alloc_page = agp_generic_alloc_page,
  1561. .agp_alloc_pages = agp_generic_alloc_pages,
  1562. .agp_destroy_page = agp_generic_destroy_page,
  1563. .agp_destroy_pages = agp_generic_destroy_pages,
  1564. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1565. };
  1566. static const struct agp_bridge_driver intel_840_driver = {
  1567. .owner = THIS_MODULE,
  1568. .aperture_sizes = intel_8xx_sizes,
  1569. .size_type = U8_APER_SIZE,
  1570. .num_aperture_sizes = 7,
  1571. .configure = intel_840_configure,
  1572. .fetch_size = intel_8xx_fetch_size,
  1573. .cleanup = intel_8xx_cleanup,
  1574. .tlb_flush = intel_8xx_tlbflush,
  1575. .mask_memory = agp_generic_mask_memory,
  1576. .masks = intel_generic_masks,
  1577. .agp_enable = agp_generic_enable,
  1578. .cache_flush = global_cache_flush,
  1579. .create_gatt_table = agp_generic_create_gatt_table,
  1580. .free_gatt_table = agp_generic_free_gatt_table,
  1581. .insert_memory = agp_generic_insert_memory,
  1582. .remove_memory = agp_generic_remove_memory,
  1583. .alloc_by_type = agp_generic_alloc_by_type,
  1584. .free_by_type = agp_generic_free_by_type,
  1585. .agp_alloc_page = agp_generic_alloc_page,
  1586. .agp_alloc_pages = agp_generic_alloc_pages,
  1587. .agp_destroy_page = agp_generic_destroy_page,
  1588. .agp_destroy_pages = agp_generic_destroy_pages,
  1589. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1590. };
  1591. static const struct agp_bridge_driver intel_845_driver = {
  1592. .owner = THIS_MODULE,
  1593. .aperture_sizes = intel_8xx_sizes,
  1594. .size_type = U8_APER_SIZE,
  1595. .num_aperture_sizes = 7,
  1596. .configure = intel_845_configure,
  1597. .fetch_size = intel_8xx_fetch_size,
  1598. .cleanup = intel_8xx_cleanup,
  1599. .tlb_flush = intel_8xx_tlbflush,
  1600. .mask_memory = agp_generic_mask_memory,
  1601. .masks = intel_generic_masks,
  1602. .agp_enable = agp_generic_enable,
  1603. .cache_flush = global_cache_flush,
  1604. .create_gatt_table = agp_generic_create_gatt_table,
  1605. .free_gatt_table = agp_generic_free_gatt_table,
  1606. .insert_memory = agp_generic_insert_memory,
  1607. .remove_memory = agp_generic_remove_memory,
  1608. .alloc_by_type = agp_generic_alloc_by_type,
  1609. .free_by_type = agp_generic_free_by_type,
  1610. .agp_alloc_page = agp_generic_alloc_page,
  1611. .agp_alloc_pages = agp_generic_alloc_pages,
  1612. .agp_destroy_page = agp_generic_destroy_page,
  1613. .agp_destroy_pages = agp_generic_destroy_pages,
  1614. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1615. .chipset_flush = intel_i830_chipset_flush,
  1616. };
  1617. static const struct agp_bridge_driver intel_850_driver = {
  1618. .owner = THIS_MODULE,
  1619. .aperture_sizes = intel_8xx_sizes,
  1620. .size_type = U8_APER_SIZE,
  1621. .num_aperture_sizes = 7,
  1622. .configure = intel_850_configure,
  1623. .fetch_size = intel_8xx_fetch_size,
  1624. .cleanup = intel_8xx_cleanup,
  1625. .tlb_flush = intel_8xx_tlbflush,
  1626. .mask_memory = agp_generic_mask_memory,
  1627. .masks = intel_generic_masks,
  1628. .agp_enable = agp_generic_enable,
  1629. .cache_flush = global_cache_flush,
  1630. .create_gatt_table = agp_generic_create_gatt_table,
  1631. .free_gatt_table = agp_generic_free_gatt_table,
  1632. .insert_memory = agp_generic_insert_memory,
  1633. .remove_memory = agp_generic_remove_memory,
  1634. .alloc_by_type = agp_generic_alloc_by_type,
  1635. .free_by_type = agp_generic_free_by_type,
  1636. .agp_alloc_page = agp_generic_alloc_page,
  1637. .agp_alloc_pages = agp_generic_alloc_pages,
  1638. .agp_destroy_page = agp_generic_destroy_page,
  1639. .agp_destroy_pages = agp_generic_destroy_pages,
  1640. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1641. };
  1642. static const struct agp_bridge_driver intel_860_driver = {
  1643. .owner = THIS_MODULE,
  1644. .aperture_sizes = intel_8xx_sizes,
  1645. .size_type = U8_APER_SIZE,
  1646. .num_aperture_sizes = 7,
  1647. .configure = intel_860_configure,
  1648. .fetch_size = intel_8xx_fetch_size,
  1649. .cleanup = intel_8xx_cleanup,
  1650. .tlb_flush = intel_8xx_tlbflush,
  1651. .mask_memory = agp_generic_mask_memory,
  1652. .masks = intel_generic_masks,
  1653. .agp_enable = agp_generic_enable,
  1654. .cache_flush = global_cache_flush,
  1655. .create_gatt_table = agp_generic_create_gatt_table,
  1656. .free_gatt_table = agp_generic_free_gatt_table,
  1657. .insert_memory = agp_generic_insert_memory,
  1658. .remove_memory = agp_generic_remove_memory,
  1659. .alloc_by_type = agp_generic_alloc_by_type,
  1660. .free_by_type = agp_generic_free_by_type,
  1661. .agp_alloc_page = agp_generic_alloc_page,
  1662. .agp_alloc_pages = agp_generic_alloc_pages,
  1663. .agp_destroy_page = agp_generic_destroy_page,
  1664. .agp_destroy_pages = agp_generic_destroy_pages,
  1665. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1666. };
  1667. static const struct agp_bridge_driver intel_915_driver = {
  1668. .owner = THIS_MODULE,
  1669. .aperture_sizes = intel_i830_sizes,
  1670. .size_type = FIXED_APER_SIZE,
  1671. .num_aperture_sizes = 4,
  1672. .needs_scratch_page = true,
  1673. .configure = intel_i915_configure,
  1674. .fetch_size = intel_i9xx_fetch_size,
  1675. .cleanup = intel_i915_cleanup,
  1676. .tlb_flush = intel_i810_tlbflush,
  1677. .mask_memory = intel_i810_mask_memory,
  1678. .masks = intel_i810_masks,
  1679. .agp_enable = intel_i810_agp_enable,
  1680. .cache_flush = global_cache_flush,
  1681. .create_gatt_table = intel_i915_create_gatt_table,
  1682. .free_gatt_table = intel_i830_free_gatt_table,
  1683. .insert_memory = intel_i915_insert_entries,
  1684. .remove_memory = intel_i915_remove_entries,
  1685. .alloc_by_type = intel_i830_alloc_by_type,
  1686. .free_by_type = intel_i810_free_by_type,
  1687. .agp_alloc_page = agp_generic_alloc_page,
  1688. .agp_alloc_pages = agp_generic_alloc_pages,
  1689. .agp_destroy_page = agp_generic_destroy_page,
  1690. .agp_destroy_pages = agp_generic_destroy_pages,
  1691. .agp_type_to_mask_type = intel_i830_type_to_mask_type,
  1692. .chipset_flush = intel_i915_chipset_flush,
  1693. };
  1694. static const struct agp_bridge_driver intel_i965_driver = {
  1695. .owner = THIS_MODULE,
  1696. .aperture_sizes = intel_i830_sizes,
  1697. .size_type = FIXED_APER_SIZE,
  1698. .num_aperture_sizes = 4,
  1699. .needs_scratch_page = true,
  1700. .configure = intel_i915_configure,
  1701. .fetch_size = intel_i9xx_fetch_size,
  1702. .cleanup = intel_i915_cleanup,
  1703. .tlb_flush = intel_i810_tlbflush,
  1704. .mask_memory = intel_i965_mask_memory,
  1705. .masks = intel_i810_masks,
  1706. .agp_enable = intel_i810_agp_enable,
  1707. .cache_flush = global_cache_flush,
  1708. .create_gatt_table = intel_i965_create_gatt_table,
  1709. .free_gatt_table = intel_i830_free_gatt_table,
  1710. .insert_memory = intel_i915_insert_entries,
  1711. .remove_memory = intel_i915_remove_entries,
  1712. .alloc_by_type = intel_i830_alloc_by_type,
  1713. .free_by_type = intel_i810_free_by_type,
  1714. .agp_alloc_page = agp_generic_alloc_page,
  1715. .agp_alloc_pages = agp_generic_alloc_pages,
  1716. .agp_destroy_page = agp_generic_destroy_page,
  1717. .agp_destroy_pages = agp_generic_destroy_pages,
  1718. .agp_type_to_mask_type = intel_i830_type_to_mask_type,
  1719. .chipset_flush = intel_i915_chipset_flush,
  1720. };
  1721. static const struct agp_bridge_driver intel_7505_driver = {
  1722. .owner = THIS_MODULE,
  1723. .aperture_sizes = intel_8xx_sizes,
  1724. .size_type = U8_APER_SIZE,
  1725. .num_aperture_sizes = 7,
  1726. .configure = intel_7505_configure,
  1727. .fetch_size = intel_8xx_fetch_size,
  1728. .cleanup = intel_8xx_cleanup,
  1729. .tlb_flush = intel_8xx_tlbflush,
  1730. .mask_memory = agp_generic_mask_memory,
  1731. .masks = intel_generic_masks,
  1732. .agp_enable = agp_generic_enable,
  1733. .cache_flush = global_cache_flush,
  1734. .create_gatt_table = agp_generic_create_gatt_table,
  1735. .free_gatt_table = agp_generic_free_gatt_table,
  1736. .insert_memory = agp_generic_insert_memory,
  1737. .remove_memory = agp_generic_remove_memory,
  1738. .alloc_by_type = agp_generic_alloc_by_type,
  1739. .free_by_type = agp_generic_free_by_type,
  1740. .agp_alloc_page = agp_generic_alloc_page,
  1741. .agp_alloc_pages = agp_generic_alloc_pages,
  1742. .agp_destroy_page = agp_generic_destroy_page,
  1743. .agp_destroy_pages = agp_generic_destroy_pages,
  1744. .agp_type_to_mask_type = agp_generic_type_to_mask_type,
  1745. };
  1746. static const struct agp_bridge_driver intel_g33_driver = {
  1747. .owner = THIS_MODULE,
  1748. .aperture_sizes = intel_i830_sizes,
  1749. .size_type = FIXED_APER_SIZE,
  1750. .num_aperture_sizes = 4,
  1751. .needs_scratch_page = true,
  1752. .configure = intel_i915_configure,
  1753. .fetch_size = intel_i9xx_fetch_size,
  1754. .cleanup = intel_i915_cleanup,
  1755. .tlb_flush = intel_i810_tlbflush,
  1756. .mask_memory = intel_i965_mask_memory,
  1757. .masks = intel_i810_masks,
  1758. .agp_enable = intel_i810_agp_enable,
  1759. .cache_flush = global_cache_flush,
  1760. .create_gatt_table = intel_i915_create_gatt_table,
  1761. .free_gatt_table = intel_i830_free_gatt_table,
  1762. .insert_memory = intel_i915_insert_entries,
  1763. .remove_memory = intel_i915_remove_entries,
  1764. .alloc_by_type = intel_i830_alloc_by_type,
  1765. .free_by_type = intel_i810_free_by_type,
  1766. .agp_alloc_page = agp_generic_alloc_page,
  1767. .agp_alloc_pages = agp_generic_alloc_pages,
  1768. .agp_destroy_page = agp_generic_destroy_page,
  1769. .agp_destroy_pages = agp_generic_destroy_pages,
  1770. .agp_type_to_mask_type = intel_i830_type_to_mask_type,
  1771. .chipset_flush = intel_i915_chipset_flush,
  1772. };
  1773. static int find_gmch(u16 device)
  1774. {
  1775. struct pci_dev *gmch_device;
  1776. gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
  1777. if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
  1778. gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
  1779. device, gmch_device);
  1780. }
  1781. if (!gmch_device)
  1782. return 0;
  1783. intel_private.pcidev = gmch_device;
  1784. return 1;
  1785. }
  1786. /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
  1787. * driver and gmch_driver must be non-null, and find_gmch will determine
  1788. * which one should be used if a gmch_chip_id is present.
  1789. */
  1790. static const struct intel_driver_description {
  1791. unsigned int chip_id;
  1792. unsigned int gmch_chip_id;
  1793. unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
  1794. char *name;
  1795. const struct agp_bridge_driver *driver;
  1796. const struct agp_bridge_driver *gmch_driver;
  1797. } intel_agp_chipsets[] = {
  1798. { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
  1799. { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
  1800. { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
  1801. { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
  1802. NULL, &intel_810_driver },
  1803. { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
  1804. NULL, &intel_810_driver },
  1805. { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
  1806. NULL, &intel_810_driver },
  1807. { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
  1808. &intel_815_driver, &intel_810_driver },
  1809. { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
  1810. { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
  1811. { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
  1812. &intel_830mp_driver, &intel_830_driver },
  1813. { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
  1814. { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
  1815. { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
  1816. &intel_845_driver, &intel_830_driver },
  1817. { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
  1818. { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
  1819. &intel_845_driver, &intel_830_driver },
  1820. { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
  1821. { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
  1822. &intel_845_driver, &intel_830_driver },
  1823. { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
  1824. { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
  1825. &intel_845_driver, &intel_830_driver },
  1826. { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
  1827. { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
  1828. NULL, &intel_915_driver },
  1829. { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
  1830. NULL, &intel_915_driver },
  1831. { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
  1832. NULL, &intel_915_driver },
  1833. { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
  1834. NULL, &intel_915_driver },
  1835. { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
  1836. NULL, &intel_915_driver },
  1837. { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
  1838. NULL, &intel_915_driver },
  1839. { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
  1840. NULL, &intel_i965_driver },
  1841. { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
  1842. NULL, &intel_i965_driver },
  1843. { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
  1844. NULL, &intel_i965_driver },
  1845. { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
  1846. NULL, &intel_i965_driver },
  1847. { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
  1848. NULL, &intel_i965_driver },
  1849. { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
  1850. NULL, &intel_i965_driver },
  1851. { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
  1852. { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
  1853. { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
  1854. NULL, &intel_g33_driver },
  1855. { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
  1856. NULL, &intel_g33_driver },
  1857. { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
  1858. NULL, &intel_g33_driver },
  1859. { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
  1860. NULL, &intel_g33_driver },
  1861. { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
  1862. NULL, &intel_g33_driver },
  1863. { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
  1864. "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
  1865. { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
  1866. "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
  1867. { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
  1868. "Q45/Q43", NULL, &intel_i965_driver },
  1869. { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
  1870. "G45/G43", NULL, &intel_i965_driver },
  1871. { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
  1872. "G41", NULL, &intel_i965_driver },
  1873. { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
  1874. "IGDNG/D", NULL, &intel_i965_driver },
  1875. { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
  1876. "IGDNG/M", NULL, &intel_i965_driver },
  1877. { 0, 0, 0, NULL, NULL, NULL }
  1878. };
  1879. static int __devinit agp_intel_probe(struct pci_dev *pdev,
  1880. const struct pci_device_id *ent)
  1881. {
  1882. struct agp_bridge_data *bridge;
  1883. u8 cap_ptr = 0;
  1884. struct resource *r;
  1885. int i;
  1886. cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
  1887. bridge = agp_alloc_bridge();
  1888. if (!bridge)
  1889. return -ENOMEM;
  1890. for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
  1891. /* In case that multiple models of gfx chip may
  1892. stand on same host bridge type, this can be
  1893. sure we detect the right IGD. */
  1894. if (pdev->device == intel_agp_chipsets[i].chip_id) {
  1895. if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
  1896. find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
  1897. bridge->driver =
  1898. intel_agp_chipsets[i].gmch_driver;
  1899. break;
  1900. } else if (intel_agp_chipsets[i].multi_gmch_chip) {
  1901. continue;
  1902. } else {
  1903. bridge->driver = intel_agp_chipsets[i].driver;
  1904. break;
  1905. }
  1906. }
  1907. }
  1908. if (intel_agp_chipsets[i].name == NULL) {
  1909. if (cap_ptr)
  1910. dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
  1911. pdev->vendor, pdev->device);
  1912. agp_put_bridge(bridge);
  1913. return -ENODEV;
  1914. }
  1915. if (bridge->driver == NULL) {
  1916. /* bridge has no AGP and no IGD detected */
  1917. if (cap_ptr)
  1918. dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
  1919. intel_agp_chipsets[i].gmch_chip_id);
  1920. agp_put_bridge(bridge);
  1921. return -ENODEV;
  1922. }
  1923. bridge->dev = pdev;
  1924. bridge->capndx = cap_ptr;
  1925. bridge->dev_private_data = &intel_private;
  1926. dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
  1927. /*
  1928. * The following fixes the case where the BIOS has "forgotten" to
  1929. * provide an address range for the GART.
  1930. * 20030610 - hamish@zot.org
  1931. */
  1932. r = &pdev->resource[0];
  1933. if (!r->start && r->end) {
  1934. if (pci_assign_resource(pdev, 0)) {
  1935. dev_err(&pdev->dev, "can't assign resource 0\n");
  1936. agp_put_bridge(bridge);
  1937. return -ENODEV;
  1938. }
  1939. }
  1940. /*
  1941. * If the device has not been properly setup, the following will catch
  1942. * the problem and should stop the system from crashing.
  1943. * 20030610 - hamish@zot.org
  1944. */
  1945. if (pci_enable_device(pdev)) {
  1946. dev_err(&pdev->dev, "can't enable PCI device\n");
  1947. agp_put_bridge(bridge);
  1948. return -ENODEV;
  1949. }
  1950. /* Fill in the mode register */
  1951. if (cap_ptr) {
  1952. pci_read_config_dword(pdev,
  1953. bridge->capndx+PCI_AGP_STATUS,
  1954. &bridge->mode);
  1955. }
  1956. pci_set_drvdata(pdev, bridge);
  1957. return agp_add_bridge(bridge);
  1958. }
  1959. static void __devexit agp_intel_remove(struct pci_dev *pdev)
  1960. {
  1961. struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
  1962. agp_remove_bridge(bridge);
  1963. if (intel_private.pcidev)
  1964. pci_dev_put(intel_private.pcidev);
  1965. agp_put_bridge(bridge);
  1966. }
  1967. #ifdef CONFIG_PM
  1968. static int agp_intel_resume(struct pci_dev *pdev)
  1969. {
  1970. struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
  1971. int ret_val;
  1972. pci_restore_state(pdev);
  1973. /* We should restore our graphics device's config space,
  1974. * as host bridge (00:00) resumes before graphics device (02:00),
  1975. * then our access to its pci space can work right.
  1976. */
  1977. if (intel_private.pcidev)
  1978. pci_restore_state(intel_private.pcidev);
  1979. if (bridge->driver == &intel_generic_driver)
  1980. intel_configure();
  1981. else if (bridge->driver == &intel_850_driver)
  1982. intel_850_configure();
  1983. else if (bridge->driver == &intel_845_driver)
  1984. intel_845_configure();
  1985. else if (bridge->driver == &intel_830mp_driver)
  1986. intel_830mp_configure();
  1987. else if (bridge->driver == &intel_915_driver)
  1988. intel_i915_configure();
  1989. else if (bridge->driver == &intel_830_driver)
  1990. intel_i830_configure();
  1991. else if (bridge->driver == &intel_810_driver)
  1992. intel_i810_configure();
  1993. else if (bridge->driver == &intel_i965_driver)
  1994. intel_i915_configure();
  1995. ret_val = agp_rebind_memory();
  1996. if (ret_val != 0)
  1997. return ret_val;
  1998. return 0;
  1999. }
  2000. #endif
  2001. static struct pci_device_id agp_intel_pci_table[] = {
  2002. #define ID(x) \
  2003. { \
  2004. .class = (PCI_CLASS_BRIDGE_HOST << 8), \
  2005. .class_mask = ~0, \
  2006. .vendor = PCI_VENDOR_ID_INTEL, \
  2007. .device = x, \
  2008. .subvendor = PCI_ANY_ID, \
  2009. .subdevice = PCI_ANY_ID, \
  2010. }
  2011. ID(PCI_DEVICE_ID_INTEL_82443LX_0),
  2012. ID(PCI_DEVICE_ID_INTEL_82443BX_0),
  2013. ID(PCI_DEVICE_ID_INTEL_82443GX_0),
  2014. ID(PCI_DEVICE_ID_INTEL_82810_MC1),
  2015. ID(PCI_DEVICE_ID_INTEL_82810_MC3),
  2016. ID(PCI_DEVICE_ID_INTEL_82810E_MC),
  2017. ID(PCI_DEVICE_ID_INTEL_82815_MC),
  2018. ID(PCI_DEVICE_ID_INTEL_82820_HB),
  2019. ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
  2020. ID(PCI_DEVICE_ID_INTEL_82830_HB),
  2021. ID(PCI_DEVICE_ID_INTEL_82840_HB),
  2022. ID(PCI_DEVICE_ID_INTEL_82845_HB),
  2023. ID(PCI_DEVICE_ID_INTEL_82845G_HB),
  2024. ID(PCI_DEVICE_ID_INTEL_82850_HB),
  2025. ID(PCI_DEVICE_ID_INTEL_82854_HB),
  2026. ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
  2027. ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
  2028. ID(PCI_DEVICE_ID_INTEL_82860_HB),
  2029. ID(PCI_DEVICE_ID_INTEL_82865_HB),
  2030. ID(PCI_DEVICE_ID_INTEL_82875_HB),
  2031. ID(PCI_DEVICE_ID_INTEL_7505_0),
  2032. ID(PCI_DEVICE_ID_INTEL_7205_0),
  2033. ID(PCI_DEVICE_ID_INTEL_E7221_HB),
  2034. ID(PCI_DEVICE_ID_INTEL_82915G_HB),
  2035. ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
  2036. ID(PCI_DEVICE_ID_INTEL_82945G_HB),
  2037. ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
  2038. ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
  2039. ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
  2040. ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
  2041. ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
  2042. ID(PCI_DEVICE_ID_INTEL_82G35_HB),
  2043. ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
  2044. ID(PCI_DEVICE_ID_INTEL_82965G_HB),
  2045. ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
  2046. ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
  2047. ID(PCI_DEVICE_ID_INTEL_G33_HB),
  2048. ID(PCI_DEVICE_ID_INTEL_Q35_HB),
  2049. ID(PCI_DEVICE_ID_INTEL_Q33_HB),
  2050. ID(PCI_DEVICE_ID_INTEL_GM45_HB),
  2051. ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
  2052. ID(PCI_DEVICE_ID_INTEL_Q45_HB),
  2053. ID(PCI_DEVICE_ID_INTEL_G45_HB),
  2054. ID(PCI_DEVICE_ID_INTEL_G41_HB),
  2055. ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
  2056. ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
  2057. { }
  2058. };
  2059. MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
  2060. static struct pci_driver agp_intel_pci_driver = {
  2061. .name = "agpgart-intel",
  2062. .id_table = agp_intel_pci_table,
  2063. .probe = agp_intel_probe,
  2064. .remove = __devexit_p(agp_intel_remove),
  2065. #ifdef CONFIG_PM
  2066. .resume = agp_intel_resume,
  2067. #endif
  2068. };
  2069. static int __init agp_intel_init(void)
  2070. {
  2071. if (agp_off)
  2072. return -EINVAL;
  2073. return pci_register_driver(&agp_intel_pci_driver);
  2074. }
  2075. static void __exit agp_intel_cleanup(void)
  2076. {
  2077. pci_unregister_driver(&agp_intel_pci_driver);
  2078. }
  2079. module_init(agp_intel_init);
  2080. module_exit(agp_intel_cleanup);
  2081. MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
  2082. MODULE_LICENSE("GPL and additional rights");