devs.c 9.5 KB

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  1. /* linux/arch/arm/plat-s3c24xx/devs.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Base S3C24XX platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <asm/mach/arch.h>
  23. #include <asm/mach/map.h>
  24. #include <asm/mach/irq.h>
  25. #include <mach/fb.h>
  26. #include <mach/hardware.h>
  27. #include <asm/irq.h>
  28. #include <plat/regs-serial.h>
  29. #include <plat/udc.h>
  30. #include <plat/devs.h>
  31. #include <plat/cpu.h>
  32. #include <plat/regs-spi.h>
  33. /* Serial port registrations */
  34. static struct resource s3c2410_uart0_resource[] = {
  35. [0] = {
  36. .start = S3C2410_PA_UART0,
  37. .end = S3C2410_PA_UART0 + 0x3fff,
  38. .flags = IORESOURCE_MEM,
  39. },
  40. [1] = {
  41. .start = IRQ_S3CUART_RX0,
  42. .end = IRQ_S3CUART_ERR0,
  43. .flags = IORESOURCE_IRQ,
  44. }
  45. };
  46. static struct resource s3c2410_uart1_resource[] = {
  47. [0] = {
  48. .start = S3C2410_PA_UART1,
  49. .end = S3C2410_PA_UART1 + 0x3fff,
  50. .flags = IORESOURCE_MEM,
  51. },
  52. [1] = {
  53. .start = IRQ_S3CUART_RX1,
  54. .end = IRQ_S3CUART_ERR1,
  55. .flags = IORESOURCE_IRQ,
  56. }
  57. };
  58. static struct resource s3c2410_uart2_resource[] = {
  59. [0] = {
  60. .start = S3C2410_PA_UART2,
  61. .end = S3C2410_PA_UART2 + 0x3fff,
  62. .flags = IORESOURCE_MEM,
  63. },
  64. [1] = {
  65. .start = IRQ_S3CUART_RX2,
  66. .end = IRQ_S3CUART_ERR2,
  67. .flags = IORESOURCE_IRQ,
  68. }
  69. };
  70. static struct resource s3c2410_uart3_resource[] = {
  71. [0] = {
  72. .start = S3C2443_PA_UART3,
  73. .end = S3C2443_PA_UART3 + 0x3fff,
  74. .flags = IORESOURCE_MEM,
  75. },
  76. [1] = {
  77. .start = IRQ_S3CUART_RX3,
  78. .end = IRQ_S3CUART_ERR3,
  79. .flags = IORESOURCE_IRQ,
  80. },
  81. };
  82. struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
  83. [0] = {
  84. .resources = s3c2410_uart0_resource,
  85. .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
  86. },
  87. [1] = {
  88. .resources = s3c2410_uart1_resource,
  89. .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
  90. },
  91. [2] = {
  92. .resources = s3c2410_uart2_resource,
  93. .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
  94. },
  95. [3] = {
  96. .resources = s3c2410_uart3_resource,
  97. .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
  98. },
  99. };
  100. /* yart devices */
  101. static struct platform_device s3c24xx_uart_device0 = {
  102. .id = 0,
  103. };
  104. static struct platform_device s3c24xx_uart_device1 = {
  105. .id = 1,
  106. };
  107. static struct platform_device s3c24xx_uart_device2 = {
  108. .id = 2,
  109. };
  110. static struct platform_device s3c24xx_uart_device3 = {
  111. .id = 3,
  112. };
  113. struct platform_device *s3c24xx_uart_src[4] = {
  114. &s3c24xx_uart_device0,
  115. &s3c24xx_uart_device1,
  116. &s3c24xx_uart_device2,
  117. &s3c24xx_uart_device3,
  118. };
  119. struct platform_device *s3c24xx_uart_devs[4] = {
  120. };
  121. /* LCD Controller */
  122. static struct resource s3c_lcd_resource[] = {
  123. [0] = {
  124. .start = S3C24XX_PA_LCD,
  125. .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
  126. .flags = IORESOURCE_MEM,
  127. },
  128. [1] = {
  129. .start = IRQ_LCD,
  130. .end = IRQ_LCD,
  131. .flags = IORESOURCE_IRQ,
  132. }
  133. };
  134. static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
  135. struct platform_device s3c_device_lcd = {
  136. .name = "s3c2410-lcd",
  137. .id = -1,
  138. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  139. .resource = s3c_lcd_resource,
  140. .dev = {
  141. .dma_mask = &s3c_device_lcd_dmamask,
  142. .coherent_dma_mask = 0xffffffffUL
  143. }
  144. };
  145. EXPORT_SYMBOL(s3c_device_lcd);
  146. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  147. {
  148. struct s3c2410fb_mach_info *npd;
  149. npd = kmalloc(sizeof(*npd), GFP_KERNEL);
  150. if (npd) {
  151. memcpy(npd, pd, sizeof(*npd));
  152. s3c_device_lcd.dev.platform_data = npd;
  153. } else {
  154. printk(KERN_ERR "no memory for LCD platform data\n");
  155. }
  156. }
  157. /* NAND Controller */
  158. static struct resource s3c_nand_resource[] = {
  159. [0] = {
  160. .start = S3C24XX_PA_NAND,
  161. .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
  162. .flags = IORESOURCE_MEM,
  163. }
  164. };
  165. struct platform_device s3c_device_nand = {
  166. .name = "s3c2410-nand",
  167. .id = -1,
  168. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  169. .resource = s3c_nand_resource,
  170. };
  171. EXPORT_SYMBOL(s3c_device_nand);
  172. /* USB Device (Gadget)*/
  173. static struct resource s3c_usbgadget_resource[] = {
  174. [0] = {
  175. .start = S3C24XX_PA_USBDEV,
  176. .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
  177. .flags = IORESOURCE_MEM,
  178. },
  179. [1] = {
  180. .start = IRQ_USBD,
  181. .end = IRQ_USBD,
  182. .flags = IORESOURCE_IRQ,
  183. }
  184. };
  185. struct platform_device s3c_device_usbgadget = {
  186. .name = "s3c2410-usbgadget",
  187. .id = -1,
  188. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  189. .resource = s3c_usbgadget_resource,
  190. };
  191. EXPORT_SYMBOL(s3c_device_usbgadget);
  192. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  193. {
  194. struct s3c2410_udc_mach_info *npd;
  195. npd = kmalloc(sizeof(*npd), GFP_KERNEL);
  196. if (npd) {
  197. memcpy(npd, pd, sizeof(*npd));
  198. s3c_device_usbgadget.dev.platform_data = npd;
  199. } else {
  200. printk(KERN_ERR "no memory for udc platform data\n");
  201. }
  202. }
  203. /* Watchdog */
  204. static struct resource s3c_wdt_resource[] = {
  205. [0] = {
  206. .start = S3C24XX_PA_WATCHDOG,
  207. .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
  208. .flags = IORESOURCE_MEM,
  209. },
  210. [1] = {
  211. .start = IRQ_WDT,
  212. .end = IRQ_WDT,
  213. .flags = IORESOURCE_IRQ,
  214. }
  215. };
  216. struct platform_device s3c_device_wdt = {
  217. .name = "s3c2410-wdt",
  218. .id = -1,
  219. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  220. .resource = s3c_wdt_resource,
  221. };
  222. EXPORT_SYMBOL(s3c_device_wdt);
  223. /* IIS */
  224. static struct resource s3c_iis_resource[] = {
  225. [0] = {
  226. .start = S3C24XX_PA_IIS,
  227. .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
  228. .flags = IORESOURCE_MEM,
  229. }
  230. };
  231. static u64 s3c_device_iis_dmamask = 0xffffffffUL;
  232. struct platform_device s3c_device_iis = {
  233. .name = "s3c2410-iis",
  234. .id = -1,
  235. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  236. .resource = s3c_iis_resource,
  237. .dev = {
  238. .dma_mask = &s3c_device_iis_dmamask,
  239. .coherent_dma_mask = 0xffffffffUL
  240. }
  241. };
  242. EXPORT_SYMBOL(s3c_device_iis);
  243. /* RTC */
  244. static struct resource s3c_rtc_resource[] = {
  245. [0] = {
  246. .start = S3C24XX_PA_RTC,
  247. .end = S3C24XX_PA_RTC + 0xff,
  248. .flags = IORESOURCE_MEM,
  249. },
  250. [1] = {
  251. .start = IRQ_RTC,
  252. .end = IRQ_RTC,
  253. .flags = IORESOURCE_IRQ,
  254. },
  255. [2] = {
  256. .start = IRQ_TICK,
  257. .end = IRQ_TICK,
  258. .flags = IORESOURCE_IRQ
  259. }
  260. };
  261. struct platform_device s3c_device_rtc = {
  262. .name = "s3c2410-rtc",
  263. .id = -1,
  264. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  265. .resource = s3c_rtc_resource,
  266. };
  267. EXPORT_SYMBOL(s3c_device_rtc);
  268. /* ADC */
  269. static struct resource s3c_adc_resource[] = {
  270. [0] = {
  271. .start = S3C24XX_PA_ADC,
  272. .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
  273. .flags = IORESOURCE_MEM,
  274. },
  275. [1] = {
  276. .start = IRQ_TC,
  277. .end = IRQ_TC,
  278. .flags = IORESOURCE_IRQ,
  279. },
  280. [2] = {
  281. .start = IRQ_ADC,
  282. .end = IRQ_ADC,
  283. .flags = IORESOURCE_IRQ,
  284. }
  285. };
  286. struct platform_device s3c_device_adc = {
  287. .name = "s3c24xx-adc",
  288. .id = -1,
  289. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  290. .resource = s3c_adc_resource,
  291. };
  292. /* HWMON */
  293. struct platform_device s3c_device_hwmon = {
  294. .name = "s3c24xx-hwmon",
  295. .id = -1,
  296. .dev.parent = &s3c_device_adc.dev,
  297. };
  298. /* SDI */
  299. static struct resource s3c_sdi_resource[] = {
  300. [0] = {
  301. .start = S3C24XX_PA_SDI,
  302. .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
  303. .flags = IORESOURCE_MEM,
  304. },
  305. [1] = {
  306. .start = IRQ_SDI,
  307. .end = IRQ_SDI,
  308. .flags = IORESOURCE_IRQ,
  309. }
  310. };
  311. struct platform_device s3c_device_sdi = {
  312. .name = "s3c2410-sdi",
  313. .id = -1,
  314. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  315. .resource = s3c_sdi_resource,
  316. };
  317. EXPORT_SYMBOL(s3c_device_sdi);
  318. /* SPI (0) */
  319. static struct resource s3c_spi0_resource[] = {
  320. [0] = {
  321. .start = S3C24XX_PA_SPI,
  322. .end = S3C24XX_PA_SPI + 0x1f,
  323. .flags = IORESOURCE_MEM,
  324. },
  325. [1] = {
  326. .start = IRQ_SPI0,
  327. .end = IRQ_SPI0,
  328. .flags = IORESOURCE_IRQ,
  329. }
  330. };
  331. static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
  332. struct platform_device s3c_device_spi0 = {
  333. .name = "s3c2410-spi",
  334. .id = 0,
  335. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  336. .resource = s3c_spi0_resource,
  337. .dev = {
  338. .dma_mask = &s3c_device_spi0_dmamask,
  339. .coherent_dma_mask = 0xffffffffUL
  340. }
  341. };
  342. EXPORT_SYMBOL(s3c_device_spi0);
  343. /* SPI (1) */
  344. static struct resource s3c_spi1_resource[] = {
  345. [0] = {
  346. .start = S3C24XX_PA_SPI + S3C2410_SPI1,
  347. .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
  348. .flags = IORESOURCE_MEM,
  349. },
  350. [1] = {
  351. .start = IRQ_SPI1,
  352. .end = IRQ_SPI1,
  353. .flags = IORESOURCE_IRQ,
  354. }
  355. };
  356. static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
  357. struct platform_device s3c_device_spi1 = {
  358. .name = "s3c2410-spi",
  359. .id = 1,
  360. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  361. .resource = s3c_spi1_resource,
  362. .dev = {
  363. .dma_mask = &s3c_device_spi1_dmamask,
  364. .coherent_dma_mask = 0xffffffffUL
  365. }
  366. };
  367. EXPORT_SYMBOL(s3c_device_spi1);
  368. #ifdef CONFIG_CPU_S3C2440
  369. /* Camif Controller */
  370. static struct resource s3c_camif_resource[] = {
  371. [0] = {
  372. .start = S3C2440_PA_CAMIF,
  373. .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
  374. .flags = IORESOURCE_MEM,
  375. },
  376. [1] = {
  377. .start = IRQ_CAM,
  378. .end = IRQ_CAM,
  379. .flags = IORESOURCE_IRQ,
  380. }
  381. };
  382. static u64 s3c_device_camif_dmamask = 0xffffffffUL;
  383. struct platform_device s3c_device_camif = {
  384. .name = "s3c2440-camif",
  385. .id = -1,
  386. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  387. .resource = s3c_camif_resource,
  388. .dev = {
  389. .dma_mask = &s3c_device_camif_dmamask,
  390. .coherent_dma_mask = 0xffffffffUL
  391. }
  392. };
  393. EXPORT_SYMBOL(s3c_device_camif);
  394. #endif // CONFIG_CPU_S32440