stex.c 34 KB

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  1. /*
  2. * SuperTrak EX Series Storage Controller driver for Linux
  3. *
  4. * Copyright (C) 2005, 2006 Promise Technology Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Written By:
  12. * Ed Lin <promise_linux@promise.com>
  13. *
  14. */
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/kernel.h>
  18. #include <linux/delay.h>
  19. #include <linux/sched.h>
  20. #include <linux/time.h>
  21. #include <linux/pci.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/types.h>
  25. #include <linux/module.h>
  26. #include <linux/spinlock.h>
  27. #include <asm/io.h>
  28. #include <asm/irq.h>
  29. #include <asm/byteorder.h>
  30. #include <scsi/scsi.h>
  31. #include <scsi/scsi_device.h>
  32. #include <scsi/scsi_cmnd.h>
  33. #include <scsi/scsi_host.h>
  34. #include <scsi/scsi_tcq.h>
  35. #define DRV_NAME "stex"
  36. #define ST_DRIVER_VERSION "3.1.0.1"
  37. #define ST_VER_MAJOR 3
  38. #define ST_VER_MINOR 1
  39. #define ST_OEM 0
  40. #define ST_BUILD_VER 1
  41. enum {
  42. /* MU register offset */
  43. IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  44. IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  45. OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  46. OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  47. IDBL = 0x20, /* MU_INBOUND_DOORBELL */
  48. IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  49. IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  50. ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
  51. OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  52. OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  53. /* MU register value */
  54. MU_INBOUND_DOORBELL_HANDSHAKE = 1,
  55. MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
  56. MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
  57. MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
  58. MU_INBOUND_DOORBELL_RESET = 16,
  59. MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
  60. MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  61. MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
  62. MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
  63. MU_OUTBOUND_DOORBELL_HASEVENT = 16,
  64. /* MU status code */
  65. MU_STATE_STARTING = 1,
  66. MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
  67. MU_STATE_SEND_HANDSHAKE_FRAME = 3,
  68. MU_STATE_STARTED = 4,
  69. MU_STATE_RESETTING = 5,
  70. MU_MAX_DELAY = 120,
  71. MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
  72. MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
  73. MU_HARD_RESET_WAIT = 30000,
  74. HMU_PARTNER_TYPE = 2,
  75. /* firmware returned values */
  76. SRB_STATUS_SUCCESS = 0x01,
  77. SRB_STATUS_ERROR = 0x04,
  78. SRB_STATUS_BUSY = 0x05,
  79. SRB_STATUS_INVALID_REQUEST = 0x06,
  80. SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
  81. SRB_SEE_SENSE = 0x80,
  82. /* task attribute */
  83. TASK_ATTRIBUTE_SIMPLE = 0x0,
  84. TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
  85. TASK_ATTRIBUTE_ORDERED = 0x2,
  86. TASK_ATTRIBUTE_ACA = 0x4,
  87. /* request count, etc. */
  88. MU_MAX_REQUEST = 32,
  89. /* one message wasted, use MU_MAX_REQUEST+1
  90. to handle MU_MAX_REQUEST messages */
  91. MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
  92. MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
  93. STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
  94. REQ_VARIABLE_LEN = 1024,
  95. STATUS_VAR_LEN = 128,
  96. ST_CAN_QUEUE = MU_MAX_REQUEST,
  97. ST_CMD_PER_LUN = MU_MAX_REQUEST,
  98. ST_MAX_SG = 32,
  99. /* sg flags */
  100. SG_CF_EOT = 0x80, /* end of table */
  101. SG_CF_64B = 0x40, /* 64 bit item */
  102. SG_CF_HOST = 0x20, /* sg in host memory */
  103. ST_MAX_ARRAY_SUPPORTED = 16,
  104. ST_MAX_TARGET_NUM = (ST_MAX_ARRAY_SUPPORTED+1),
  105. ST_MAX_LUN_PER_TARGET = 16,
  106. st_shasta = 0,
  107. st_vsc = 1,
  108. st_vsc1 = 2,
  109. st_yosemite = 3,
  110. PASSTHRU_REQ_TYPE = 0x00000001,
  111. PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
  112. ST_INTERNAL_TIMEOUT = 30,
  113. ST_TO_CMD = 0,
  114. ST_FROM_CMD = 1,
  115. /* vendor specific commands of Promise */
  116. MGT_CMD = 0xd8,
  117. SINBAND_MGT_CMD = 0xd9,
  118. ARRAY_CMD = 0xe0,
  119. CONTROLLER_CMD = 0xe1,
  120. DEBUGGING_CMD = 0xe2,
  121. PASSTHRU_CMD = 0xe3,
  122. PASSTHRU_GET_ADAPTER = 0x05,
  123. PASSTHRU_GET_DRVVER = 0x10,
  124. CTLR_CONFIG_CMD = 0x03,
  125. CTLR_SHUTDOWN = 0x0d,
  126. CTLR_POWER_STATE_CHANGE = 0x0e,
  127. CTLR_POWER_SAVING = 0x01,
  128. PASSTHRU_SIGNATURE = 0x4e415041,
  129. MGT_CMD_SIGNATURE = 0xba,
  130. INQUIRY_EVPD = 0x01,
  131. ST_ADDITIONAL_MEM = 0x200000,
  132. };
  133. /* SCSI inquiry data */
  134. typedef struct st_inq {
  135. u8 DeviceType :5;
  136. u8 DeviceTypeQualifier :3;
  137. u8 DeviceTypeModifier :7;
  138. u8 RemovableMedia :1;
  139. u8 Versions;
  140. u8 ResponseDataFormat :4;
  141. u8 HiSupport :1;
  142. u8 NormACA :1;
  143. u8 ReservedBit :1;
  144. u8 AERC :1;
  145. u8 AdditionalLength;
  146. u8 Reserved[2];
  147. u8 SoftReset :1;
  148. u8 CommandQueue :1;
  149. u8 Reserved2 :1;
  150. u8 LinkedCommands :1;
  151. u8 Synchronous :1;
  152. u8 Wide16Bit :1;
  153. u8 Wide32Bit :1;
  154. u8 RelativeAddressing :1;
  155. u8 VendorId[8];
  156. u8 ProductId[16];
  157. u8 ProductRevisionLevel[4];
  158. u8 VendorSpecific[20];
  159. u8 Reserved3[40];
  160. } ST_INQ;
  161. struct st_sgitem {
  162. u8 ctrl; /* SG_CF_xxx */
  163. u8 reserved[3];
  164. __le32 count;
  165. __le32 addr;
  166. __le32 addr_hi;
  167. };
  168. struct st_sgtable {
  169. __le16 sg_count;
  170. __le16 max_sg_count;
  171. __le32 sz_in_byte;
  172. struct st_sgitem table[ST_MAX_SG];
  173. };
  174. struct handshake_frame {
  175. __le32 rb_phy; /* request payload queue physical address */
  176. __le32 rb_phy_hi;
  177. __le16 req_sz; /* size of each request payload */
  178. __le16 req_cnt; /* count of reqs the buffer can hold */
  179. __le16 status_sz; /* size of each status payload */
  180. __le16 status_cnt; /* count of status the buffer can hold */
  181. __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
  182. __le32 hosttime_hi;
  183. u8 partner_type; /* who sends this frame */
  184. u8 reserved0[7];
  185. __le32 partner_ver_major;
  186. __le32 partner_ver_minor;
  187. __le32 partner_ver_oem;
  188. __le32 partner_ver_build;
  189. __le32 extra_offset; /* NEW */
  190. __le32 extra_size; /* NEW */
  191. u32 reserved1[2];
  192. };
  193. struct req_msg {
  194. __le16 tag;
  195. u8 lun;
  196. u8 target;
  197. u8 task_attr;
  198. u8 task_manage;
  199. u8 prd_entry;
  200. u8 payload_sz; /* payload size in 4-byte, not used */
  201. u8 cdb[STEX_CDB_LENGTH];
  202. u8 variable[REQ_VARIABLE_LEN];
  203. };
  204. struct status_msg {
  205. __le16 tag;
  206. u8 lun;
  207. u8 target;
  208. u8 srb_status;
  209. u8 scsi_status;
  210. u8 reserved;
  211. u8 payload_sz; /* payload size in 4-byte */
  212. u8 variable[STATUS_VAR_LEN];
  213. };
  214. struct ver_info {
  215. u32 major;
  216. u32 minor;
  217. u32 oem;
  218. u32 build;
  219. u32 reserved[2];
  220. };
  221. struct st_frame {
  222. u32 base[6];
  223. u32 rom_addr;
  224. struct ver_info drv_ver;
  225. struct ver_info bios_ver;
  226. u32 bus;
  227. u32 slot;
  228. u32 irq_level;
  229. u32 irq_vec;
  230. u32 id;
  231. u32 subid;
  232. u32 dimm_size;
  233. u8 dimm_type;
  234. u8 reserved[3];
  235. u32 channel;
  236. u32 reserved1;
  237. };
  238. struct st_drvver {
  239. u32 major;
  240. u32 minor;
  241. u32 oem;
  242. u32 build;
  243. u32 signature[2];
  244. u8 console_id;
  245. u8 host_no;
  246. u8 reserved0[2];
  247. u32 reserved[3];
  248. };
  249. #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
  250. #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
  251. #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
  252. #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
  253. #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
  254. struct st_ccb {
  255. struct req_msg *req;
  256. struct scsi_cmnd *cmd;
  257. void *sense_buffer;
  258. unsigned int sense_bufflen;
  259. int sg_count;
  260. u32 req_type;
  261. u8 srb_status;
  262. u8 scsi_status;
  263. };
  264. struct st_hba {
  265. void __iomem *mmio_base; /* iomapped PCI memory space */
  266. void *dma_mem;
  267. dma_addr_t dma_handle;
  268. size_t dma_size;
  269. struct Scsi_Host *host;
  270. struct pci_dev *pdev;
  271. u32 req_head;
  272. u32 req_tail;
  273. u32 status_head;
  274. u32 status_tail;
  275. struct status_msg *status_buffer;
  276. void *copy_buffer; /* temp buffer for driver-handled commands */
  277. struct st_ccb ccb[MU_MAX_REQUEST];
  278. struct st_ccb *wait_ccb;
  279. wait_queue_head_t waitq;
  280. unsigned int mu_status;
  281. int out_req_cnt;
  282. unsigned int cardtype;
  283. };
  284. static const char console_inq_page[] =
  285. {
  286. 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
  287. 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
  288. 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
  289. 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
  290. 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
  291. 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
  292. 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
  293. 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  294. };
  295. MODULE_AUTHOR("Ed Lin");
  296. MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
  297. MODULE_LICENSE("GPL");
  298. MODULE_VERSION(ST_DRIVER_VERSION);
  299. static void stex_gettime(__le32 *time)
  300. {
  301. struct timeval tv;
  302. do_gettimeofday(&tv);
  303. *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
  304. *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
  305. }
  306. static struct status_msg *stex_get_status(struct st_hba *hba)
  307. {
  308. struct status_msg *status =
  309. hba->status_buffer + hba->status_tail;
  310. ++hba->status_tail;
  311. hba->status_tail %= MU_STATUS_COUNT;
  312. return status;
  313. }
  314. static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
  315. {
  316. cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
  317. cmd->sense_buffer[0] = 0x70; /* fixed format, current */
  318. cmd->sense_buffer[2] = sk;
  319. cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
  320. cmd->sense_buffer[12] = asc;
  321. cmd->sense_buffer[13] = ascq;
  322. }
  323. static void stex_invalid_field(struct scsi_cmnd *cmd,
  324. void (*done)(struct scsi_cmnd *))
  325. {
  326. /* "Invalid field in cbd" */
  327. stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
  328. done(cmd);
  329. }
  330. static struct req_msg *stex_alloc_req(struct st_hba *hba)
  331. {
  332. struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
  333. hba->req_head;
  334. ++hba->req_head;
  335. hba->req_head %= MU_REQ_COUNT;
  336. return req;
  337. }
  338. static int stex_map_sg(struct st_hba *hba,
  339. struct req_msg *req, struct st_ccb *ccb)
  340. {
  341. struct pci_dev *pdev = hba->pdev;
  342. struct scsi_cmnd *cmd;
  343. dma_addr_t dma_handle;
  344. struct scatterlist *src;
  345. struct st_sgtable *dst;
  346. int i;
  347. cmd = ccb->cmd;
  348. dst = (struct st_sgtable *)req->variable;
  349. dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
  350. dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
  351. if (cmd->use_sg) {
  352. int n_elem;
  353. src = (struct scatterlist *) cmd->request_buffer;
  354. n_elem = pci_map_sg(pdev, src,
  355. cmd->use_sg, cmd->sc_data_direction);
  356. if (n_elem <= 0)
  357. return -EIO;
  358. ccb->sg_count = n_elem;
  359. dst->sg_count = cpu_to_le16((u16)n_elem);
  360. for (i = 0; i < n_elem; i++, src++) {
  361. dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
  362. dst->table[i].addr =
  363. cpu_to_le32(sg_dma_address(src) & 0xffffffff);
  364. dst->table[i].addr_hi =
  365. cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
  366. dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
  367. }
  368. dst->table[--i].ctrl |= SG_CF_EOT;
  369. return 0;
  370. }
  371. dma_handle = pci_map_single(pdev, cmd->request_buffer,
  372. cmd->request_bufflen, cmd->sc_data_direction);
  373. cmd->SCp.dma_handle = dma_handle;
  374. ccb->sg_count = 1;
  375. dst->sg_count = cpu_to_le16(1);
  376. dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
  377. dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
  378. dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
  379. dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
  380. return 0;
  381. }
  382. static void stex_internal_copy(struct scsi_cmnd *cmd,
  383. const void *src, size_t *count, int sg_count, int direction)
  384. {
  385. size_t lcount;
  386. size_t len;
  387. void *s, *d, *base = NULL;
  388. if (*count > cmd->request_bufflen)
  389. *count = cmd->request_bufflen;
  390. lcount = *count;
  391. while (lcount) {
  392. len = lcount;
  393. s = (void *)src;
  394. if (cmd->use_sg) {
  395. size_t offset = *count - lcount;
  396. s += offset;
  397. base = scsi_kmap_atomic_sg(cmd->request_buffer,
  398. sg_count, &offset, &len);
  399. if (base == NULL) {
  400. *count -= lcount;
  401. return;
  402. }
  403. d = base + offset;
  404. } else
  405. d = cmd->request_buffer;
  406. if (direction == ST_TO_CMD)
  407. memcpy(d, s, len);
  408. else
  409. memcpy(s, d, len);
  410. lcount -= len;
  411. if (cmd->use_sg)
  412. scsi_kunmap_atomic_sg(base);
  413. }
  414. }
  415. static int stex_direct_copy(struct scsi_cmnd *cmd,
  416. const void *src, size_t count)
  417. {
  418. struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  419. size_t cp_len = count;
  420. int n_elem = 0;
  421. if (cmd->use_sg) {
  422. n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
  423. cmd->use_sg, cmd->sc_data_direction);
  424. if (n_elem <= 0)
  425. return 0;
  426. }
  427. stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
  428. if (cmd->use_sg)
  429. pci_unmap_sg(hba->pdev, cmd->request_buffer,
  430. cmd->use_sg, cmd->sc_data_direction);
  431. return cp_len == count;
  432. }
  433. static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
  434. {
  435. struct st_frame *p;
  436. size_t count = sizeof(struct st_frame);
  437. p = hba->copy_buffer;
  438. stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
  439. memset(p->base, 0, sizeof(u32)*6);
  440. *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
  441. p->rom_addr = 0;
  442. p->drv_ver.major = ST_VER_MAJOR;
  443. p->drv_ver.minor = ST_VER_MINOR;
  444. p->drv_ver.oem = ST_OEM;
  445. p->drv_ver.build = ST_BUILD_VER;
  446. p->bus = hba->pdev->bus->number;
  447. p->slot = hba->pdev->devfn;
  448. p->irq_level = 0;
  449. p->irq_vec = hba->pdev->irq;
  450. p->id = hba->pdev->vendor << 16 | hba->pdev->device;
  451. p->subid =
  452. hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
  453. stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
  454. }
  455. static void
  456. stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
  457. {
  458. req->tag = cpu_to_le16(tag);
  459. req->task_attr = TASK_ATTRIBUTE_SIMPLE;
  460. req->task_manage = 0; /* not supported yet */
  461. hba->ccb[tag].req = req;
  462. hba->out_req_cnt++;
  463. writel(hba->req_head, hba->mmio_base + IMR0);
  464. writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
  465. readl(hba->mmio_base + IDBL); /* flush */
  466. }
  467. static int
  468. stex_slave_alloc(struct scsi_device *sdev)
  469. {
  470. /* Cheat: usually extracted from Inquiry data */
  471. sdev->tagged_supported = 1;
  472. scsi_activate_tcq(sdev, sdev->host->can_queue);
  473. return 0;
  474. }
  475. static int
  476. stex_slave_config(struct scsi_device *sdev)
  477. {
  478. sdev->use_10_for_rw = 1;
  479. sdev->use_10_for_ms = 1;
  480. sdev->timeout = 60 * HZ;
  481. sdev->tagged_supported = 1;
  482. return 0;
  483. }
  484. static void
  485. stex_slave_destroy(struct scsi_device *sdev)
  486. {
  487. scsi_deactivate_tcq(sdev, 1);
  488. }
  489. static int
  490. stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
  491. {
  492. struct st_hba *hba;
  493. struct Scsi_Host *host;
  494. unsigned int id,lun;
  495. struct req_msg *req;
  496. u16 tag;
  497. host = cmd->device->host;
  498. id = cmd->device->id;
  499. lun = cmd->device->channel; /* firmware lun issue work around */
  500. hba = (struct st_hba *) &host->hostdata[0];
  501. switch (cmd->cmnd[0]) {
  502. case MODE_SENSE_10:
  503. {
  504. static char ms10_caching_page[12] =
  505. { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
  506. unsigned char page;
  507. page = cmd->cmnd[2] & 0x3f;
  508. if (page == 0x8 || page == 0x3f) {
  509. stex_direct_copy(cmd, ms10_caching_page,
  510. sizeof(ms10_caching_page));
  511. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  512. done(cmd);
  513. } else
  514. stex_invalid_field(cmd, done);
  515. return 0;
  516. }
  517. case INQUIRY:
  518. if (id != ST_MAX_ARRAY_SUPPORTED)
  519. break;
  520. if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
  521. stex_direct_copy(cmd, console_inq_page,
  522. sizeof(console_inq_page));
  523. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  524. done(cmd);
  525. } else
  526. stex_invalid_field(cmd, done);
  527. return 0;
  528. case PASSTHRU_CMD:
  529. if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
  530. struct st_drvver ver;
  531. ver.major = ST_VER_MAJOR;
  532. ver.minor = ST_VER_MINOR;
  533. ver.oem = ST_OEM;
  534. ver.build = ST_BUILD_VER;
  535. ver.signature[0] = PASSTHRU_SIGNATURE;
  536. ver.console_id = ST_MAX_ARRAY_SUPPORTED;
  537. ver.host_no = hba->host->host_no;
  538. cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
  539. DID_OK << 16 | COMMAND_COMPLETE << 8 :
  540. DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  541. done(cmd);
  542. return 0;
  543. }
  544. default:
  545. break;
  546. }
  547. cmd->scsi_done = done;
  548. tag = cmd->request->tag;
  549. if (unlikely(tag >= host->can_queue))
  550. return SCSI_MLQUEUE_HOST_BUSY;
  551. req = stex_alloc_req(hba);
  552. if (hba->cardtype == st_yosemite) {
  553. req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id;
  554. req->target = 0;
  555. } else {
  556. req->lun = lun;
  557. req->target = id;
  558. }
  559. /* cdb */
  560. memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
  561. hba->ccb[tag].cmd = cmd;
  562. hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  563. hba->ccb[tag].sense_buffer = cmd->sense_buffer;
  564. hba->ccb[tag].req_type = 0;
  565. if (cmd->sc_data_direction != DMA_NONE)
  566. stex_map_sg(hba, req, &hba->ccb[tag]);
  567. stex_send_cmd(hba, req, tag);
  568. return 0;
  569. }
  570. static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
  571. {
  572. if (cmd->sc_data_direction != DMA_NONE) {
  573. if (cmd->use_sg)
  574. pci_unmap_sg(hba->pdev, cmd->request_buffer,
  575. cmd->use_sg, cmd->sc_data_direction);
  576. else
  577. pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
  578. cmd->request_bufflen, cmd->sc_data_direction);
  579. }
  580. }
  581. static void stex_scsi_done(struct st_ccb *ccb)
  582. {
  583. struct scsi_cmnd *cmd = ccb->cmd;
  584. int result;
  585. if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
  586. result = ccb->scsi_status;
  587. switch (ccb->scsi_status) {
  588. case SAM_STAT_GOOD:
  589. result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
  590. break;
  591. case SAM_STAT_CHECK_CONDITION:
  592. result |= DRIVER_SENSE << 24;
  593. break;
  594. case SAM_STAT_BUSY:
  595. result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  596. break;
  597. default:
  598. result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  599. break;
  600. }
  601. }
  602. else if (ccb->srb_status & SRB_SEE_SENSE)
  603. result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
  604. else switch (ccb->srb_status) {
  605. case SRB_STATUS_SELECTION_TIMEOUT:
  606. result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
  607. break;
  608. case SRB_STATUS_BUSY:
  609. result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  610. break;
  611. case SRB_STATUS_INVALID_REQUEST:
  612. case SRB_STATUS_ERROR:
  613. default:
  614. result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  615. break;
  616. }
  617. cmd->result = result;
  618. cmd->scsi_done(cmd);
  619. }
  620. static void stex_copy_data(struct st_ccb *ccb,
  621. struct status_msg *resp, unsigned int variable)
  622. {
  623. size_t count = variable;
  624. if (resp->scsi_status != SAM_STAT_GOOD) {
  625. if (ccb->sense_buffer != NULL)
  626. memcpy(ccb->sense_buffer, resp->variable,
  627. min(variable, ccb->sense_bufflen));
  628. return;
  629. }
  630. if (ccb->cmd == NULL)
  631. return;
  632. stex_internal_copy(ccb->cmd,
  633. resp->variable, &count, ccb->sg_count, ST_TO_CMD);
  634. }
  635. static void stex_ys_commands(struct st_hba *hba,
  636. struct st_ccb *ccb, struct status_msg *resp)
  637. {
  638. size_t count;
  639. if (ccb->cmd->cmnd[0] == MGT_CMD &&
  640. resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
  641. ccb->cmd->request_bufflen =
  642. le32_to_cpu(*(__le32 *)&resp->variable[0]);
  643. return;
  644. }
  645. if (resp->srb_status != 0)
  646. return;
  647. /* determine inquiry command status by DeviceTypeQualifier */
  648. if (ccb->cmd->cmnd[0] == INQUIRY &&
  649. resp->scsi_status == SAM_STAT_GOOD) {
  650. ST_INQ *inq_data;
  651. count = STEX_EXTRA_SIZE;
  652. stex_internal_copy(ccb->cmd, hba->copy_buffer,
  653. &count, ccb->sg_count, ST_FROM_CMD);
  654. inq_data = (ST_INQ *)hba->copy_buffer;
  655. if (inq_data->DeviceTypeQualifier != 0)
  656. ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
  657. else
  658. ccb->srb_status = SRB_STATUS_SUCCESS;
  659. } else if (ccb->cmd->cmnd[0] == REPORT_LUNS) {
  660. u8 *report_lun_data = (u8 *)hba->copy_buffer;
  661. count = STEX_EXTRA_SIZE;
  662. stex_internal_copy(ccb->cmd, report_lun_data,
  663. &count, ccb->sg_count, ST_FROM_CMD);
  664. if (report_lun_data[2] || report_lun_data[3]) {
  665. report_lun_data[2] = 0x00;
  666. report_lun_data[3] = 0x08;
  667. stex_internal_copy(ccb->cmd, report_lun_data,
  668. &count, ccb->sg_count, ST_TO_CMD);
  669. }
  670. }
  671. }
  672. static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
  673. {
  674. void __iomem *base = hba->mmio_base;
  675. struct status_msg *resp;
  676. struct st_ccb *ccb;
  677. unsigned int size;
  678. u16 tag;
  679. if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
  680. return;
  681. /* status payloads */
  682. hba->status_head = readl(base + OMR1);
  683. if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
  684. printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
  685. pci_name(hba->pdev));
  686. return;
  687. }
  688. /*
  689. * it's not a valid status payload if:
  690. * 1. there are no pending requests(e.g. during init stage)
  691. * 2. there are some pending requests, but the controller is in
  692. * reset status, and its type is not st_yosemite
  693. * firmware of st_yosemite in reset status will return pending requests
  694. * to driver, so we allow it to pass
  695. */
  696. if (unlikely(hba->out_req_cnt <= 0 ||
  697. (hba->mu_status == MU_STATE_RESETTING &&
  698. hba->cardtype != st_yosemite))) {
  699. hba->status_tail = hba->status_head;
  700. goto update_status;
  701. }
  702. while (hba->status_tail != hba->status_head) {
  703. resp = stex_get_status(hba);
  704. tag = le16_to_cpu(resp->tag);
  705. if (unlikely(tag >= hba->host->can_queue)) {
  706. printk(KERN_WARNING DRV_NAME
  707. "(%s): invalid tag\n", pci_name(hba->pdev));
  708. continue;
  709. }
  710. ccb = &hba->ccb[tag];
  711. if (hba->wait_ccb == ccb)
  712. hba->wait_ccb = NULL;
  713. if (unlikely(ccb->req == NULL)) {
  714. printk(KERN_WARNING DRV_NAME
  715. "(%s): lagging req\n", pci_name(hba->pdev));
  716. hba->out_req_cnt--;
  717. continue;
  718. }
  719. size = resp->payload_sz * sizeof(u32); /* payload size */
  720. if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
  721. size > sizeof(*resp))) {
  722. printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
  723. pci_name(hba->pdev));
  724. } else {
  725. size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
  726. if (size)
  727. stex_copy_data(ccb, resp, size);
  728. }
  729. ccb->srb_status = resp->srb_status;
  730. ccb->scsi_status = resp->scsi_status;
  731. if (likely(ccb->cmd != NULL)) {
  732. if (hba->cardtype == st_yosemite)
  733. stex_ys_commands(hba, ccb, resp);
  734. if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
  735. ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
  736. stex_controller_info(hba, ccb);
  737. stex_unmap_sg(hba, ccb->cmd);
  738. stex_scsi_done(ccb);
  739. hba->out_req_cnt--;
  740. } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
  741. hba->out_req_cnt--;
  742. if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
  743. ccb->req_type = 0;
  744. continue;
  745. }
  746. ccb->req_type = 0;
  747. if (waitqueue_active(&hba->waitq))
  748. wake_up(&hba->waitq);
  749. }
  750. }
  751. update_status:
  752. writel(hba->status_head, base + IMR1);
  753. readl(base + IMR1); /* flush */
  754. }
  755. static irqreturn_t stex_intr(int irq, void *__hba)
  756. {
  757. struct st_hba *hba = __hba;
  758. void __iomem *base = hba->mmio_base;
  759. u32 data;
  760. unsigned long flags;
  761. int handled = 0;
  762. spin_lock_irqsave(hba->host->host_lock, flags);
  763. data = readl(base + ODBL);
  764. if (data && data != 0xffffffff) {
  765. /* clear the interrupt */
  766. writel(data, base + ODBL);
  767. readl(base + ODBL); /* flush */
  768. stex_mu_intr(hba, data);
  769. handled = 1;
  770. }
  771. spin_unlock_irqrestore(hba->host->host_lock, flags);
  772. return IRQ_RETVAL(handled);
  773. }
  774. static int stex_handshake(struct st_hba *hba)
  775. {
  776. void __iomem *base = hba->mmio_base;
  777. struct handshake_frame *h;
  778. dma_addr_t status_phys;
  779. u32 data;
  780. unsigned long before;
  781. if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  782. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  783. readl(base + IDBL);
  784. before = jiffies;
  785. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  786. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  787. printk(KERN_ERR DRV_NAME
  788. "(%s): no handshake signature\n",
  789. pci_name(hba->pdev));
  790. return -1;
  791. }
  792. rmb();
  793. msleep(1);
  794. }
  795. }
  796. udelay(10);
  797. data = readl(base + OMR1);
  798. if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
  799. data &= 0x0000ffff;
  800. if (hba->host->can_queue > data)
  801. hba->host->can_queue = data;
  802. }
  803. h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  804. h->rb_phy = cpu_to_le32(hba->dma_handle);
  805. h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
  806. h->req_sz = cpu_to_le16(sizeof(struct req_msg));
  807. h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
  808. h->status_sz = cpu_to_le16(sizeof(struct status_msg));
  809. h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
  810. stex_gettime(&h->hosttime);
  811. h->partner_type = HMU_PARTNER_TYPE;
  812. if (hba->dma_size > STEX_BUFFER_SIZE) {
  813. h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
  814. h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
  815. } else
  816. h->extra_offset = h->extra_size = 0;
  817. status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
  818. writel(status_phys, base + IMR0);
  819. readl(base + IMR0);
  820. writel((status_phys >> 16) >> 16, base + IMR1);
  821. readl(base + IMR1);
  822. writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
  823. readl(base + OMR0);
  824. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  825. readl(base + IDBL); /* flush */
  826. udelay(10);
  827. before = jiffies;
  828. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  829. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  830. printk(KERN_ERR DRV_NAME
  831. "(%s): no signature after handshake frame\n",
  832. pci_name(hba->pdev));
  833. return -1;
  834. }
  835. rmb();
  836. msleep(1);
  837. }
  838. writel(0, base + IMR0);
  839. readl(base + IMR0);
  840. writel(0, base + OMR0);
  841. readl(base + OMR0);
  842. writel(0, base + IMR1);
  843. readl(base + IMR1);
  844. writel(0, base + OMR1);
  845. readl(base + OMR1); /* flush */
  846. hba->mu_status = MU_STATE_STARTED;
  847. return 0;
  848. }
  849. static int stex_abort(struct scsi_cmnd *cmd)
  850. {
  851. struct Scsi_Host *host = cmd->device->host;
  852. struct st_hba *hba = (struct st_hba *)host->hostdata;
  853. u16 tag = cmd->request->tag;
  854. void __iomem *base;
  855. u32 data;
  856. int result = SUCCESS;
  857. unsigned long flags;
  858. base = hba->mmio_base;
  859. spin_lock_irqsave(host->host_lock, flags);
  860. if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
  861. hba->wait_ccb = &hba->ccb[tag];
  862. else {
  863. for (tag = 0; tag < host->can_queue; tag++)
  864. if (hba->ccb[tag].cmd == cmd) {
  865. hba->wait_ccb = &hba->ccb[tag];
  866. break;
  867. }
  868. if (tag >= host->can_queue)
  869. goto out;
  870. }
  871. data = readl(base + ODBL);
  872. if (data == 0 || data == 0xffffffff)
  873. goto fail_out;
  874. writel(data, base + ODBL);
  875. readl(base + ODBL); /* flush */
  876. stex_mu_intr(hba, data);
  877. if (hba->wait_ccb == NULL) {
  878. printk(KERN_WARNING DRV_NAME
  879. "(%s): lost interrupt\n", pci_name(hba->pdev));
  880. goto out;
  881. }
  882. fail_out:
  883. stex_unmap_sg(hba, cmd);
  884. hba->wait_ccb->req = NULL; /* nullify the req's future return */
  885. hba->wait_ccb = NULL;
  886. result = FAILED;
  887. out:
  888. spin_unlock_irqrestore(host->host_lock, flags);
  889. return result;
  890. }
  891. static void stex_hard_reset(struct st_hba *hba)
  892. {
  893. struct pci_bus *bus;
  894. int i;
  895. u16 pci_cmd;
  896. u8 pci_bctl;
  897. for (i = 0; i < 16; i++)
  898. pci_read_config_dword(hba->pdev, i * 4,
  899. &hba->pdev->saved_config_space[i]);
  900. /* Reset secondary bus. Our controller(MU/ATU) is the only device on
  901. secondary bus. Consult Intel 80331/3 developer's manual for detail */
  902. bus = hba->pdev->bus;
  903. pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
  904. pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
  905. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  906. msleep(1);
  907. pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
  908. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  909. for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
  910. pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
  911. if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
  912. break;
  913. msleep(1);
  914. }
  915. ssleep(5);
  916. for (i = 0; i < 16; i++)
  917. pci_write_config_dword(hba->pdev, i * 4,
  918. hba->pdev->saved_config_space[i]);
  919. }
  920. static int stex_reset(struct scsi_cmnd *cmd)
  921. {
  922. struct st_hba *hba;
  923. unsigned long flags;
  924. unsigned long before;
  925. hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  926. hba->mu_status = MU_STATE_RESETTING;
  927. if (hba->cardtype == st_shasta)
  928. stex_hard_reset(hba);
  929. if (hba->cardtype != st_yosemite) {
  930. if (stex_handshake(hba)) {
  931. printk(KERN_WARNING DRV_NAME
  932. "(%s): resetting: handshake failed\n",
  933. pci_name(hba->pdev));
  934. return FAILED;
  935. }
  936. spin_lock_irqsave(hba->host->host_lock, flags);
  937. hba->req_head = 0;
  938. hba->req_tail = 0;
  939. hba->status_head = 0;
  940. hba->status_tail = 0;
  941. hba->out_req_cnt = 0;
  942. spin_unlock_irqrestore(hba->host->host_lock, flags);
  943. return SUCCESS;
  944. }
  945. /* st_yosemite */
  946. writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
  947. readl(hba->mmio_base + IDBL); /* flush */
  948. before = jiffies;
  949. while (hba->out_req_cnt > 0) {
  950. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
  951. printk(KERN_WARNING DRV_NAME
  952. "(%s): reset timeout\n", pci_name(hba->pdev));
  953. return FAILED;
  954. }
  955. msleep(1);
  956. }
  957. hba->mu_status = MU_STATE_STARTED;
  958. return SUCCESS;
  959. }
  960. static int stex_biosparam(struct scsi_device *sdev,
  961. struct block_device *bdev, sector_t capacity, int geom[])
  962. {
  963. int heads = 255, sectors = 63;
  964. if (capacity < 0x200000) {
  965. heads = 64;
  966. sectors = 32;
  967. }
  968. sector_div(capacity, heads * sectors);
  969. geom[0] = heads;
  970. geom[1] = sectors;
  971. geom[2] = capacity;
  972. return 0;
  973. }
  974. static struct scsi_host_template driver_template = {
  975. .module = THIS_MODULE,
  976. .name = DRV_NAME,
  977. .proc_name = DRV_NAME,
  978. .bios_param = stex_biosparam,
  979. .queuecommand = stex_queuecommand,
  980. .slave_alloc = stex_slave_alloc,
  981. .slave_configure = stex_slave_config,
  982. .slave_destroy = stex_slave_destroy,
  983. .eh_abort_handler = stex_abort,
  984. .eh_host_reset_handler = stex_reset,
  985. .can_queue = ST_CAN_QUEUE,
  986. .this_id = -1,
  987. .sg_tablesize = ST_MAX_SG,
  988. .cmd_per_lun = ST_CMD_PER_LUN,
  989. };
  990. static int stex_set_dma_mask(struct pci_dev * pdev)
  991. {
  992. int ret;
  993. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
  994. && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
  995. return 0;
  996. ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  997. if (!ret)
  998. ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  999. return ret;
  1000. }
  1001. static int __devinit
  1002. stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1003. {
  1004. struct st_hba *hba;
  1005. struct Scsi_Host *host;
  1006. int err;
  1007. err = pci_enable_device(pdev);
  1008. if (err)
  1009. return err;
  1010. pci_set_master(pdev);
  1011. host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
  1012. if (!host) {
  1013. printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
  1014. pci_name(pdev));
  1015. err = -ENOMEM;
  1016. goto out_disable;
  1017. }
  1018. hba = (struct st_hba *)host->hostdata;
  1019. memset(hba, 0, sizeof(struct st_hba));
  1020. err = pci_request_regions(pdev, DRV_NAME);
  1021. if (err < 0) {
  1022. printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
  1023. pci_name(pdev));
  1024. goto out_scsi_host_put;
  1025. }
  1026. hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
  1027. pci_resource_len(pdev, 0));
  1028. if ( !hba->mmio_base) {
  1029. printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
  1030. pci_name(pdev));
  1031. err = -ENOMEM;
  1032. goto out_release_regions;
  1033. }
  1034. err = stex_set_dma_mask(pdev);
  1035. if (err) {
  1036. printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
  1037. pci_name(pdev));
  1038. goto out_iounmap;
  1039. }
  1040. hba->cardtype = (unsigned int) id->driver_data;
  1041. if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
  1042. hba->cardtype = st_vsc1;
  1043. hba->dma_size = (hba->cardtype == st_vsc1) ?
  1044. (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
  1045. hba->dma_mem = dma_alloc_coherent(&pdev->dev,
  1046. hba->dma_size, &hba->dma_handle, GFP_KERNEL);
  1047. if (!hba->dma_mem) {
  1048. err = -ENOMEM;
  1049. printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
  1050. pci_name(pdev));
  1051. goto out_iounmap;
  1052. }
  1053. hba->status_buffer =
  1054. (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  1055. hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
  1056. hba->mu_status = MU_STATE_STARTING;
  1057. /* firmware uses id/lun pair for a logical drive, but lun would be
  1058. always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
  1059. channel to map lun here */
  1060. host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
  1061. host->max_id = ST_MAX_TARGET_NUM;
  1062. host->max_lun = 1;
  1063. host->unique_id = host->host_no;
  1064. host->max_cmd_len = STEX_CDB_LENGTH;
  1065. hba->host = host;
  1066. hba->pdev = pdev;
  1067. init_waitqueue_head(&hba->waitq);
  1068. err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
  1069. if (err) {
  1070. printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
  1071. pci_name(pdev));
  1072. goto out_pci_free;
  1073. }
  1074. err = stex_handshake(hba);
  1075. if (err)
  1076. goto out_free_irq;
  1077. err = scsi_init_shared_tag_map(host, host->can_queue);
  1078. if (err) {
  1079. printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
  1080. pci_name(pdev));
  1081. goto out_free_irq;
  1082. }
  1083. pci_set_drvdata(pdev, hba);
  1084. err = scsi_add_host(host, &pdev->dev);
  1085. if (err) {
  1086. printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
  1087. pci_name(pdev));
  1088. goto out_free_irq;
  1089. }
  1090. scsi_scan_host(host);
  1091. return 0;
  1092. out_free_irq:
  1093. free_irq(pdev->irq, hba);
  1094. out_pci_free:
  1095. dma_free_coherent(&pdev->dev, hba->dma_size,
  1096. hba->dma_mem, hba->dma_handle);
  1097. out_iounmap:
  1098. iounmap(hba->mmio_base);
  1099. out_release_regions:
  1100. pci_release_regions(pdev);
  1101. out_scsi_host_put:
  1102. scsi_host_put(host);
  1103. out_disable:
  1104. pci_disable_device(pdev);
  1105. return err;
  1106. }
  1107. static void stex_hba_stop(struct st_hba *hba)
  1108. {
  1109. struct req_msg *req;
  1110. unsigned long flags;
  1111. unsigned long before;
  1112. u16 tag = 0;
  1113. spin_lock_irqsave(hba->host->host_lock, flags);
  1114. req = stex_alloc_req(hba);
  1115. memset(req->cdb, 0, STEX_CDB_LENGTH);
  1116. if (hba->cardtype == st_yosemite) {
  1117. req->cdb[0] = MGT_CMD;
  1118. req->cdb[1] = MGT_CMD_SIGNATURE;
  1119. req->cdb[2] = CTLR_CONFIG_CMD;
  1120. req->cdb[3] = CTLR_SHUTDOWN;
  1121. } else {
  1122. req->cdb[0] = CONTROLLER_CMD;
  1123. req->cdb[1] = CTLR_POWER_STATE_CHANGE;
  1124. req->cdb[2] = CTLR_POWER_SAVING;
  1125. }
  1126. hba->ccb[tag].cmd = NULL;
  1127. hba->ccb[tag].sg_count = 0;
  1128. hba->ccb[tag].sense_bufflen = 0;
  1129. hba->ccb[tag].sense_buffer = NULL;
  1130. hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
  1131. stex_send_cmd(hba, req, tag);
  1132. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1133. before = jiffies;
  1134. while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
  1135. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
  1136. return;
  1137. msleep(10);
  1138. }
  1139. }
  1140. static void stex_hba_free(struct st_hba *hba)
  1141. {
  1142. free_irq(hba->pdev->irq, hba);
  1143. iounmap(hba->mmio_base);
  1144. pci_release_regions(hba->pdev);
  1145. dma_free_coherent(&hba->pdev->dev, hba->dma_size,
  1146. hba->dma_mem, hba->dma_handle);
  1147. }
  1148. static void stex_remove(struct pci_dev *pdev)
  1149. {
  1150. struct st_hba *hba = pci_get_drvdata(pdev);
  1151. scsi_remove_host(hba->host);
  1152. pci_set_drvdata(pdev, NULL);
  1153. stex_hba_stop(hba);
  1154. stex_hba_free(hba);
  1155. scsi_host_put(hba->host);
  1156. pci_disable_device(pdev);
  1157. }
  1158. static void stex_shutdown(struct pci_dev *pdev)
  1159. {
  1160. struct st_hba *hba = pci_get_drvdata(pdev);
  1161. stex_hba_stop(hba);
  1162. }
  1163. static struct pci_device_id stex_pci_tbl[] = {
  1164. /* st_shasta */
  1165. { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1166. st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
  1167. { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1168. st_shasta }, /* SuperTrak EX12350 */
  1169. { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1170. st_shasta }, /* SuperTrak EX4350 */
  1171. { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1172. st_shasta }, /* SuperTrak EX24350 */
  1173. /* st_vsc */
  1174. { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
  1175. /* st_yosemite */
  1176. { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
  1177. st_yosemite }, /* SuperTrak EX4650 */
  1178. { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
  1179. st_yosemite }, /* SuperTrak EX4650o */
  1180. { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
  1181. st_yosemite }, /* SuperTrak EX8650EL */
  1182. { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
  1183. st_yosemite }, /* SuperTrak EX8650 */
  1184. { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
  1185. st_yosemite }, /* SuperTrak EX8654 */
  1186. { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1187. st_yosemite }, /* generic st_yosemite */
  1188. { } /* terminate list */
  1189. };
  1190. MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
  1191. static struct pci_driver stex_pci_driver = {
  1192. .name = DRV_NAME,
  1193. .id_table = stex_pci_tbl,
  1194. .probe = stex_probe,
  1195. .remove = __devexit_p(stex_remove),
  1196. .shutdown = stex_shutdown,
  1197. };
  1198. static int __init stex_init(void)
  1199. {
  1200. printk(KERN_INFO DRV_NAME
  1201. ": Promise SuperTrak EX Driver version: %s\n",
  1202. ST_DRIVER_VERSION);
  1203. return pci_register_driver(&stex_pci_driver);
  1204. }
  1205. static void __exit stex_exit(void)
  1206. {
  1207. pci_unregister_driver(&stex_pci_driver);
  1208. }
  1209. module_init(stex_init);
  1210. module_exit(stex_exit);