tifm_sd.c 26 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/tifm.h>
  12. #include <linux/mmc/protocol.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/highmem.h>
  15. #include <asm/io.h>
  16. #define DRIVER_NAME "tifm_sd"
  17. #define DRIVER_VERSION "0.7"
  18. static int no_dma = 0;
  19. static int fixed_timeout = 0;
  20. module_param(no_dma, bool, 0644);
  21. module_param(fixed_timeout, bool, 0644);
  22. /* Constants here are mostly from OMAP5912 datasheet */
  23. #define TIFM_MMCSD_RESET 0x0002
  24. #define TIFM_MMCSD_CLKMASK 0x03ff
  25. #define TIFM_MMCSD_POWER 0x0800
  26. #define TIFM_MMCSD_4BBUS 0x8000
  27. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  28. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  29. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  30. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  31. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  32. #define TIFM_MMCSD_READ 0x8000
  33. #define TIFM_MMCSD_DATAMASK 0x001d /* set bits: EOFB, BRS, CB, EOC */
  34. #define TIFM_MMCSD_ERRMASK 0x41e0 /* set bits: CERR, CCRC, CTO, DCRC, DTO */
  35. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  36. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  37. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  38. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  39. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  40. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  41. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  42. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  43. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  44. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  45. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  46. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  47. #define TIFM_MMCSD_RSP_R0 0x0000
  48. #define TIFM_MMCSD_RSP_R1 0x0100
  49. #define TIFM_MMCSD_RSP_R2 0x0200
  50. #define TIFM_MMCSD_RSP_R3 0x0300
  51. #define TIFM_MMCSD_RSP_R4 0x0400
  52. #define TIFM_MMCSD_RSP_R5 0x0500
  53. #define TIFM_MMCSD_RSP_R6 0x0600
  54. #define TIFM_MMCSD_RSP_BUSY 0x0800
  55. #define TIFM_MMCSD_CMD_BC 0x0000
  56. #define TIFM_MMCSD_CMD_BCR 0x1000
  57. #define TIFM_MMCSD_CMD_AC 0x2000
  58. #define TIFM_MMCSD_CMD_ADTC 0x3000
  59. typedef enum {
  60. IDLE = 0,
  61. CMD, /* main command ended */
  62. BRS, /* block transfer finished */
  63. SCMD, /* stop command ended */
  64. CARD, /* card left busy state */
  65. FIFO, /* FIFO operation completed (uncertain) */
  66. READY
  67. } card_state_t;
  68. enum {
  69. FIFO_RDY = 0x0001, /* hardware dependent value */
  70. EJECT = 0x0004,
  71. EJECT_DONE = 0x0008,
  72. CARD_BUSY = 0x0010,
  73. OPENDRAIN = 0x0040, /* hardware dependent value */
  74. CARD_EVENT = 0x0100, /* hardware dependent value */
  75. CARD_RO = 0x0200, /* hardware dependent value */
  76. FIFO_EVENT = 0x10000 }; /* hardware dependent value */
  77. struct tifm_sd {
  78. struct tifm_dev *dev;
  79. unsigned int flags;
  80. card_state_t state;
  81. unsigned int clk_freq;
  82. unsigned int clk_div;
  83. unsigned long timeout_jiffies;
  84. struct tasklet_struct finish_tasklet;
  85. struct timer_list timer;
  86. struct mmc_request *req;
  87. wait_queue_head_t notify;
  88. size_t written_blocks;
  89. size_t buffer_size;
  90. size_t buffer_pos;
  91. };
  92. static char* tifm_sd_data_buffer(struct mmc_data *data)
  93. {
  94. return page_address(data->sg->page) + data->sg->offset;
  95. }
  96. static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
  97. unsigned int host_status)
  98. {
  99. struct mmc_command *cmd = host->req->cmd;
  100. unsigned int t_val = 0, cnt = 0;
  101. char *buffer;
  102. if (host_status & TIFM_MMCSD_BRS) {
  103. /* in non-dma rx mode BRS fires when fifo is still not empty */
  104. if (no_dma && (cmd->data->flags & MMC_DATA_READ)) {
  105. buffer = tifm_sd_data_buffer(host->req->data);
  106. while (host->buffer_size > host->buffer_pos) {
  107. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  108. buffer[host->buffer_pos++] = t_val & 0xff;
  109. buffer[host->buffer_pos++] =
  110. (t_val >> 8) & 0xff;
  111. }
  112. }
  113. return 1;
  114. } else if (no_dma) {
  115. buffer = tifm_sd_data_buffer(host->req->data);
  116. if ((cmd->data->flags & MMC_DATA_READ) &&
  117. (host_status & TIFM_MMCSD_AF)) {
  118. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  119. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  120. if (host->buffer_size > host->buffer_pos) {
  121. buffer[host->buffer_pos++] =
  122. t_val & 0xff;
  123. buffer[host->buffer_pos++] =
  124. (t_val >> 8) & 0xff;
  125. }
  126. }
  127. } else if ((cmd->data->flags & MMC_DATA_WRITE)
  128. && (host_status & TIFM_MMCSD_AE)) {
  129. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  130. if (host->buffer_size > host->buffer_pos) {
  131. t_val = buffer[host->buffer_pos++]
  132. & 0x00ff;
  133. t_val |= ((buffer[host->buffer_pos++])
  134. << 8) & 0xff00;
  135. writel(t_val,
  136. sock->addr + SOCK_MMCSD_DATA);
  137. }
  138. }
  139. }
  140. }
  141. return 0;
  142. }
  143. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  144. {
  145. unsigned int rc = 0;
  146. switch (mmc_resp_type(cmd)) {
  147. case MMC_RSP_NONE:
  148. rc |= TIFM_MMCSD_RSP_R0;
  149. break;
  150. case MMC_RSP_R1B:
  151. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  152. case MMC_RSP_R1:
  153. rc |= TIFM_MMCSD_RSP_R1;
  154. break;
  155. case MMC_RSP_R2:
  156. rc |= TIFM_MMCSD_RSP_R2;
  157. break;
  158. case MMC_RSP_R3:
  159. rc |= TIFM_MMCSD_RSP_R3;
  160. break;
  161. default:
  162. BUG();
  163. }
  164. switch (mmc_cmd_type(cmd)) {
  165. case MMC_CMD_BC:
  166. rc |= TIFM_MMCSD_CMD_BC;
  167. break;
  168. case MMC_CMD_BCR:
  169. rc |= TIFM_MMCSD_CMD_BCR;
  170. break;
  171. case MMC_CMD_AC:
  172. rc |= TIFM_MMCSD_CMD_AC;
  173. break;
  174. case MMC_CMD_ADTC:
  175. rc |= TIFM_MMCSD_CMD_ADTC;
  176. break;
  177. default:
  178. BUG();
  179. }
  180. return rc;
  181. }
  182. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  183. {
  184. struct tifm_dev *sock = host->dev;
  185. unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
  186. (host->flags & OPENDRAIN);
  187. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  188. cmd_mask |= TIFM_MMCSD_READ;
  189. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  190. cmd->opcode, cmd->arg, cmd_mask);
  191. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  192. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  193. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  194. }
  195. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  196. {
  197. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  198. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  199. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  200. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  201. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  202. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  203. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  204. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  205. }
  206. static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
  207. unsigned int host_status)
  208. {
  209. struct mmc_command *cmd = host->req->cmd;
  210. change_state:
  211. switch (host->state) {
  212. case IDLE:
  213. return;
  214. case CMD:
  215. if (host_status & TIFM_MMCSD_EOC) {
  216. tifm_sd_fetch_resp(cmd, sock);
  217. if (cmd->data) {
  218. host->state = BRS;
  219. } else {
  220. host->state = READY;
  221. }
  222. goto change_state;
  223. }
  224. break;
  225. case BRS:
  226. if (tifm_sd_transfer_data(sock, host, host_status)) {
  227. if (cmd->data->flags & MMC_DATA_WRITE) {
  228. host->state = CARD;
  229. } else {
  230. if (no_dma) {
  231. if (host->req->stop) {
  232. tifm_sd_exec(host, host->req->stop);
  233. host->state = SCMD;
  234. } else {
  235. host->state = READY;
  236. }
  237. } else {
  238. host->state = FIFO;
  239. }
  240. }
  241. goto change_state;
  242. }
  243. break;
  244. case SCMD:
  245. if (host_status & TIFM_MMCSD_EOC) {
  246. tifm_sd_fetch_resp(host->req->stop, sock);
  247. host->state = READY;
  248. goto change_state;
  249. }
  250. break;
  251. case CARD:
  252. dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
  253. host->written_blocks);
  254. if (!(host->flags & CARD_BUSY)
  255. && (host->written_blocks == cmd->data->blocks)) {
  256. if (no_dma) {
  257. if (host->req->stop) {
  258. tifm_sd_exec(host, host->req->stop);
  259. host->state = SCMD;
  260. } else {
  261. host->state = READY;
  262. }
  263. } else {
  264. host->state = FIFO;
  265. }
  266. goto change_state;
  267. }
  268. break;
  269. case FIFO:
  270. if (host->flags & FIFO_RDY) {
  271. host->flags &= ~FIFO_RDY;
  272. if (host->req->stop) {
  273. tifm_sd_exec(host, host->req->stop);
  274. host->state = SCMD;
  275. } else {
  276. host->state = READY;
  277. }
  278. goto change_state;
  279. }
  280. break;
  281. case READY:
  282. tasklet_schedule(&host->finish_tasklet);
  283. return;
  284. }
  285. }
  286. /* Called from interrupt handler */
  287. static void tifm_sd_signal_irq(struct tifm_dev *sock,
  288. unsigned int sock_irq_status)
  289. {
  290. struct tifm_sd *host;
  291. unsigned int host_status = 0, fifo_status = 0;
  292. int error_code = 0;
  293. spin_lock(&sock->lock);
  294. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  295. if (sock_irq_status & FIFO_EVENT) {
  296. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  297. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  298. host->flags |= fifo_status & FIFO_RDY;
  299. }
  300. if (sock_irq_status & CARD_EVENT) {
  301. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  302. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  303. if (!host->req)
  304. goto done;
  305. if (host_status & TIFM_MMCSD_ERRMASK) {
  306. if (host_status & TIFM_MMCSD_CERR)
  307. error_code = MMC_ERR_FAILED;
  308. else if (host_status
  309. & (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
  310. error_code = MMC_ERR_TIMEOUT;
  311. else if (host_status
  312. & (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
  313. error_code = MMC_ERR_BADCRC;
  314. writel(TIFM_FIFO_INT_SETALL,
  315. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  316. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  317. if (host->req->stop) {
  318. if (host->state == SCMD) {
  319. host->req->stop->error = error_code;
  320. } else if (host->state == BRS
  321. || host->state == CARD
  322. || host->state == FIFO) {
  323. host->req->cmd->error = error_code;
  324. tifm_sd_exec(host, host->req->stop);
  325. host->state = SCMD;
  326. goto done;
  327. } else {
  328. host->req->cmd->error = error_code;
  329. }
  330. } else {
  331. host->req->cmd->error = error_code;
  332. }
  333. host->state = READY;
  334. }
  335. if (host_status & TIFM_MMCSD_CB)
  336. host->flags |= CARD_BUSY;
  337. if ((host_status & TIFM_MMCSD_EOFB)
  338. && (host->flags & CARD_BUSY)) {
  339. host->written_blocks++;
  340. host->flags &= ~CARD_BUSY;
  341. }
  342. }
  343. if (host->req)
  344. tifm_sd_process_cmd(sock, host, host_status);
  345. done:
  346. dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
  347. host_status, fifo_status);
  348. spin_unlock(&sock->lock);
  349. }
  350. static void tifm_sd_prepare_data(struct tifm_sd *host, struct mmc_command *cmd)
  351. {
  352. struct tifm_dev *sock = host->dev;
  353. unsigned int dest_cnt;
  354. /* DMA style IO */
  355. dev_dbg(&sock->dev, "setting dma for %d blocks\n",
  356. cmd->data->blocks);
  357. writel(TIFM_FIFO_INT_SETALL,
  358. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  359. writel(ilog2(cmd->data->blksz) - 2,
  360. sock->addr + SOCK_FIFO_PAGE_SIZE);
  361. writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
  362. writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  363. dest_cnt = (cmd->data->blocks) << 8;
  364. writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
  365. writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  366. writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  367. if (cmd->data->flags & MMC_DATA_WRITE) {
  368. writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  369. writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
  370. sock->addr + SOCK_DMA_CONTROL);
  371. } else {
  372. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  373. writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
  374. }
  375. }
  376. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  377. struct mmc_data *data)
  378. {
  379. struct tifm_dev *sock = host->dev;
  380. unsigned int data_timeout = data->timeout_clks;
  381. if (fixed_timeout)
  382. return;
  383. data_timeout += data->timeout_ns /
  384. ((1000000000UL / host->clk_freq) * host->clk_div);
  385. if (data_timeout < 0xffff) {
  386. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  387. writel((~TIFM_MMCSD_DPE)
  388. & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  389. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  390. } else {
  391. data_timeout = (data_timeout >> 10) + 1;
  392. if (data_timeout > 0xffff)
  393. data_timeout = 0; /* set to unlimited */
  394. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  395. writel(TIFM_MMCSD_DPE
  396. | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  397. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  398. }
  399. }
  400. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  401. {
  402. struct tifm_sd *host = mmc_priv(mmc);
  403. struct tifm_dev *sock = host->dev;
  404. unsigned long flags;
  405. int sg_count = 0;
  406. struct mmc_data *r_data = mrq->cmd->data;
  407. spin_lock_irqsave(&sock->lock, flags);
  408. if (host->flags & EJECT) {
  409. spin_unlock_irqrestore(&sock->lock, flags);
  410. goto err_out;
  411. }
  412. if (host->req) {
  413. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  414. spin_unlock_irqrestore(&sock->lock, flags);
  415. goto err_out;
  416. }
  417. if (r_data) {
  418. tifm_sd_set_data_timeout(host, r_data);
  419. sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
  420. mrq->cmd->flags & MMC_DATA_WRITE
  421. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  422. if (sg_count != 1) {
  423. printk(KERN_ERR DRIVER_NAME
  424. ": scatterlist map failed\n");
  425. spin_unlock_irqrestore(&sock->lock, flags);
  426. goto err_out;
  427. }
  428. host->written_blocks = 0;
  429. host->flags &= ~CARD_BUSY;
  430. tifm_sd_prepare_data(host, mrq->cmd);
  431. }
  432. host->req = mrq;
  433. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  434. host->state = CMD;
  435. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  436. sock->addr + SOCK_CONTROL);
  437. tifm_sd_exec(host, mrq->cmd);
  438. spin_unlock_irqrestore(&sock->lock, flags);
  439. return;
  440. err_out:
  441. if (sg_count > 0)
  442. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  443. (r_data->flags & MMC_DATA_WRITE)
  444. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  445. mrq->cmd->error = MMC_ERR_TIMEOUT;
  446. mmc_request_done(mmc, mrq);
  447. }
  448. static void tifm_sd_end_cmd(unsigned long data)
  449. {
  450. struct tifm_sd *host = (struct tifm_sd*)data;
  451. struct tifm_dev *sock = host->dev;
  452. struct mmc_host *mmc = tifm_get_drvdata(sock);
  453. struct mmc_request *mrq;
  454. struct mmc_data *r_data = NULL;
  455. unsigned long flags;
  456. spin_lock_irqsave(&sock->lock, flags);
  457. del_timer(&host->timer);
  458. mrq = host->req;
  459. host->req = NULL;
  460. host->state = IDLE;
  461. if (!mrq) {
  462. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  463. spin_unlock_irqrestore(&sock->lock, flags);
  464. return;
  465. }
  466. r_data = mrq->cmd->data;
  467. if (r_data) {
  468. if (r_data->flags & MMC_DATA_WRITE) {
  469. r_data->bytes_xfered = host->written_blocks
  470. * r_data->blksz;
  471. } else {
  472. r_data->bytes_xfered = r_data->blocks -
  473. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  474. r_data->bytes_xfered *= r_data->blksz;
  475. r_data->bytes_xfered += r_data->blksz -
  476. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  477. }
  478. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  479. (r_data->flags & MMC_DATA_WRITE)
  480. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  481. }
  482. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  483. sock->addr + SOCK_CONTROL);
  484. spin_unlock_irqrestore(&sock->lock, flags);
  485. mmc_request_done(mmc, mrq);
  486. }
  487. static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
  488. {
  489. struct tifm_sd *host = mmc_priv(mmc);
  490. struct tifm_dev *sock = host->dev;
  491. unsigned long flags;
  492. struct mmc_data *r_data = mrq->cmd->data;
  493. spin_lock_irqsave(&sock->lock, flags);
  494. if (host->flags & EJECT) {
  495. spin_unlock_irqrestore(&sock->lock, flags);
  496. goto err_out;
  497. }
  498. if (host->req) {
  499. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  500. spin_unlock_irqrestore(&sock->lock, flags);
  501. goto err_out;
  502. }
  503. if (r_data) {
  504. tifm_sd_set_data_timeout(host, r_data);
  505. host->buffer_size = mrq->cmd->data->blocks
  506. * mrq->cmd->data->blksz;
  507. writel(TIFM_MMCSD_BUFINT
  508. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  509. sock->addr + SOCK_MMCSD_INT_ENABLE);
  510. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
  511. | (TIFM_MMCSD_FIFO_SIZE - 1),
  512. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  513. host->written_blocks = 0;
  514. host->flags &= ~CARD_BUSY;
  515. host->buffer_pos = 0;
  516. writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  517. writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  518. }
  519. host->req = mrq;
  520. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  521. host->state = CMD;
  522. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  523. sock->addr + SOCK_CONTROL);
  524. tifm_sd_exec(host, mrq->cmd);
  525. spin_unlock_irqrestore(&sock->lock, flags);
  526. return;
  527. err_out:
  528. mrq->cmd->error = MMC_ERR_TIMEOUT;
  529. mmc_request_done(mmc, mrq);
  530. }
  531. static void tifm_sd_end_cmd_nodma(unsigned long data)
  532. {
  533. struct tifm_sd *host = (struct tifm_sd*)data;
  534. struct tifm_dev *sock = host->dev;
  535. struct mmc_host *mmc = tifm_get_drvdata(sock);
  536. struct mmc_request *mrq;
  537. struct mmc_data *r_data = NULL;
  538. unsigned long flags;
  539. spin_lock_irqsave(&sock->lock, flags);
  540. del_timer(&host->timer);
  541. mrq = host->req;
  542. host->req = NULL;
  543. host->state = IDLE;
  544. if (!mrq) {
  545. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  546. spin_unlock_irqrestore(&sock->lock, flags);
  547. return;
  548. }
  549. r_data = mrq->cmd->data;
  550. if (r_data) {
  551. writel((~TIFM_MMCSD_BUFINT) &
  552. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  553. sock->addr + SOCK_MMCSD_INT_ENABLE);
  554. if (r_data->flags & MMC_DATA_WRITE) {
  555. r_data->bytes_xfered = host->written_blocks
  556. * r_data->blksz;
  557. } else {
  558. r_data->bytes_xfered = r_data->blocks -
  559. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  560. r_data->bytes_xfered *= r_data->blksz;
  561. r_data->bytes_xfered += r_data->blksz -
  562. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  563. }
  564. host->buffer_pos = 0;
  565. host->buffer_size = 0;
  566. }
  567. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  568. sock->addr + SOCK_CONTROL);
  569. spin_unlock_irqrestore(&sock->lock, flags);
  570. mmc_request_done(mmc, mrq);
  571. }
  572. static void tifm_sd_terminate(struct tifm_sd *host)
  573. {
  574. struct tifm_dev *sock = host->dev;
  575. unsigned long flags;
  576. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  577. mmiowb();
  578. spin_lock_irqsave(&sock->lock, flags);
  579. host->flags |= EJECT;
  580. if (host->req) {
  581. writel(TIFM_FIFO_INT_SETALL,
  582. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  583. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  584. tasklet_schedule(&host->finish_tasklet);
  585. }
  586. spin_unlock_irqrestore(&sock->lock, flags);
  587. }
  588. static void tifm_sd_abort(unsigned long data)
  589. {
  590. struct tifm_sd *host = (struct tifm_sd*)data;
  591. printk(KERN_ERR DRIVER_NAME
  592. ": card failed to respond for a long period of time");
  593. tifm_sd_terminate(host);
  594. tifm_eject(host->dev);
  595. }
  596. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  597. {
  598. struct tifm_sd *host = mmc_priv(mmc);
  599. struct tifm_dev *sock = host->dev;
  600. unsigned int clk_div1, clk_div2;
  601. unsigned long flags;
  602. spin_lock_irqsave(&sock->lock, flags);
  603. dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
  604. ios->power_mode);
  605. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  606. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  607. sock->addr + SOCK_MMCSD_CONFIG);
  608. } else {
  609. writel((~TIFM_MMCSD_4BBUS)
  610. & readl(sock->addr + SOCK_MMCSD_CONFIG),
  611. sock->addr + SOCK_MMCSD_CONFIG);
  612. }
  613. if (ios->clock) {
  614. clk_div1 = 20000000 / ios->clock;
  615. if (!clk_div1)
  616. clk_div1 = 1;
  617. clk_div2 = 24000000 / ios->clock;
  618. if (!clk_div2)
  619. clk_div2 = 1;
  620. if ((20000000 / clk_div1) > ios->clock)
  621. clk_div1++;
  622. if ((24000000 / clk_div2) > ios->clock)
  623. clk_div2++;
  624. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  625. host->clk_freq = 20000000;
  626. host->clk_div = clk_div1;
  627. writel((~TIFM_CTRL_FAST_CLK)
  628. & readl(sock->addr + SOCK_CONTROL),
  629. sock->addr + SOCK_CONTROL);
  630. } else {
  631. host->clk_freq = 24000000;
  632. host->clk_div = clk_div2;
  633. writel(TIFM_CTRL_FAST_CLK
  634. | readl(sock->addr + SOCK_CONTROL),
  635. sock->addr + SOCK_CONTROL);
  636. }
  637. } else {
  638. host->clk_div = 0;
  639. }
  640. host->clk_div &= TIFM_MMCSD_CLKMASK;
  641. writel(host->clk_div
  642. | ((~TIFM_MMCSD_CLKMASK)
  643. & readl(sock->addr + SOCK_MMCSD_CONFIG)),
  644. sock->addr + SOCK_MMCSD_CONFIG);
  645. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  646. host->flags |= OPENDRAIN;
  647. else
  648. host->flags &= ~OPENDRAIN;
  649. /* chip_select : maybe later */
  650. //vdd
  651. //power is set before probe / after remove
  652. //I believe, power_off when already marked for eject is sufficient to
  653. // allow removal.
  654. if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
  655. host->flags |= EJECT_DONE;
  656. wake_up_all(&host->notify);
  657. }
  658. spin_unlock_irqrestore(&sock->lock, flags);
  659. }
  660. static int tifm_sd_ro(struct mmc_host *mmc)
  661. {
  662. int rc;
  663. struct tifm_sd *host = mmc_priv(mmc);
  664. struct tifm_dev *sock = host->dev;
  665. unsigned long flags;
  666. spin_lock_irqsave(&sock->lock, flags);
  667. host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
  668. rc = (host->flags & CARD_RO) ? 1 : 0;
  669. spin_unlock_irqrestore(&sock->lock, flags);
  670. return rc;
  671. }
  672. static struct mmc_host_ops tifm_sd_ops = {
  673. .request = tifm_sd_request,
  674. .set_ios = tifm_sd_ios,
  675. .get_ro = tifm_sd_ro
  676. };
  677. static int tifm_sd_initialize_host(struct tifm_sd *host)
  678. {
  679. int rc;
  680. unsigned int host_status = 0;
  681. struct tifm_dev *sock = host->dev;
  682. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  683. mmiowb();
  684. host->clk_div = 61;
  685. host->clk_freq = 20000000;
  686. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  687. writel(host->clk_div | TIFM_MMCSD_POWER,
  688. sock->addr + SOCK_MMCSD_CONFIG);
  689. /* wait up to 0.51 sec for reset */
  690. for (rc = 2; rc <= 256; rc <<= 1) {
  691. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  692. rc = 0;
  693. break;
  694. }
  695. msleep(rc);
  696. }
  697. if (rc) {
  698. printk(KERN_ERR DRIVER_NAME
  699. ": controller failed to reset\n");
  700. return -ENODEV;
  701. }
  702. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  703. writel(host->clk_div | TIFM_MMCSD_POWER,
  704. sock->addr + SOCK_MMCSD_CONFIG);
  705. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  706. // command timeout fixed to 64 clocks for now
  707. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
  708. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  709. /* INAB should take much less than reset */
  710. for (rc = 1; rc <= 16; rc <<= 1) {
  711. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  712. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  713. if (!(host_status & TIFM_MMCSD_ERRMASK)
  714. && (host_status & TIFM_MMCSD_EOC)) {
  715. rc = 0;
  716. break;
  717. }
  718. msleep(rc);
  719. }
  720. if (rc) {
  721. printk(KERN_ERR DRIVER_NAME
  722. ": card not ready - probe failed on initialization\n");
  723. return -ENODEV;
  724. }
  725. writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
  726. sock->addr + SOCK_MMCSD_INT_ENABLE);
  727. mmiowb();
  728. return 0;
  729. }
  730. static int tifm_sd_probe(struct tifm_dev *sock)
  731. {
  732. struct mmc_host *mmc;
  733. struct tifm_sd *host;
  734. int rc = -EIO;
  735. if (!(TIFM_SOCK_STATE_OCCUPIED
  736. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  737. printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
  738. return rc;
  739. }
  740. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  741. if (!mmc)
  742. return -ENOMEM;
  743. host = mmc_priv(mmc);
  744. tifm_set_drvdata(sock, mmc);
  745. host->dev = sock;
  746. host->timeout_jiffies = msecs_to_jiffies(1000);
  747. init_waitqueue_head(&host->notify);
  748. tasklet_init(&host->finish_tasklet,
  749. no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd,
  750. (unsigned long)host);
  751. setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
  752. tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
  753. mmc->ops = &tifm_sd_ops;
  754. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  755. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
  756. mmc->f_min = 20000000 / 60;
  757. mmc->f_max = 24000000;
  758. mmc->max_hw_segs = 1;
  759. mmc->max_phys_segs = 1;
  760. // limited by DMA counter - it's safer to stick with
  761. // block counter has 11 bits though
  762. mmc->max_blk_count = 256;
  763. // 2k maximum hw block length
  764. mmc->max_blk_size = 2048;
  765. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  766. mmc->max_seg_size = mmc->max_req_size;
  767. sock->signal_irq = tifm_sd_signal_irq;
  768. rc = tifm_sd_initialize_host(host);
  769. if (!rc)
  770. rc = mmc_add_host(mmc);
  771. if (rc)
  772. goto out_free_mmc;
  773. return 0;
  774. out_free_mmc:
  775. mmc_free_host(mmc);
  776. return rc;
  777. }
  778. static void tifm_sd_remove(struct tifm_dev *sock)
  779. {
  780. struct mmc_host *mmc = tifm_get_drvdata(sock);
  781. struct tifm_sd *host = mmc_priv(mmc);
  782. del_timer_sync(&host->timer);
  783. tifm_sd_terminate(host);
  784. wait_event_timeout(host->notify, host->flags & EJECT_DONE,
  785. host->timeout_jiffies);
  786. tasklet_kill(&host->finish_tasklet);
  787. mmc_remove_host(mmc);
  788. /* The meaning of the bit majority in this constant is unknown. */
  789. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  790. sock->addr + SOCK_CONTROL);
  791. tifm_set_drvdata(sock, NULL);
  792. mmc_free_host(mmc);
  793. }
  794. #ifdef CONFIG_PM
  795. static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
  796. {
  797. struct mmc_host *mmc = tifm_get_drvdata(sock);
  798. int rc;
  799. rc = mmc_suspend_host(mmc, state);
  800. /* The meaning of the bit majority in this constant is unknown. */
  801. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  802. sock->addr + SOCK_CONTROL);
  803. return rc;
  804. }
  805. static int tifm_sd_resume(struct tifm_dev *sock)
  806. {
  807. struct mmc_host *mmc = tifm_get_drvdata(sock);
  808. struct tifm_sd *host = mmc_priv(mmc);
  809. if (sock->media_id != FM_SD
  810. || tifm_sd_initialize_host(host)) {
  811. tifm_eject(sock);
  812. return 0;
  813. } else {
  814. return mmc_resume_host(mmc);
  815. }
  816. }
  817. #else
  818. #define tifm_sd_suspend NULL
  819. #define tifm_sd_resume NULL
  820. #endif /* CONFIG_PM */
  821. static tifm_media_id tifm_sd_id_tbl[] = {
  822. FM_SD, 0
  823. };
  824. static struct tifm_driver tifm_sd_driver = {
  825. .driver = {
  826. .name = DRIVER_NAME,
  827. .owner = THIS_MODULE
  828. },
  829. .id_table = tifm_sd_id_tbl,
  830. .probe = tifm_sd_probe,
  831. .remove = tifm_sd_remove,
  832. .suspend = tifm_sd_suspend,
  833. .resume = tifm_sd_resume
  834. };
  835. static int __init tifm_sd_init(void)
  836. {
  837. return tifm_register_driver(&tifm_sd_driver);
  838. }
  839. static void __exit tifm_sd_exit(void)
  840. {
  841. tifm_unregister_driver(&tifm_sd_driver);
  842. }
  843. MODULE_AUTHOR("Alex Dubov");
  844. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  845. MODULE_LICENSE("GPL");
  846. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  847. MODULE_VERSION(DRIVER_VERSION);
  848. module_init(tifm_sd_init);
  849. module_exit(tifm_sd_exit);