i810_dma.c 36 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/pagemap.h>
  39. #define I810_BUF_FREE 2
  40. #define I810_BUF_CLIENT 1
  41. #define I810_BUF_HARDWARE 0
  42. #define I810_BUF_UNMAPPED 0
  43. #define I810_BUF_MAPPED 1
  44. static drm_buf_t *i810_freelist_get(drm_device_t * dev)
  45. {
  46. drm_device_dma_t *dma = dev->dma;
  47. int i;
  48. int used;
  49. /* Linear search might not be the best solution */
  50. for (i = 0; i < dma->buf_count; i++) {
  51. drm_buf_t *buf = dma->buflist[i];
  52. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  53. /* In use is already a pointer */
  54. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  55. I810_BUF_CLIENT);
  56. if (used == I810_BUF_FREE) {
  57. return buf;
  58. }
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(drm_device_t * dev, drm_buf_t * buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. drm_file_t *priv = filp->private_data;
  80. drm_device_t *dev;
  81. drm_i810_private_t *dev_priv;
  82. drm_buf_t *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. lock_kernel();
  85. dev = priv->head->dev;
  86. dev_priv = dev->dev_private;
  87. buf = dev_priv->mmap_buffer;
  88. buf_priv = buf->dev_private;
  89. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  90. vma->vm_file = filp;
  91. buf_priv->currently_mapped = I810_BUF_MAPPED;
  92. unlock_kernel();
  93. if (io_remap_pfn_range(vma, vma->vm_start,
  94. vma->vm_pgoff,
  95. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  96. return -EAGAIN;
  97. return 0;
  98. }
  99. static struct file_operations i810_buffer_fops = {
  100. .open = drm_open,
  101. .release = drm_release,
  102. .ioctl = drm_ioctl,
  103. .mmap = i810_mmap_buffers,
  104. .fasync = drm_fasync,
  105. };
  106. static int i810_map_buffer(drm_buf_t * buf, struct file *filp)
  107. {
  108. drm_file_t *priv = filp->private_data;
  109. drm_device_t *dev = priv->head->dev;
  110. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  111. drm_i810_private_t *dev_priv = dev->dev_private;
  112. const struct file_operations *old_fops;
  113. int retcode = 0;
  114. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  115. return -EINVAL;
  116. down_write(&current->mm->mmap_sem);
  117. old_fops = filp->f_op;
  118. filp->f_op = &i810_buffer_fops;
  119. dev_priv->mmap_buffer = buf;
  120. buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total,
  121. PROT_READ | PROT_WRITE,
  122. MAP_SHARED, buf->bus_address);
  123. dev_priv->mmap_buffer = NULL;
  124. filp->f_op = old_fops;
  125. if (IS_ERR(buf_priv->virtual)) {
  126. /* Real error */
  127. DRM_ERROR("mmap error\n");
  128. retcode = PTR_ERR(buf_priv->virtual);
  129. buf_priv->virtual = NULL;
  130. }
  131. up_write(&current->mm->mmap_sem);
  132. return retcode;
  133. }
  134. static int i810_unmap_buffer(drm_buf_t * buf)
  135. {
  136. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  137. int retcode = 0;
  138. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  139. return -EINVAL;
  140. down_write(&current->mm->mmap_sem);
  141. retcode = do_munmap(current->mm,
  142. (unsigned long)buf_priv->virtual,
  143. (size_t) buf->total);
  144. up_write(&current->mm->mmap_sem);
  145. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  146. buf_priv->virtual = NULL;
  147. return retcode;
  148. }
  149. static int i810_dma_get_buffer(drm_device_t * dev, drm_i810_dma_t * d,
  150. struct file *filp)
  151. {
  152. drm_buf_t *buf;
  153. drm_i810_buf_priv_t *buf_priv;
  154. int retcode = 0;
  155. buf = i810_freelist_get(dev);
  156. if (!buf) {
  157. retcode = -ENOMEM;
  158. DRM_DEBUG("retcode=%d\n", retcode);
  159. return retcode;
  160. }
  161. retcode = i810_map_buffer(buf, filp);
  162. if (retcode) {
  163. i810_freelist_put(dev, buf);
  164. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  165. return retcode;
  166. }
  167. buf->filp = filp;
  168. buf_priv = buf->dev_private;
  169. d->granted = 1;
  170. d->request_idx = buf->idx;
  171. d->request_size = buf->total;
  172. d->virtual = buf_priv->virtual;
  173. return retcode;
  174. }
  175. static int i810_dma_cleanup(drm_device_t * dev)
  176. {
  177. drm_device_dma_t *dma = dev->dma;
  178. /* Make sure interrupts are disabled here because the uninstall ioctl
  179. * may not have been called from userspace and after dev_private
  180. * is freed, it's too late.
  181. */
  182. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  183. drm_irq_uninstall(dev);
  184. if (dev->dev_private) {
  185. int i;
  186. drm_i810_private_t *dev_priv =
  187. (drm_i810_private_t *) dev->dev_private;
  188. if (dev_priv->ring.virtual_start) {
  189. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  190. }
  191. if (dev_priv->hw_status_page) {
  192. pci_free_consistent(dev->pdev, PAGE_SIZE,
  193. dev_priv->hw_status_page,
  194. dev_priv->dma_status_page);
  195. /* Need to rewrite hardware status page */
  196. I810_WRITE(0x02080, 0x1ffff000);
  197. }
  198. drm_free(dev->dev_private, sizeof(drm_i810_private_t),
  199. DRM_MEM_DRIVER);
  200. dev->dev_private = NULL;
  201. for (i = 0; i < dma->buf_count; i++) {
  202. drm_buf_t *buf = dma->buflist[i];
  203. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  204. if (buf_priv->kernel_virtual && buf->total)
  205. drm_core_ioremapfree(&buf_priv->map, dev);
  206. }
  207. }
  208. return 0;
  209. }
  210. static int i810_wait_ring(drm_device_t * dev, int n)
  211. {
  212. drm_i810_private_t *dev_priv = dev->dev_private;
  213. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  214. int iters = 0;
  215. unsigned long end;
  216. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  217. end = jiffies + (HZ * 3);
  218. while (ring->space < n) {
  219. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  220. ring->space = ring->head - (ring->tail + 8);
  221. if (ring->space < 0)
  222. ring->space += ring->Size;
  223. if (ring->head != last_head) {
  224. end = jiffies + (HZ * 3);
  225. last_head = ring->head;
  226. }
  227. iters++;
  228. if (time_before(end, jiffies)) {
  229. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  230. DRM_ERROR("lockup\n");
  231. goto out_wait_ring;
  232. }
  233. udelay(1);
  234. }
  235. out_wait_ring:
  236. return iters;
  237. }
  238. static void i810_kernel_lost_context(drm_device_t * dev)
  239. {
  240. drm_i810_private_t *dev_priv = dev->dev_private;
  241. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  242. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  243. ring->tail = I810_READ(LP_RING + RING_TAIL);
  244. ring->space = ring->head - (ring->tail + 8);
  245. if (ring->space < 0)
  246. ring->space += ring->Size;
  247. }
  248. static int i810_freelist_init(drm_device_t * dev, drm_i810_private_t * dev_priv)
  249. {
  250. drm_device_dma_t *dma = dev->dma;
  251. int my_idx = 24;
  252. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  253. int i;
  254. if (dma->buf_count > 1019) {
  255. /* Not enough space in the status page for the freelist */
  256. return -EINVAL;
  257. }
  258. for (i = 0; i < dma->buf_count; i++) {
  259. drm_buf_t *buf = dma->buflist[i];
  260. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  261. buf_priv->in_use = hw_status++;
  262. buf_priv->my_use_idx = my_idx;
  263. my_idx += 4;
  264. *buf_priv->in_use = I810_BUF_FREE;
  265. buf_priv->map.offset = buf->bus_address;
  266. buf_priv->map.size = buf->total;
  267. buf_priv->map.type = _DRM_AGP;
  268. buf_priv->map.flags = 0;
  269. buf_priv->map.mtrr = 0;
  270. drm_core_ioremap(&buf_priv->map, dev);
  271. buf_priv->kernel_virtual = buf_priv->map.handle;
  272. }
  273. return 0;
  274. }
  275. static int i810_dma_initialize(drm_device_t * dev,
  276. drm_i810_private_t * dev_priv,
  277. drm_i810_init_t * init)
  278. {
  279. struct list_head *list;
  280. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  281. list_for_each(list, &dev->maplist->head) {
  282. drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
  283. if (r_list->map &&
  284. r_list->map->type == _DRM_SHM &&
  285. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  286. dev_priv->sarea_map = r_list->map;
  287. break;
  288. }
  289. }
  290. if (!dev_priv->sarea_map) {
  291. dev->dev_private = (void *)dev_priv;
  292. i810_dma_cleanup(dev);
  293. DRM_ERROR("can not find sarea!\n");
  294. return -EINVAL;
  295. }
  296. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  297. if (!dev_priv->mmio_map) {
  298. dev->dev_private = (void *)dev_priv;
  299. i810_dma_cleanup(dev);
  300. DRM_ERROR("can not find mmio map!\n");
  301. return -EINVAL;
  302. }
  303. dev->agp_buffer_token = init->buffers_offset;
  304. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  305. if (!dev->agp_buffer_map) {
  306. dev->dev_private = (void *)dev_priv;
  307. i810_dma_cleanup(dev);
  308. DRM_ERROR("can not find dma buffer map!\n");
  309. return -EINVAL;
  310. }
  311. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  312. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  313. dev_priv->ring.Start = init->ring_start;
  314. dev_priv->ring.End = init->ring_end;
  315. dev_priv->ring.Size = init->ring_size;
  316. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  317. dev_priv->ring.map.size = init->ring_size;
  318. dev_priv->ring.map.type = _DRM_AGP;
  319. dev_priv->ring.map.flags = 0;
  320. dev_priv->ring.map.mtrr = 0;
  321. drm_core_ioremap(&dev_priv->ring.map, dev);
  322. if (dev_priv->ring.map.handle == NULL) {
  323. dev->dev_private = (void *)dev_priv;
  324. i810_dma_cleanup(dev);
  325. DRM_ERROR("can not ioremap virtual address for"
  326. " ring buffer\n");
  327. return DRM_ERR(ENOMEM);
  328. }
  329. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  330. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  331. dev_priv->w = init->w;
  332. dev_priv->h = init->h;
  333. dev_priv->pitch = init->pitch;
  334. dev_priv->back_offset = init->back_offset;
  335. dev_priv->depth_offset = init->depth_offset;
  336. dev_priv->front_offset = init->front_offset;
  337. dev_priv->overlay_offset = init->overlay_offset;
  338. dev_priv->overlay_physical = init->overlay_physical;
  339. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  340. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  341. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  342. /* Program Hardware Status Page */
  343. dev_priv->hw_status_page =
  344. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  345. &dev_priv->dma_status_page);
  346. if (!dev_priv->hw_status_page) {
  347. dev->dev_private = (void *)dev_priv;
  348. i810_dma_cleanup(dev);
  349. DRM_ERROR("Can not allocate hardware status page\n");
  350. return -ENOMEM;
  351. }
  352. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  353. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  354. I810_WRITE(0x02080, dev_priv->dma_status_page);
  355. DRM_DEBUG("Enabled hardware status page\n");
  356. /* Now we need to init our freelist */
  357. if (i810_freelist_init(dev, dev_priv) != 0) {
  358. dev->dev_private = (void *)dev_priv;
  359. i810_dma_cleanup(dev);
  360. DRM_ERROR("Not enough space in the status page for"
  361. " the freelist\n");
  362. return -ENOMEM;
  363. }
  364. dev->dev_private = (void *)dev_priv;
  365. return 0;
  366. }
  367. /* i810 DRM version 1.1 used a smaller init structure with different
  368. * ordering of values than is currently used (drm >= 1.2). There is
  369. * no defined way to detect the XFree version to correct this problem,
  370. * however by checking using this procedure we can detect the correct
  371. * thing to do.
  372. *
  373. * #1 Read the Smaller init structure from user-space
  374. * #2 Verify the overlay_physical is a valid physical address, or NULL
  375. * If it isn't then we have a v1.1 client. Fix up params.
  376. * If it is, then we have a 1.2 client... get the rest of the data.
  377. */
  378. static int i810_dma_init_compat(drm_i810_init_t * init, unsigned long arg)
  379. {
  380. /* Get v1.1 init data */
  381. if (copy_from_user(init, (drm_i810_pre12_init_t __user *) arg,
  382. sizeof(drm_i810_pre12_init_t))) {
  383. return -EFAULT;
  384. }
  385. if ((!init->overlay_physical) || (init->overlay_physical > 4096)) {
  386. /* This is a v1.2 client, just get the v1.2 init data */
  387. DRM_INFO("Using POST v1.2 init.\n");
  388. if (copy_from_user(init, (drm_i810_init_t __user *) arg,
  389. sizeof(drm_i810_init_t))) {
  390. return -EFAULT;
  391. }
  392. } else {
  393. /* This is a v1.1 client, fix the params */
  394. DRM_INFO("Using PRE v1.2 init.\n");
  395. init->pitch_bits = init->h;
  396. init->pitch = init->w;
  397. init->h = init->overlay_physical;
  398. init->w = init->overlay_offset;
  399. init->overlay_physical = 0;
  400. init->overlay_offset = 0;
  401. }
  402. return 0;
  403. }
  404. static int i810_dma_init(struct inode *inode, struct file *filp,
  405. unsigned int cmd, unsigned long arg)
  406. {
  407. drm_file_t *priv = filp->private_data;
  408. drm_device_t *dev = priv->head->dev;
  409. drm_i810_private_t *dev_priv;
  410. drm_i810_init_t init;
  411. int retcode = 0;
  412. /* Get only the init func */
  413. if (copy_from_user
  414. (&init, (void __user *)arg, sizeof(drm_i810_init_func_t)))
  415. return -EFAULT;
  416. switch (init.func) {
  417. case I810_INIT_DMA:
  418. /* This case is for backward compatibility. It
  419. * handles XFree 4.1.0 and 4.2.0, and has to
  420. * do some parameter checking as described below.
  421. * It will someday go away.
  422. */
  423. retcode = i810_dma_init_compat(&init, arg);
  424. if (retcode)
  425. return retcode;
  426. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  427. DRM_MEM_DRIVER);
  428. if (dev_priv == NULL)
  429. return -ENOMEM;
  430. retcode = i810_dma_initialize(dev, dev_priv, &init);
  431. break;
  432. default:
  433. case I810_INIT_DMA_1_4:
  434. DRM_INFO("Using v1.4 init.\n");
  435. if (copy_from_user(&init, (drm_i810_init_t __user *) arg,
  436. sizeof(drm_i810_init_t))) {
  437. return -EFAULT;
  438. }
  439. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  440. DRM_MEM_DRIVER);
  441. if (dev_priv == NULL)
  442. return -ENOMEM;
  443. retcode = i810_dma_initialize(dev, dev_priv, &init);
  444. break;
  445. case I810_CLEANUP_DMA:
  446. DRM_INFO("DMA Cleanup\n");
  447. retcode = i810_dma_cleanup(dev);
  448. break;
  449. }
  450. return retcode;
  451. }
  452. /* Most efficient way to verify state for the i810 is as it is
  453. * emitted. Non-conformant state is silently dropped.
  454. *
  455. * Use 'volatile' & local var tmp to force the emitted values to be
  456. * identical to the verified ones.
  457. */
  458. static void i810EmitContextVerified(drm_device_t * dev,
  459. volatile unsigned int *code)
  460. {
  461. drm_i810_private_t *dev_priv = dev->dev_private;
  462. int i, j = 0;
  463. unsigned int tmp;
  464. RING_LOCALS;
  465. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  466. OUT_RING(GFX_OP_COLOR_FACTOR);
  467. OUT_RING(code[I810_CTXREG_CF1]);
  468. OUT_RING(GFX_OP_STIPPLE);
  469. OUT_RING(code[I810_CTXREG_ST1]);
  470. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  471. tmp = code[i];
  472. if ((tmp & (7 << 29)) == (3 << 29) &&
  473. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  474. OUT_RING(tmp);
  475. j++;
  476. } else
  477. printk("constext state dropped!!!\n");
  478. }
  479. if (j & 1)
  480. OUT_RING(0);
  481. ADVANCE_LP_RING();
  482. }
  483. static void i810EmitTexVerified(drm_device_t * dev, volatile unsigned int *code)
  484. {
  485. drm_i810_private_t *dev_priv = dev->dev_private;
  486. int i, j = 0;
  487. unsigned int tmp;
  488. RING_LOCALS;
  489. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  490. OUT_RING(GFX_OP_MAP_INFO);
  491. OUT_RING(code[I810_TEXREG_MI1]);
  492. OUT_RING(code[I810_TEXREG_MI2]);
  493. OUT_RING(code[I810_TEXREG_MI3]);
  494. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  495. tmp = code[i];
  496. if ((tmp & (7 << 29)) == (3 << 29) &&
  497. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  498. OUT_RING(tmp);
  499. j++;
  500. } else
  501. printk("texture state dropped!!!\n");
  502. }
  503. if (j & 1)
  504. OUT_RING(0);
  505. ADVANCE_LP_RING();
  506. }
  507. /* Need to do some additional checking when setting the dest buffer.
  508. */
  509. static void i810EmitDestVerified(drm_device_t * dev,
  510. volatile unsigned int *code)
  511. {
  512. drm_i810_private_t *dev_priv = dev->dev_private;
  513. unsigned int tmp;
  514. RING_LOCALS;
  515. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  516. tmp = code[I810_DESTREG_DI1];
  517. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  518. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  519. OUT_RING(tmp);
  520. } else
  521. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  522. tmp, dev_priv->front_di1, dev_priv->back_di1);
  523. /* invarient:
  524. */
  525. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  526. OUT_RING(dev_priv->zi1);
  527. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  528. OUT_RING(code[I810_DESTREG_DV1]);
  529. OUT_RING(GFX_OP_DRAWRECT_INFO);
  530. OUT_RING(code[I810_DESTREG_DR1]);
  531. OUT_RING(code[I810_DESTREG_DR2]);
  532. OUT_RING(code[I810_DESTREG_DR3]);
  533. OUT_RING(code[I810_DESTREG_DR4]);
  534. OUT_RING(0);
  535. ADVANCE_LP_RING();
  536. }
  537. static void i810EmitState(drm_device_t * dev)
  538. {
  539. drm_i810_private_t *dev_priv = dev->dev_private;
  540. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  541. unsigned int dirty = sarea_priv->dirty;
  542. DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
  543. if (dirty & I810_UPLOAD_BUFFERS) {
  544. i810EmitDestVerified(dev, sarea_priv->BufferState);
  545. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  546. }
  547. if (dirty & I810_UPLOAD_CTX) {
  548. i810EmitContextVerified(dev, sarea_priv->ContextState);
  549. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  550. }
  551. if (dirty & I810_UPLOAD_TEX0) {
  552. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  553. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  554. }
  555. if (dirty & I810_UPLOAD_TEX1) {
  556. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  557. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  558. }
  559. }
  560. /* need to verify
  561. */
  562. static void i810_dma_dispatch_clear(drm_device_t * dev, int flags,
  563. unsigned int clear_color,
  564. unsigned int clear_zval)
  565. {
  566. drm_i810_private_t *dev_priv = dev->dev_private;
  567. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  568. int nbox = sarea_priv->nbox;
  569. drm_clip_rect_t *pbox = sarea_priv->boxes;
  570. int pitch = dev_priv->pitch;
  571. int cpp = 2;
  572. int i;
  573. RING_LOCALS;
  574. if (dev_priv->current_page == 1) {
  575. unsigned int tmp = flags;
  576. flags &= ~(I810_FRONT | I810_BACK);
  577. if (tmp & I810_FRONT)
  578. flags |= I810_BACK;
  579. if (tmp & I810_BACK)
  580. flags |= I810_FRONT;
  581. }
  582. i810_kernel_lost_context(dev);
  583. if (nbox > I810_NR_SAREA_CLIPRECTS)
  584. nbox = I810_NR_SAREA_CLIPRECTS;
  585. for (i = 0; i < nbox; i++, pbox++) {
  586. unsigned int x = pbox->x1;
  587. unsigned int y = pbox->y1;
  588. unsigned int width = (pbox->x2 - x) * cpp;
  589. unsigned int height = pbox->y2 - y;
  590. unsigned int start = y * pitch + x * cpp;
  591. if (pbox->x1 > pbox->x2 ||
  592. pbox->y1 > pbox->y2 ||
  593. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  594. continue;
  595. if (flags & I810_FRONT) {
  596. BEGIN_LP_RING(6);
  597. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  598. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  599. OUT_RING((height << 16) | width);
  600. OUT_RING(start);
  601. OUT_RING(clear_color);
  602. OUT_RING(0);
  603. ADVANCE_LP_RING();
  604. }
  605. if (flags & I810_BACK) {
  606. BEGIN_LP_RING(6);
  607. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  608. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  609. OUT_RING((height << 16) | width);
  610. OUT_RING(dev_priv->back_offset + start);
  611. OUT_RING(clear_color);
  612. OUT_RING(0);
  613. ADVANCE_LP_RING();
  614. }
  615. if (flags & I810_DEPTH) {
  616. BEGIN_LP_RING(6);
  617. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  618. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  619. OUT_RING((height << 16) | width);
  620. OUT_RING(dev_priv->depth_offset + start);
  621. OUT_RING(clear_zval);
  622. OUT_RING(0);
  623. ADVANCE_LP_RING();
  624. }
  625. }
  626. }
  627. static void i810_dma_dispatch_swap(drm_device_t * dev)
  628. {
  629. drm_i810_private_t *dev_priv = dev->dev_private;
  630. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  631. int nbox = sarea_priv->nbox;
  632. drm_clip_rect_t *pbox = sarea_priv->boxes;
  633. int pitch = dev_priv->pitch;
  634. int cpp = 2;
  635. int i;
  636. RING_LOCALS;
  637. DRM_DEBUG("swapbuffers\n");
  638. i810_kernel_lost_context(dev);
  639. if (nbox > I810_NR_SAREA_CLIPRECTS)
  640. nbox = I810_NR_SAREA_CLIPRECTS;
  641. for (i = 0; i < nbox; i++, pbox++) {
  642. unsigned int w = pbox->x2 - pbox->x1;
  643. unsigned int h = pbox->y2 - pbox->y1;
  644. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  645. unsigned int start = dst;
  646. if (pbox->x1 > pbox->x2 ||
  647. pbox->y1 > pbox->y2 ||
  648. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  649. continue;
  650. BEGIN_LP_RING(6);
  651. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  652. OUT_RING(pitch | (0xCC << 16));
  653. OUT_RING((h << 16) | (w * cpp));
  654. if (dev_priv->current_page == 0)
  655. OUT_RING(dev_priv->front_offset + start);
  656. else
  657. OUT_RING(dev_priv->back_offset + start);
  658. OUT_RING(pitch);
  659. if (dev_priv->current_page == 0)
  660. OUT_RING(dev_priv->back_offset + start);
  661. else
  662. OUT_RING(dev_priv->front_offset + start);
  663. ADVANCE_LP_RING();
  664. }
  665. }
  666. static void i810_dma_dispatch_vertex(drm_device_t * dev,
  667. drm_buf_t * buf, int discard, int used)
  668. {
  669. drm_i810_private_t *dev_priv = dev->dev_private;
  670. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  671. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  672. drm_clip_rect_t *box = sarea_priv->boxes;
  673. int nbox = sarea_priv->nbox;
  674. unsigned long address = (unsigned long)buf->bus_address;
  675. unsigned long start = address - dev->agp->base;
  676. int i = 0;
  677. RING_LOCALS;
  678. i810_kernel_lost_context(dev);
  679. if (nbox > I810_NR_SAREA_CLIPRECTS)
  680. nbox = I810_NR_SAREA_CLIPRECTS;
  681. if (used > 4 * 1024)
  682. used = 0;
  683. if (sarea_priv->dirty)
  684. i810EmitState(dev);
  685. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  686. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  687. *(u32 *) buf_priv->kernel_virtual =
  688. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  689. if (used & 4) {
  690. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  691. used += 4;
  692. }
  693. i810_unmap_buffer(buf);
  694. }
  695. if (used) {
  696. do {
  697. if (i < nbox) {
  698. BEGIN_LP_RING(4);
  699. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  700. SC_ENABLE);
  701. OUT_RING(GFX_OP_SCISSOR_INFO);
  702. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  703. OUT_RING((box[i].x2 -
  704. 1) | ((box[i].y2 - 1) << 16));
  705. ADVANCE_LP_RING();
  706. }
  707. BEGIN_LP_RING(4);
  708. OUT_RING(CMD_OP_BATCH_BUFFER);
  709. OUT_RING(start | BB1_PROTECTED);
  710. OUT_RING(start + used - 4);
  711. OUT_RING(0);
  712. ADVANCE_LP_RING();
  713. } while (++i < nbox);
  714. }
  715. if (discard) {
  716. dev_priv->counter++;
  717. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  718. I810_BUF_HARDWARE);
  719. BEGIN_LP_RING(8);
  720. OUT_RING(CMD_STORE_DWORD_IDX);
  721. OUT_RING(20);
  722. OUT_RING(dev_priv->counter);
  723. OUT_RING(CMD_STORE_DWORD_IDX);
  724. OUT_RING(buf_priv->my_use_idx);
  725. OUT_RING(I810_BUF_FREE);
  726. OUT_RING(CMD_REPORT_HEAD);
  727. OUT_RING(0);
  728. ADVANCE_LP_RING();
  729. }
  730. }
  731. static void i810_dma_dispatch_flip(drm_device_t * dev)
  732. {
  733. drm_i810_private_t *dev_priv = dev->dev_private;
  734. int pitch = dev_priv->pitch;
  735. RING_LOCALS;
  736. DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
  737. __FUNCTION__,
  738. dev_priv->current_page,
  739. dev_priv->sarea_priv->pf_current_page);
  740. i810_kernel_lost_context(dev);
  741. BEGIN_LP_RING(2);
  742. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  743. OUT_RING(0);
  744. ADVANCE_LP_RING();
  745. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  746. /* On i815 at least ASYNC is buggy */
  747. /* pitch<<5 is from 11.2.8 p158,
  748. its the pitch / 8 then left shifted 8,
  749. so (pitch >> 3) << 8 */
  750. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  751. if (dev_priv->current_page == 0) {
  752. OUT_RING(dev_priv->back_offset);
  753. dev_priv->current_page = 1;
  754. } else {
  755. OUT_RING(dev_priv->front_offset);
  756. dev_priv->current_page = 0;
  757. }
  758. OUT_RING(0);
  759. ADVANCE_LP_RING();
  760. BEGIN_LP_RING(2);
  761. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  762. OUT_RING(0);
  763. ADVANCE_LP_RING();
  764. /* Increment the frame counter. The client-side 3D driver must
  765. * throttle the framerate by waiting for this value before
  766. * performing the swapbuffer ioctl.
  767. */
  768. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  769. }
  770. static void i810_dma_quiescent(drm_device_t * dev)
  771. {
  772. drm_i810_private_t *dev_priv = dev->dev_private;
  773. RING_LOCALS;
  774. /* printk("%s\n", __FUNCTION__); */
  775. i810_kernel_lost_context(dev);
  776. BEGIN_LP_RING(4);
  777. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  778. OUT_RING(CMD_REPORT_HEAD);
  779. OUT_RING(0);
  780. OUT_RING(0);
  781. ADVANCE_LP_RING();
  782. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  783. }
  784. static int i810_flush_queue(drm_device_t * dev)
  785. {
  786. drm_i810_private_t *dev_priv = dev->dev_private;
  787. drm_device_dma_t *dma = dev->dma;
  788. int i, ret = 0;
  789. RING_LOCALS;
  790. /* printk("%s\n", __FUNCTION__); */
  791. i810_kernel_lost_context(dev);
  792. BEGIN_LP_RING(2);
  793. OUT_RING(CMD_REPORT_HEAD);
  794. OUT_RING(0);
  795. ADVANCE_LP_RING();
  796. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  797. for (i = 0; i < dma->buf_count; i++) {
  798. drm_buf_t *buf = dma->buflist[i];
  799. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  800. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  801. I810_BUF_FREE);
  802. if (used == I810_BUF_HARDWARE)
  803. DRM_DEBUG("reclaimed from HARDWARE\n");
  804. if (used == I810_BUF_CLIENT)
  805. DRM_DEBUG("still on client\n");
  806. }
  807. return ret;
  808. }
  809. /* Must be called with the lock held */
  810. static void i810_reclaim_buffers(drm_device_t * dev, struct file *filp)
  811. {
  812. drm_device_dma_t *dma = dev->dma;
  813. int i;
  814. if (!dma)
  815. return;
  816. if (!dev->dev_private)
  817. return;
  818. if (!dma->buflist)
  819. return;
  820. i810_flush_queue(dev);
  821. for (i = 0; i < dma->buf_count; i++) {
  822. drm_buf_t *buf = dma->buflist[i];
  823. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  824. if (buf->filp == filp && buf_priv) {
  825. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  826. I810_BUF_FREE);
  827. if (used == I810_BUF_CLIENT)
  828. DRM_DEBUG("reclaimed from client\n");
  829. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  830. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  831. }
  832. }
  833. }
  834. static int i810_flush_ioctl(struct inode *inode, struct file *filp,
  835. unsigned int cmd, unsigned long arg)
  836. {
  837. drm_file_t *priv = filp->private_data;
  838. drm_device_t *dev = priv->head->dev;
  839. LOCK_TEST_WITH_RETURN(dev, filp);
  840. i810_flush_queue(dev);
  841. return 0;
  842. }
  843. static int i810_dma_vertex(struct inode *inode, struct file *filp,
  844. unsigned int cmd, unsigned long arg)
  845. {
  846. drm_file_t *priv = filp->private_data;
  847. drm_device_t *dev = priv->head->dev;
  848. drm_device_dma_t *dma = dev->dma;
  849. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  850. u32 *hw_status = dev_priv->hw_status_page;
  851. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  852. dev_priv->sarea_priv;
  853. drm_i810_vertex_t vertex;
  854. if (copy_from_user
  855. (&vertex, (drm_i810_vertex_t __user *) arg, sizeof(vertex)))
  856. return -EFAULT;
  857. LOCK_TEST_WITH_RETURN(dev, filp);
  858. DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
  859. vertex.idx, vertex.used, vertex.discard);
  860. if (vertex.idx < 0 || vertex.idx > dma->buf_count)
  861. return -EINVAL;
  862. i810_dma_dispatch_vertex(dev,
  863. dma->buflist[vertex.idx],
  864. vertex.discard, vertex.used);
  865. atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
  866. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  867. sarea_priv->last_enqueue = dev_priv->counter - 1;
  868. sarea_priv->last_dispatch = (int)hw_status[5];
  869. return 0;
  870. }
  871. static int i810_clear_bufs(struct inode *inode, struct file *filp,
  872. unsigned int cmd, unsigned long arg)
  873. {
  874. drm_file_t *priv = filp->private_data;
  875. drm_device_t *dev = priv->head->dev;
  876. drm_i810_clear_t clear;
  877. if (copy_from_user
  878. (&clear, (drm_i810_clear_t __user *) arg, sizeof(clear)))
  879. return -EFAULT;
  880. LOCK_TEST_WITH_RETURN(dev, filp);
  881. /* GH: Someone's doing nasty things... */
  882. if (!dev->dev_private) {
  883. return -EINVAL;
  884. }
  885. i810_dma_dispatch_clear(dev, clear.flags,
  886. clear.clear_color, clear.clear_depth);
  887. return 0;
  888. }
  889. static int i810_swap_bufs(struct inode *inode, struct file *filp,
  890. unsigned int cmd, unsigned long arg)
  891. {
  892. drm_file_t *priv = filp->private_data;
  893. drm_device_t *dev = priv->head->dev;
  894. DRM_DEBUG("i810_swap_bufs\n");
  895. LOCK_TEST_WITH_RETURN(dev, filp);
  896. i810_dma_dispatch_swap(dev);
  897. return 0;
  898. }
  899. static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
  900. unsigned long arg)
  901. {
  902. drm_file_t *priv = filp->private_data;
  903. drm_device_t *dev = priv->head->dev;
  904. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  905. u32 *hw_status = dev_priv->hw_status_page;
  906. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  907. dev_priv->sarea_priv;
  908. sarea_priv->last_dispatch = (int)hw_status[5];
  909. return 0;
  910. }
  911. static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
  912. unsigned long arg)
  913. {
  914. drm_file_t *priv = filp->private_data;
  915. drm_device_t *dev = priv->head->dev;
  916. int retcode = 0;
  917. drm_i810_dma_t d;
  918. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  919. u32 *hw_status = dev_priv->hw_status_page;
  920. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  921. dev_priv->sarea_priv;
  922. if (copy_from_user(&d, (drm_i810_dma_t __user *) arg, sizeof(d)))
  923. return -EFAULT;
  924. LOCK_TEST_WITH_RETURN(dev, filp);
  925. d.granted = 0;
  926. retcode = i810_dma_get_buffer(dev, &d, filp);
  927. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  928. current->pid, retcode, d.granted);
  929. if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d)))
  930. return -EFAULT;
  931. sarea_priv->last_dispatch = (int)hw_status[5];
  932. return retcode;
  933. }
  934. static int i810_copybuf(struct inode *inode,
  935. struct file *filp, unsigned int cmd, unsigned long arg)
  936. {
  937. /* Never copy - 2.4.x doesn't need it */
  938. return 0;
  939. }
  940. static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
  941. unsigned long arg)
  942. {
  943. /* Never copy - 2.4.x doesn't need it */
  944. return 0;
  945. }
  946. static void i810_dma_dispatch_mc(drm_device_t * dev, drm_buf_t * buf, int used,
  947. unsigned int last_render)
  948. {
  949. drm_i810_private_t *dev_priv = dev->dev_private;
  950. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  951. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  952. unsigned long address = (unsigned long)buf->bus_address;
  953. unsigned long start = address - dev->agp->base;
  954. int u;
  955. RING_LOCALS;
  956. i810_kernel_lost_context(dev);
  957. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  958. if (u != I810_BUF_CLIENT) {
  959. DRM_DEBUG("MC found buffer that isn't mine!\n");
  960. }
  961. if (used > 4 * 1024)
  962. used = 0;
  963. sarea_priv->dirty = 0x7f;
  964. DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used);
  965. dev_priv->counter++;
  966. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  967. DRM_DEBUG("i810_dma_dispatch_mc\n");
  968. DRM_DEBUG("start : %lx\n", start);
  969. DRM_DEBUG("used : %d\n", used);
  970. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  971. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  972. if (used & 4) {
  973. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  974. used += 4;
  975. }
  976. i810_unmap_buffer(buf);
  977. }
  978. BEGIN_LP_RING(4);
  979. OUT_RING(CMD_OP_BATCH_BUFFER);
  980. OUT_RING(start | BB1_PROTECTED);
  981. OUT_RING(start + used - 4);
  982. OUT_RING(0);
  983. ADVANCE_LP_RING();
  984. BEGIN_LP_RING(8);
  985. OUT_RING(CMD_STORE_DWORD_IDX);
  986. OUT_RING(buf_priv->my_use_idx);
  987. OUT_RING(I810_BUF_FREE);
  988. OUT_RING(0);
  989. OUT_RING(CMD_STORE_DWORD_IDX);
  990. OUT_RING(16);
  991. OUT_RING(last_render);
  992. OUT_RING(0);
  993. ADVANCE_LP_RING();
  994. }
  995. static int i810_dma_mc(struct inode *inode, struct file *filp,
  996. unsigned int cmd, unsigned long arg)
  997. {
  998. drm_file_t *priv = filp->private_data;
  999. drm_device_t *dev = priv->head->dev;
  1000. drm_device_dma_t *dma = dev->dma;
  1001. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1002. u32 *hw_status = dev_priv->hw_status_page;
  1003. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  1004. dev_priv->sarea_priv;
  1005. drm_i810_mc_t mc;
  1006. if (copy_from_user(&mc, (drm_i810_mc_t __user *) arg, sizeof(mc)))
  1007. return -EFAULT;
  1008. LOCK_TEST_WITH_RETURN(dev, filp);
  1009. if (mc.idx >= dma->buf_count || mc.idx < 0)
  1010. return -EINVAL;
  1011. i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used,
  1012. mc.last_render);
  1013. atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]);
  1014. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  1015. sarea_priv->last_enqueue = dev_priv->counter - 1;
  1016. sarea_priv->last_dispatch = (int)hw_status[5];
  1017. return 0;
  1018. }
  1019. static int i810_rstatus(struct inode *inode, struct file *filp,
  1020. unsigned int cmd, unsigned long arg)
  1021. {
  1022. drm_file_t *priv = filp->private_data;
  1023. drm_device_t *dev = priv->head->dev;
  1024. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1025. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  1026. }
  1027. static int i810_ov0_info(struct inode *inode, struct file *filp,
  1028. unsigned int cmd, unsigned long arg)
  1029. {
  1030. drm_file_t *priv = filp->private_data;
  1031. drm_device_t *dev = priv->head->dev;
  1032. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1033. drm_i810_overlay_t data;
  1034. data.offset = dev_priv->overlay_offset;
  1035. data.physical = dev_priv->overlay_physical;
  1036. if (copy_to_user
  1037. ((drm_i810_overlay_t __user *) arg, &data, sizeof(data)))
  1038. return -EFAULT;
  1039. return 0;
  1040. }
  1041. static int i810_fstatus(struct inode *inode, struct file *filp,
  1042. unsigned int cmd, unsigned long arg)
  1043. {
  1044. drm_file_t *priv = filp->private_data;
  1045. drm_device_t *dev = priv->head->dev;
  1046. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1047. LOCK_TEST_WITH_RETURN(dev, filp);
  1048. return I810_READ(0x30008);
  1049. }
  1050. static int i810_ov0_flip(struct inode *inode, struct file *filp,
  1051. unsigned int cmd, unsigned long arg)
  1052. {
  1053. drm_file_t *priv = filp->private_data;
  1054. drm_device_t *dev = priv->head->dev;
  1055. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  1056. LOCK_TEST_WITH_RETURN(dev, filp);
  1057. //Tell the overlay to update
  1058. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  1059. return 0;
  1060. }
  1061. /* Not sure why this isn't set all the time:
  1062. */
  1063. static void i810_do_init_pageflip(drm_device_t * dev)
  1064. {
  1065. drm_i810_private_t *dev_priv = dev->dev_private;
  1066. DRM_DEBUG("%s\n", __FUNCTION__);
  1067. dev_priv->page_flipping = 1;
  1068. dev_priv->current_page = 0;
  1069. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  1070. }
  1071. static int i810_do_cleanup_pageflip(drm_device_t * dev)
  1072. {
  1073. drm_i810_private_t *dev_priv = dev->dev_private;
  1074. DRM_DEBUG("%s\n", __FUNCTION__);
  1075. if (dev_priv->current_page != 0)
  1076. i810_dma_dispatch_flip(dev);
  1077. dev_priv->page_flipping = 0;
  1078. return 0;
  1079. }
  1080. static int i810_flip_bufs(struct inode *inode, struct file *filp,
  1081. unsigned int cmd, unsigned long arg)
  1082. {
  1083. drm_file_t *priv = filp->private_data;
  1084. drm_device_t *dev = priv->head->dev;
  1085. drm_i810_private_t *dev_priv = dev->dev_private;
  1086. DRM_DEBUG("%s\n", __FUNCTION__);
  1087. LOCK_TEST_WITH_RETURN(dev, filp);
  1088. if (!dev_priv->page_flipping)
  1089. i810_do_init_pageflip(dev);
  1090. i810_dma_dispatch_flip(dev);
  1091. return 0;
  1092. }
  1093. int i810_driver_load(drm_device_t *dev, unsigned long flags)
  1094. {
  1095. /* i810 has 4 more counters */
  1096. dev->counters += 4;
  1097. dev->types[6] = _DRM_STAT_IRQ;
  1098. dev->types[7] = _DRM_STAT_PRIMARY;
  1099. dev->types[8] = _DRM_STAT_SECONDARY;
  1100. dev->types[9] = _DRM_STAT_DMA;
  1101. return 0;
  1102. }
  1103. void i810_driver_lastclose(drm_device_t * dev)
  1104. {
  1105. i810_dma_cleanup(dev);
  1106. }
  1107. void i810_driver_preclose(drm_device_t * dev, DRMFILE filp)
  1108. {
  1109. if (dev->dev_private) {
  1110. drm_i810_private_t *dev_priv = dev->dev_private;
  1111. if (dev_priv->page_flipping) {
  1112. i810_do_cleanup_pageflip(dev);
  1113. }
  1114. }
  1115. }
  1116. void i810_driver_reclaim_buffers_locked(drm_device_t * dev, struct file *filp)
  1117. {
  1118. i810_reclaim_buffers(dev, filp);
  1119. }
  1120. int i810_driver_dma_quiescent(drm_device_t * dev)
  1121. {
  1122. i810_dma_quiescent(dev);
  1123. return 0;
  1124. }
  1125. drm_ioctl_desc_t i810_ioctls[] = {
  1126. [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
  1127. [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, DRM_AUTH},
  1128. [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, DRM_AUTH},
  1129. [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, DRM_AUTH},
  1130. [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, DRM_AUTH},
  1131. [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, DRM_AUTH},
  1132. [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, DRM_AUTH},
  1133. [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, DRM_AUTH},
  1134. [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, DRM_AUTH},
  1135. [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, DRM_AUTH},
  1136. [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, DRM_AUTH},
  1137. [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, DRM_AUTH},
  1138. [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
  1139. [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, DRM_AUTH},
  1140. [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, DRM_AUTH}
  1141. };
  1142. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1143. /**
  1144. * Determine if the device really is AGP or not.
  1145. *
  1146. * All Intel graphics chipsets are treated as AGP, even if they are really
  1147. * PCI-e.
  1148. *
  1149. * \param dev The device to be tested.
  1150. *
  1151. * \returns
  1152. * A value of 1 is always retured to indictate every i810 is AGP.
  1153. */
  1154. int i810_driver_device_is_agp(drm_device_t * dev)
  1155. {
  1156. return 1;
  1157. }