timer-tmu.c 4.0 KB

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  1. /*
  2. * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
  3. *
  4. * Copyright (C) 2005 Paul Mundt
  5. *
  6. * TMU handling code hacked out of arch/sh/kernel/time.c
  7. *
  8. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  9. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  10. * Copyright (C) 2002, 2003, 2004 Paul Mundt
  11. * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
  12. *
  13. * This file is subject to the terms and conditions of the GNU General Public
  14. * License. See the file "COPYING" in the main directory of this archive
  15. * for more details.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/seqlock.h>
  21. #include <asm/timer.h>
  22. #include <asm/rtc.h>
  23. #include <asm/io.h>
  24. #include <asm/irq.h>
  25. #include <asm/clock.h>
  26. #define TMU_TOCR_INIT 0x00
  27. #define TMU0_TCR_INIT 0x0020
  28. #define TMU_TSTR_INIT 1
  29. #define TMU0_TCR_CALIB 0x0000
  30. static unsigned long tmu_timer_get_offset(void)
  31. {
  32. int count;
  33. static int count_p = 0x7fffffff; /* for the first call after boot */
  34. static unsigned long jiffies_p = 0;
  35. /*
  36. * cache volatile jiffies temporarily; we have IRQs turned off.
  37. */
  38. unsigned long jiffies_t;
  39. /* timer count may underflow right here */
  40. count = ctrl_inl(TMU0_TCNT); /* read the latched count */
  41. jiffies_t = jiffies;
  42. /*
  43. * avoiding timer inconsistencies (they are rare, but they happen)...
  44. * there is one kind of problem that must be avoided here:
  45. * 1. the timer counter underflows
  46. */
  47. if (jiffies_t == jiffies_p) {
  48. if (count > count_p) {
  49. /* the nutcase */
  50. if (ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
  51. count -= LATCH;
  52. } else {
  53. printk("%s (): hardware timer problem?\n",
  54. __FUNCTION__);
  55. }
  56. }
  57. } else
  58. jiffies_p = jiffies_t;
  59. count_p = count;
  60. count = ((LATCH-1) - count) * TICK_SIZE;
  61. count = (count + LATCH/2) / LATCH;
  62. return count;
  63. }
  64. static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
  65. {
  66. unsigned long timer_status;
  67. /* Clear UNF bit */
  68. timer_status = ctrl_inw(TMU0_TCR);
  69. timer_status &= ~0x100;
  70. ctrl_outw(timer_status, TMU0_TCR);
  71. /*
  72. * Here we are in the timer irq handler. We just have irqs locally
  73. * disabled but we don't know if the timer_bh is running on the other
  74. * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
  75. * the irq version of write_lock because as just said we have irq
  76. * locally disabled. -arca
  77. */
  78. write_seqlock(&xtime_lock);
  79. handle_timer_tick();
  80. write_sequnlock(&xtime_lock);
  81. return IRQ_HANDLED;
  82. }
  83. static struct irqaction tmu_irq = {
  84. .name = "timer",
  85. .handler = tmu_timer_interrupt,
  86. .flags = IRQF_DISABLED | IRQF_TIMER,
  87. .mask = CPU_MASK_NONE,
  88. };
  89. static void tmu_clk_init(struct clk *clk)
  90. {
  91. u8 divisor = TMU0_TCR_INIT & 0x7;
  92. ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
  93. clk->rate = clk->parent->rate / (4 << (divisor << 1));
  94. }
  95. static void tmu_clk_recalc(struct clk *clk)
  96. {
  97. u8 divisor = ctrl_inw(TMU0_TCR) & 0x7;
  98. clk->rate = clk->parent->rate / (4 << (divisor << 1));
  99. }
  100. static struct clk_ops tmu_clk_ops = {
  101. .init = tmu_clk_init,
  102. .recalc = tmu_clk_recalc,
  103. };
  104. static struct clk tmu0_clk = {
  105. .name = "tmu0_clk",
  106. .ops = &tmu_clk_ops,
  107. };
  108. static int tmu_timer_start(void)
  109. {
  110. ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
  111. return 0;
  112. }
  113. static int tmu_timer_stop(void)
  114. {
  115. ctrl_outb(0, TMU_TSTR);
  116. return 0;
  117. }
  118. static int tmu_timer_init(void)
  119. {
  120. unsigned long interval;
  121. setup_irq(CONFIG_SH_TIMER_IRQ, &tmu_irq);
  122. tmu0_clk.parent = clk_get(NULL, "module_clk");
  123. /* Start TMU0 */
  124. tmu_timer_stop();
  125. #if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
  126. ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
  127. #endif
  128. clk_register(&tmu0_clk);
  129. clk_enable(&tmu0_clk);
  130. interval = (clk_get_rate(&tmu0_clk) + HZ / 2) / HZ;
  131. printk(KERN_INFO "Interval = %ld\n", interval);
  132. ctrl_outl(interval, TMU0_TCOR);
  133. ctrl_outl(interval, TMU0_TCNT);
  134. tmu_timer_start();
  135. return 0;
  136. }
  137. struct sys_timer_ops tmu_timer_ops = {
  138. .init = tmu_timer_init,
  139. .start = tmu_timer_start,
  140. .stop = tmu_timer_stop,
  141. #ifndef CONFIG_GENERIC_TIME
  142. .get_offset = tmu_timer_get_offset,
  143. #endif
  144. };
  145. struct sys_timer tmu_timer = {
  146. .name = "tmu",
  147. .ops = &tmu_timer_ops,
  148. };