reipl64.S 3.2 KB

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  1. /*
  2. * arch/s390/kernel/reipl.S
  3. *
  4. * S390 version
  5. * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
  6. * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com)
  7. Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
  8. */
  9. #include <asm/lowcore.h>
  10. .globl do_reipl_asm
  11. do_reipl_asm: basr %r13,0
  12. .Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
  13. .Lpg1: # do store status of all registers
  14. stg %r1,.Lregsave-.Lpg0(%r13)
  15. lghi %r1,0x1000
  16. stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1)
  17. lg %r0,.Lregsave-.Lpg0(%r13)
  18. stg %r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1)
  19. stctg %c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1)
  20. stam %a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1)
  21. mvc __LC_PREFIX_SAVE_AREA-0x1000(4,%r1),dump_prefix_page-.Lpg0(%r13)
  22. stfpc __LC_FP_CREG_SAVE_AREA-0x1000(%r1)
  23. stckc .Lclkcmp-.Lpg0(%r13)
  24. mvc __LC_CLOCK_COMP_SAVE_AREA-0x1000(8,%r1),.Lclkcmp-.Lpg0(%r13)
  25. stpt __LC_CPU_TIMER_SAVE_AREA-0x1000(%r1)
  26. stg %r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1)
  27. lctlg %c6,%c6,.Lall-.Lpg0(%r13)
  28. lgr %r1,%r2
  29. mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
  30. stsch .Lschib-.Lpg0(%r13)
  31. oi .Lschib+5-.Lpg0(%r13),0x84
  32. .Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
  33. msch .Lschib-.Lpg0(%r13)
  34. lghi %r0,5
  35. .Lssch: ssch .Liplorb-.Lpg0(%r13)
  36. jz .L001
  37. brct %r0,.Lssch
  38. bas %r14,.Ldisab-.Lpg0(%r13)
  39. .L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
  40. .Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
  41. .Lcont: c %r1,__LC_SUBCHANNEL_ID
  42. jnz .Ltpi
  43. clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
  44. jnz .Ltpi
  45. tsch .Liplirb-.Lpg0(%r13)
  46. tm .Liplirb+9-.Lpg0(%r13),0xbf
  47. jz .L002
  48. bas %r14,.Ldisab-.Lpg0(%r13)
  49. .L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
  50. jz .L003
  51. bas %r14,.Ldisab-.Lpg0(%r13)
  52. .L003: st %r1,__LC_SUBCHANNEL_ID
  53. lhi %r1,0 # mode 0 = esa
  54. slr %r0,%r0 # set cpuid to zero
  55. sigp %r1,%r0,0x12 # switch to esa mode
  56. lpsw 0
  57. .Ldisab: sll %r14,1
  58. srl %r14,1 # need to kill hi bit to avoid specification exceptions.
  59. st %r14,.Ldispsw+12-.Lpg0(%r13)
  60. lpswe .Ldispsw-.Lpg0(%r13)
  61. .align 8
  62. .Lclkcmp: .quad 0x0000000000000000
  63. .Lall: .quad 0x00000000ff000000
  64. .Lregsave: .quad 0x0000000000000000
  65. .align 16
  66. /*
  67. * These addresses have to be 31 bit otherwise
  68. * the sigp will throw a specifcation exception
  69. * when switching to ESA mode as bit 31 be set
  70. * in the ESA psw.
  71. * Bit 31 of the addresses has to be 0 for the
  72. * 31bit lpswe instruction a fact they appear to have
  73. * ommited from the pop.
  74. */
  75. .Lnewpsw: .quad 0x0000000080000000
  76. .quad .Lpg1
  77. .Lpcnew: .quad 0x0000000080000000
  78. .quad .Lecs
  79. .Lionew: .quad 0x0000000080000000
  80. .quad .Lcont
  81. .Lwaitpsw: .quad 0x0202000080000000
  82. .quad .Ltpi
  83. .Ldispsw: .quad 0x0002000080000000
  84. .quad 0x0000000000000000
  85. .Liplccws: .long 0x02000000,0x60000018
  86. .long 0x08000008,0x20000001
  87. .Liplorb: .long 0x0049504c,0x0040ff80
  88. .long 0x00000000+.Liplccws
  89. .Lschib: .long 0x00000000,0x00000000
  90. .long 0x00000000,0x00000000
  91. .long 0x00000000,0x00000000
  92. .long 0x00000000,0x00000000
  93. .long 0x00000000,0x00000000
  94. .long 0x00000000,0x00000000
  95. .Liplirb: .long 0x00000000,0x00000000
  96. .long 0x00000000,0x00000000
  97. .long 0x00000000,0x00000000
  98. .long 0x00000000,0x00000000
  99. .long 0x00000000,0x00000000
  100. .long 0x00000000,0x00000000
  101. .long 0x00000000,0x00000000
  102. .long 0x00000000,0x00000000
  103. .globl dump_prefix_page
  104. dump_prefix_page:
  105. .long 0x00000000