mpc8xx_pic.c 4.5 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/module.h>
  3. #include <linux/stddef.h>
  4. #include <linux/init.h>
  5. #include <linux/sched.h>
  6. #include <linux/signal.h>
  7. #include <linux/irq.h>
  8. #include <linux/dma-mapping.h>
  9. #include <asm/prom.h>
  10. #include <asm/irq.h>
  11. #include <asm/io.h>
  12. #include <asm/8xx_immap.h>
  13. #include <asm/mpc8xx.h>
  14. #include "mpc8xx_pic.h"
  15. #define PIC_VEC_SPURRIOUS 15
  16. extern int cpm_get_irq(struct pt_regs *regs);
  17. static struct device_node *mpc8xx_pic_node;
  18. static struct irq_host *mpc8xx_pic_host;
  19. #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
  20. static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  21. static sysconf8xx_t *siu_reg;
  22. int cpm_get_irq(struct pt_regs *regs);
  23. static void mpc8xx_unmask_irq(unsigned int virq)
  24. {
  25. int bit, word;
  26. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  27. bit = irq_nr & 0x1f;
  28. word = irq_nr >> 5;
  29. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  30. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  31. }
  32. static void mpc8xx_mask_irq(unsigned int virq)
  33. {
  34. int bit, word;
  35. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  36. bit = irq_nr & 0x1f;
  37. word = irq_nr >> 5;
  38. ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
  39. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  40. }
  41. static void mpc8xx_ack(unsigned int virq)
  42. {
  43. int bit;
  44. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  45. bit = irq_nr & 0x1f;
  46. out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
  47. }
  48. static void mpc8xx_end_irq(unsigned int virq)
  49. {
  50. int bit, word;
  51. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  52. bit = irq_nr & 0x1f;
  53. word = irq_nr >> 5;
  54. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  55. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  56. }
  57. static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
  58. {
  59. struct irq_desc *desc = get_irq_desc(virq);
  60. desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
  61. desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
  62. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  63. desc->status |= IRQ_LEVEL;
  64. if (flow_type & IRQ_TYPE_EDGE_FALLING) {
  65. irq_hw_number_t hw = (unsigned int)irq_map[virq].hwirq;
  66. unsigned int siel = in_be32(&siu_reg->sc_siel);
  67. /* only external IRQ senses are programmable */
  68. if ((hw & 1) == 0) {
  69. siel |= (0x80000000 >> hw);
  70. out_be32(&siu_reg->sc_siel, siel);
  71. desc->handle_irq = handle_edge_irq;
  72. }
  73. }
  74. return 0;
  75. }
  76. static struct irq_chip mpc8xx_pic = {
  77. .typename = " MPC8XX SIU ",
  78. .unmask = mpc8xx_unmask_irq,
  79. .mask = mpc8xx_mask_irq,
  80. .ack = mpc8xx_ack,
  81. .eoi = mpc8xx_end_irq,
  82. .set_type = mpc8xx_set_irq_type,
  83. };
  84. unsigned int mpc8xx_get_irq(void)
  85. {
  86. int irq;
  87. /* For MPC8xx, read the SIVEC register and shift the bits down
  88. * to get the irq number.
  89. */
  90. irq = in_be32(&siu_reg->sc_sivec) >> 26;
  91. if (irq == PIC_VEC_SPURRIOUS)
  92. irq = NO_IRQ;
  93. return irq_linear_revmap(mpc8xx_pic_host, irq);
  94. }
  95. static int mpc8xx_pic_host_match(struct irq_host *h, struct device_node *node)
  96. {
  97. return mpc8xx_pic_node == node;
  98. }
  99. static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
  100. irq_hw_number_t hw)
  101. {
  102. pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
  103. /* Set default irq handle */
  104. set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
  105. return 0;
  106. }
  107. static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct,
  108. u32 *intspec, unsigned int intsize,
  109. irq_hw_number_t *out_hwirq, unsigned int *out_flags)
  110. {
  111. static unsigned char map_pic_senses[4] = {
  112. IRQ_TYPE_EDGE_RISING,
  113. IRQ_TYPE_LEVEL_LOW,
  114. IRQ_TYPE_LEVEL_HIGH,
  115. IRQ_TYPE_EDGE_FALLING,
  116. };
  117. *out_hwirq = intspec[0];
  118. if (intsize > 1 && intspec[1] < 4)
  119. *out_flags = map_pic_senses[intspec[1]];
  120. else
  121. *out_flags = IRQ_TYPE_NONE;
  122. return 0;
  123. }
  124. static struct irq_host_ops mpc8xx_pic_host_ops = {
  125. .match = mpc8xx_pic_host_match,
  126. .map = mpc8xx_pic_host_map,
  127. .xlate = mpc8xx_pic_host_xlate,
  128. };
  129. int mpc8xx_pic_init(void)
  130. {
  131. struct resource res;
  132. struct device_node *np = NULL;
  133. int ret;
  134. np = of_find_node_by_type(np, "mpc8xx-pic");
  135. if (np == NULL) {
  136. printk(KERN_ERR "Could not find open-pic node\n");
  137. return -ENOMEM;
  138. }
  139. mpc8xx_pic_node = of_node_get(np);
  140. ret = of_address_to_resource(np, 0, &res);
  141. of_node_put(np);
  142. if (ret)
  143. return ret;
  144. siu_reg = (void *)ioremap(res.start, res.end - res.start + 1);
  145. if (siu_reg == NULL)
  146. return -EINVAL;
  147. mpc8xx_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &mpc8xx_pic_host_ops, 64);
  148. if (mpc8xx_pic_host == NULL) {
  149. printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
  150. ret = -ENOMEM;
  151. }
  152. return ret;
  153. }