smp.c 6.0 KB

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  1. /*
  2. * SMP support for pSeries machines.
  3. *
  4. * Dave Engebretsen, Peter Bergner, and
  5. * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
  6. *
  7. * Plus various changes from other IBM teams...
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version
  12. * 2 of the License, or (at your option) any later version.
  13. */
  14. #undef DEBUG
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/sched.h>
  18. #include <linux/smp.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/delay.h>
  21. #include <linux/init.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/cache.h>
  24. #include <linux/err.h>
  25. #include <linux/sysdev.h>
  26. #include <linux/cpu.h>
  27. #include <asm/ptrace.h>
  28. #include <asm/atomic.h>
  29. #include <asm/irq.h>
  30. #include <asm/page.h>
  31. #include <asm/pgtable.h>
  32. #include <asm/io.h>
  33. #include <asm/prom.h>
  34. #include <asm/smp.h>
  35. #include <asm/paca.h>
  36. #include <asm/time.h>
  37. #include <asm/machdep.h>
  38. #include "xics.h"
  39. #include <asm/cputable.h>
  40. #include <asm/firmware.h>
  41. #include <asm/system.h>
  42. #include <asm/rtas.h>
  43. #include <asm/pSeries_reconfig.h>
  44. #include <asm/mpic.h>
  45. #include <asm/vdso_datapage.h>
  46. #include "plpar_wrappers.h"
  47. #ifdef DEBUG
  48. #include <asm/udbg.h>
  49. #define DBG(fmt...) udbg_printf(fmt)
  50. #else
  51. #define DBG(fmt...)
  52. #endif
  53. /*
  54. * The primary thread of each non-boot processor is recorded here before
  55. * smp init.
  56. */
  57. static cpumask_t of_spin_map;
  58. extern void generic_secondary_smp_init(unsigned long);
  59. /**
  60. * smp_startup_cpu() - start the given cpu
  61. *
  62. * At boot time, there is nothing to do for primary threads which were
  63. * started from Open Firmware. For anything else, call RTAS with the
  64. * appropriate start location.
  65. *
  66. * Returns:
  67. * 0 - failure
  68. * 1 - success
  69. */
  70. static inline int __devinit smp_startup_cpu(unsigned int lcpu)
  71. {
  72. int status;
  73. unsigned long start_here = __pa((u32)*((unsigned long *)
  74. generic_secondary_smp_init));
  75. unsigned int pcpu;
  76. int start_cpu;
  77. if (cpu_isset(lcpu, of_spin_map))
  78. /* Already started by OF and sitting in spin loop */
  79. return 1;
  80. pcpu = get_hard_smp_processor_id(lcpu);
  81. /* Fixup atomic count: it exited inside IRQ handler. */
  82. task_thread_info(paca[lcpu].__current)->preempt_count = 0;
  83. /*
  84. * If the RTAS start-cpu token does not exist then presume the
  85. * cpu is already spinning.
  86. */
  87. start_cpu = rtas_token("start-cpu");
  88. if (start_cpu == RTAS_UNKNOWN_SERVICE)
  89. return 1;
  90. status = rtas_call(start_cpu, 3, 1, NULL, pcpu, start_here, pcpu);
  91. if (status != 0) {
  92. printk(KERN_ERR "start-cpu failed: %i\n", status);
  93. return 0;
  94. }
  95. return 1;
  96. }
  97. #ifdef CONFIG_XICS
  98. static inline void smp_xics_do_message(int cpu, int msg)
  99. {
  100. set_bit(msg, &xics_ipi_message[cpu].value);
  101. mb();
  102. xics_cause_IPI(cpu);
  103. }
  104. static void smp_xics_message_pass(int target, int msg)
  105. {
  106. unsigned int i;
  107. if (target < NR_CPUS) {
  108. smp_xics_do_message(target, msg);
  109. } else {
  110. for_each_online_cpu(i) {
  111. if (target == MSG_ALL_BUT_SELF
  112. && i == smp_processor_id())
  113. continue;
  114. smp_xics_do_message(i, msg);
  115. }
  116. }
  117. }
  118. static int __init smp_xics_probe(void)
  119. {
  120. xics_request_IPIs();
  121. return cpus_weight(cpu_possible_map);
  122. }
  123. static void __devinit smp_xics_setup_cpu(int cpu)
  124. {
  125. if (cpu != boot_cpuid)
  126. xics_setup_cpu();
  127. if (firmware_has_feature(FW_FEATURE_SPLPAR))
  128. vpa_init(cpu);
  129. cpu_clear(cpu, of_spin_map);
  130. }
  131. #endif /* CONFIG_XICS */
  132. static DEFINE_SPINLOCK(timebase_lock);
  133. static unsigned long timebase = 0;
  134. static void __devinit pSeries_give_timebase(void)
  135. {
  136. spin_lock(&timebase_lock);
  137. rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
  138. timebase = get_tb();
  139. spin_unlock(&timebase_lock);
  140. while (timebase)
  141. barrier();
  142. rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
  143. }
  144. static void __devinit pSeries_take_timebase(void)
  145. {
  146. while (!timebase)
  147. barrier();
  148. spin_lock(&timebase_lock);
  149. set_tb(timebase >> 32, timebase & 0xffffffff);
  150. timebase = 0;
  151. spin_unlock(&timebase_lock);
  152. }
  153. static void __devinit smp_pSeries_kick_cpu(int nr)
  154. {
  155. BUG_ON(nr < 0 || nr >= NR_CPUS);
  156. if (!smp_startup_cpu(nr))
  157. return;
  158. /*
  159. * The processor is currently spinning, waiting for the
  160. * cpu_start field to become non-zero After we set cpu_start,
  161. * the processor will continue on to secondary_start
  162. */
  163. paca[nr].cpu_start = 1;
  164. }
  165. static int smp_pSeries_cpu_bootable(unsigned int nr)
  166. {
  167. /* Special case - we inhibit secondary thread startup
  168. * during boot if the user requests it. Odd-numbered
  169. * cpus are assumed to be secondary threads.
  170. */
  171. if (system_state < SYSTEM_RUNNING &&
  172. cpu_has_feature(CPU_FTR_SMT) &&
  173. !smt_enabled_at_boot && nr % 2 != 0)
  174. return 0;
  175. return 1;
  176. }
  177. #ifdef CONFIG_MPIC
  178. static struct smp_ops_t pSeries_mpic_smp_ops = {
  179. .message_pass = smp_mpic_message_pass,
  180. .probe = smp_mpic_probe,
  181. .kick_cpu = smp_pSeries_kick_cpu,
  182. .setup_cpu = smp_mpic_setup_cpu,
  183. };
  184. #endif
  185. #ifdef CONFIG_XICS
  186. static struct smp_ops_t pSeries_xics_smp_ops = {
  187. .message_pass = smp_xics_message_pass,
  188. .probe = smp_xics_probe,
  189. .kick_cpu = smp_pSeries_kick_cpu,
  190. .setup_cpu = smp_xics_setup_cpu,
  191. .cpu_bootable = smp_pSeries_cpu_bootable,
  192. };
  193. #endif
  194. /* This is called very early */
  195. static void __init smp_init_pseries(void)
  196. {
  197. int i;
  198. DBG(" -> smp_init_pSeries()\n");
  199. /* Mark threads which are still spinning in hold loops. */
  200. if (cpu_has_feature(CPU_FTR_SMT)) {
  201. for_each_present_cpu(i) {
  202. if (i % 2 == 0)
  203. /*
  204. * Even-numbered logical cpus correspond to
  205. * primary threads.
  206. */
  207. cpu_set(i, of_spin_map);
  208. }
  209. } else {
  210. of_spin_map = cpu_present_map;
  211. }
  212. cpu_clear(boot_cpuid, of_spin_map);
  213. /* Non-lpar has additional take/give timebase */
  214. if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
  215. smp_ops->give_timebase = pSeries_give_timebase;
  216. smp_ops->take_timebase = pSeries_take_timebase;
  217. }
  218. DBG(" <- smp_init_pSeries()\n");
  219. }
  220. #ifdef CONFIG_MPIC
  221. void __init smp_init_pseries_mpic(void)
  222. {
  223. smp_ops = &pSeries_mpic_smp_ops;
  224. smp_init_pseries();
  225. }
  226. #endif
  227. void __init smp_init_pseries_xics(void)
  228. {
  229. smp_ops = &pSeries_xics_smp_ops;
  230. smp_init_pseries();
  231. }