pci.c 4.7 KB

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  1. /*
  2. * Copyright (C) 2006 PA Semi, Inc
  3. *
  4. * Authors: Kip Walker, PA Semi
  5. * Olof Johansson, PA Semi
  6. *
  7. * Maintained by: Olof Johansson <olof@lixom.net>
  8. *
  9. * Based on arch/powerpc/platforms/maple/pci.c
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/pci.h>
  26. #include <asm/pci-bridge.h>
  27. #include <asm/machdep.h>
  28. #include <asm/ppc-pci.h>
  29. #define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
  30. #define CONFIG_OFFSET_VALID(off) ((off) < 4096)
  31. static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose,
  32. u8 bus, u8 devfn, int offset)
  33. {
  34. return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset);
  35. }
  36. static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
  37. int offset, int len, u32 *val)
  38. {
  39. struct pci_controller *hose;
  40. void volatile __iomem *addr;
  41. hose = pci_bus_to_host(bus);
  42. if (!hose)
  43. return PCIBIOS_DEVICE_NOT_FOUND;
  44. if (!CONFIG_OFFSET_VALID(offset))
  45. return PCIBIOS_BAD_REGISTER_NUMBER;
  46. addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
  47. /*
  48. * Note: the caller has already checked that offset is
  49. * suitably aligned and that len is 1, 2 or 4.
  50. */
  51. switch (len) {
  52. case 1:
  53. *val = in_8(addr);
  54. break;
  55. case 2:
  56. *val = in_le16(addr);
  57. break;
  58. default:
  59. *val = in_le32(addr);
  60. break;
  61. }
  62. return PCIBIOS_SUCCESSFUL;
  63. }
  64. static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
  65. int offset, int len, u32 val)
  66. {
  67. struct pci_controller *hose;
  68. void volatile __iomem *addr;
  69. hose = pci_bus_to_host(bus);
  70. if (!hose)
  71. return PCIBIOS_DEVICE_NOT_FOUND;
  72. if (!CONFIG_OFFSET_VALID(offset))
  73. return PCIBIOS_BAD_REGISTER_NUMBER;
  74. addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
  75. /*
  76. * Note: the caller has already checked that offset is
  77. * suitably aligned and that len is 1, 2 or 4.
  78. */
  79. switch (len) {
  80. case 1:
  81. out_8(addr, val);
  82. (void) in_8(addr);
  83. break;
  84. case 2:
  85. out_le16(addr, val);
  86. (void) in_le16(addr);
  87. break;
  88. default:
  89. out_le32(addr, val);
  90. (void) in_le32(addr);
  91. break;
  92. }
  93. return PCIBIOS_SUCCESSFUL;
  94. }
  95. static struct pci_ops pa_pxp_ops = {
  96. pa_pxp_read_config,
  97. pa_pxp_write_config,
  98. };
  99. static void __init setup_pa_pxp(struct pci_controller *hose)
  100. {
  101. hose->ops = &pa_pxp_ops;
  102. hose->cfg_data = ioremap(0xe0000000, 0x10000000);
  103. }
  104. static int __init add_bridge(struct device_node *dev)
  105. {
  106. struct pci_controller *hose;
  107. pr_debug("Adding PCI host bridge %s\n", dev->full_name);
  108. hose = pcibios_alloc_controller(dev);
  109. if (!hose)
  110. return -ENOMEM;
  111. hose->first_busno = 0;
  112. hose->last_busno = 0xff;
  113. setup_pa_pxp(hose);
  114. printk(KERN_INFO "Found PA-PXP PCI host bridge.\n");
  115. /* Interpret the "ranges" property */
  116. /* This also maps the I/O region and sets isa_io/mem_base */
  117. pci_process_bridge_OF_ranges(hose, dev, 1);
  118. pci_setup_phb_io(hose, 1);
  119. return 0;
  120. }
  121. static void __init pas_fixup_phb_resources(void)
  122. {
  123. struct pci_controller *hose, *tmp;
  124. list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
  125. unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
  126. hose->io_resource.start += offset;
  127. hose->io_resource.end += offset;
  128. printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
  129. hose->global_number,
  130. hose->io_resource.start, hose->io_resource.end);
  131. }
  132. }
  133. void __devinit pas_pci_irq_fixup(struct pci_dev *dev)
  134. {
  135. /* DMA is special, 84 interrupts (128 -> 211), all but 128
  136. * need to be mapped by hand here.
  137. */
  138. if (dev->vendor == 0x1959 && dev->device == 0xa007) {
  139. int i;
  140. for (i = 129; i < 212; i++)
  141. irq_create_mapping(NULL, i);
  142. }
  143. }
  144. void __init pas_pci_init(void)
  145. {
  146. struct device_node *np, *root;
  147. root = of_find_node_by_path("/");
  148. if (!root) {
  149. printk(KERN_CRIT "pas_pci_init: can't find root "
  150. "of device tree\n");
  151. return;
  152. }
  153. for (np = NULL; (np = of_get_next_child(root, np)) != NULL;)
  154. if (np->name && !strcmp(np->name, "pxp") && !add_bridge(np))
  155. of_node_get(np);
  156. of_node_put(root);
  157. pas_fixup_phb_resources();
  158. /* Setup the linkage between OF nodes and PHBs */
  159. pci_devs_phb_init();
  160. /* Use the common resource allocation mechanism */
  161. pci_probe_only = 1;
  162. }