mpc832x_mds.c 4.9 KB

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  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Description:
  5. * MPC832xE MDS board specific routines.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. #include <linux/stddef.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/errno.h>
  16. #include <linux/reboot.h>
  17. #include <linux/pci.h>
  18. #include <linux/kdev_t.h>
  19. #include <linux/major.h>
  20. #include <linux/console.h>
  21. #include <linux/delay.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/root_dev.h>
  24. #include <linux/initrd.h>
  25. #include <asm/of_device.h>
  26. #include <asm/of_platform.h>
  27. #include <asm/system.h>
  28. #include <asm/atomic.h>
  29. #include <asm/time.h>
  30. #include <asm/io.h>
  31. #include <asm/machdep.h>
  32. #include <asm/ipic.h>
  33. #include <asm/bootinfo.h>
  34. #include <asm/irq.h>
  35. #include <asm/prom.h>
  36. #include <asm/udbg.h>
  37. #include <sysdev/fsl_soc.h>
  38. #include <asm/qe.h>
  39. #include <asm/qe_ic.h>
  40. #include "mpc83xx.h"
  41. #include "mpc832x_mds.h"
  42. #undef DEBUG
  43. #ifdef DEBUG
  44. #define DBG(fmt...) udbg_printf(fmt)
  45. #else
  46. #define DBG(fmt...)
  47. #endif
  48. #ifndef CONFIG_PCI
  49. unsigned long isa_io_base = 0;
  50. unsigned long isa_mem_base = 0;
  51. #endif
  52. static u8 *bcsr_regs = NULL;
  53. u8 *get_bcsr(void)
  54. {
  55. return bcsr_regs;
  56. }
  57. /* ************************************************************************
  58. *
  59. * Setup the architecture
  60. *
  61. */
  62. static void __init mpc832x_sys_setup_arch(void)
  63. {
  64. struct device_node *np;
  65. if (ppc_md.progress)
  66. ppc_md.progress("mpc832x_sys_setup_arch()", 0);
  67. np = of_find_node_by_type(NULL, "cpu");
  68. if (np != 0) {
  69. unsigned int *fp =
  70. (int *)get_property(np, "clock-frequency", NULL);
  71. if (fp != 0)
  72. loops_per_jiffy = *fp / HZ;
  73. else
  74. loops_per_jiffy = 50000000 / HZ;
  75. of_node_put(np);
  76. }
  77. /* Map BCSR area */
  78. np = of_find_node_by_name(NULL, "bcsr");
  79. if (np != 0) {
  80. struct resource res;
  81. of_address_to_resource(np, 0, &res);
  82. bcsr_regs = ioremap(res.start, res.end - res.start +1);
  83. of_node_put(np);
  84. }
  85. #ifdef CONFIG_PCI
  86. for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
  87. add_bridge(np);
  88. ppc_md.pci_exclude_device = mpc83xx_exclude_device;
  89. #endif
  90. #ifdef CONFIG_QUICC_ENGINE
  91. qe_reset();
  92. if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  93. par_io_init(np);
  94. of_node_put(np);
  95. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  96. par_io_of_config(np);
  97. }
  98. if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  99. != NULL){
  100. /* Reset the Ethernet PHY */
  101. bcsr_regs[9] &= ~0x20;
  102. udelay(1000);
  103. bcsr_regs[9] |= 0x20;
  104. iounmap(bcsr_regs);
  105. of_node_put(np);
  106. }
  107. #endif /* CONFIG_QUICC_ENGINE */
  108. #ifdef CONFIG_BLK_DEV_INITRD
  109. if (initrd_start)
  110. ROOT_DEV = Root_RAM0;
  111. else
  112. #endif
  113. #ifdef CONFIG_ROOT_NFS
  114. ROOT_DEV = Root_NFS;
  115. #else
  116. ROOT_DEV = Root_HDA1;
  117. #endif
  118. }
  119. static int __init mpc832x_declare_of_platform_devices(void)
  120. {
  121. struct device_node *np;
  122. for (np = NULL; (np = of_find_compatible_node(np, "network",
  123. "ucc_geth")) != NULL;) {
  124. int ucc_num;
  125. char bus_id[BUS_ID_SIZE];
  126. ucc_num = *((uint *) get_property(np, "device-id", NULL)) - 1;
  127. snprintf(bus_id, BUS_ID_SIZE, "ucc_geth.%u", ucc_num);
  128. of_platform_device_create(np, bus_id, NULL);
  129. }
  130. return 0;
  131. }
  132. device_initcall(mpc832x_declare_of_platform_devices);
  133. static void __init mpc832x_sys_init_IRQ(void)
  134. {
  135. struct device_node *np;
  136. np = of_find_node_by_type(NULL, "ipic");
  137. if (!np)
  138. return;
  139. ipic_init(np, 0);
  140. /* Initialize the default interrupt mapping priorities,
  141. * in case the boot rom changed something on us.
  142. */
  143. ipic_set_default_priority();
  144. of_node_put(np);
  145. #ifdef CONFIG_QUICC_ENGINE
  146. np = of_find_node_by_type(NULL, "qeic");
  147. if (!np)
  148. return;
  149. qe_ic_init(np, 0);
  150. of_node_put(np);
  151. #endif /* CONFIG_QUICC_ENGINE */
  152. }
  153. #if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
  154. extern ulong ds1374_get_rtc_time(void);
  155. extern int ds1374_set_rtc_time(ulong);
  156. static int __init mpc832x_rtc_hookup(void)
  157. {
  158. struct timespec tv;
  159. ppc_md.get_rtc_time = ds1374_get_rtc_time;
  160. ppc_md.set_rtc_time = ds1374_set_rtc_time;
  161. tv.tv_nsec = 0;
  162. tv.tv_sec = (ppc_md.get_rtc_time) ();
  163. do_settimeofday(&tv);
  164. return 0;
  165. }
  166. late_initcall(mpc832x_rtc_hookup);
  167. #endif
  168. /*
  169. * Called very early, MMU is off, device-tree isn't unflattened
  170. */
  171. static int __init mpc832x_sys_probe(void)
  172. {
  173. char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
  174. "model", NULL);
  175. if (model == NULL)
  176. return 0;
  177. if (strcmp(model, "MPC8323EMDS"))
  178. return 0;
  179. DBG("%s found\n", model);
  180. return 1;
  181. }
  182. define_machine(mpc832x_mds) {
  183. .name = "MPC832x MDS",
  184. .probe = mpc832x_sys_probe,
  185. .setup_arch = mpc832x_sys_setup_arch,
  186. .init_IRQ = mpc832x_sys_init_IRQ,
  187. .get_irq = ipic_get_irq,
  188. .restart = mpc83xx_restart,
  189. .time_init = mpc83xx_time_init,
  190. .calibrate_decr = generic_calibrate_decr,
  191. .progress = udbg_progress,
  192. };