mpc8548cds.dts 6.5 KB

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  1. /*
  2. * MPC8555 CDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8548CDS";
  13. compatible = "MPC85xxCDS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. linux,phandle = <100>;
  17. cpus {
  18. #cpus = <1>;
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. linux,phandle = <200>;
  22. PowerPC,8548@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. d-cache-line-size = <20>; // 32 bytes
  26. i-cache-line-size = <20>; // 32 bytes
  27. d-cache-size = <8000>; // L1, 32K
  28. i-cache-size = <8000>; // L1, 32K
  29. timebase-frequency = <0>; // 33 MHz, from uboot
  30. bus-frequency = <0>; // 166 MHz
  31. clock-frequency = <0>; // 825 MHz, from uboot
  32. 32-bit;
  33. linux,phandle = <201>;
  34. };
  35. };
  36. memory {
  37. device_type = "memory";
  38. linux,phandle = <300>;
  39. reg = <00000000 08000000>; // 128M at 0x0
  40. };
  41. soc8548@e0000000 {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. #interrupt-cells = <2>;
  45. device_type = "soc";
  46. ranges = <0 e0000000 00100000>;
  47. reg = <e0000000 00100000>; // CCSRBAR 1M
  48. bus-frequency = <0>;
  49. i2c@3000 {
  50. device_type = "i2c";
  51. compatible = "fsl-i2c";
  52. reg = <3000 100>;
  53. interrupts = <1b 2>;
  54. interrupt-parent = <40000>;
  55. dfsrr;
  56. };
  57. mdio@24520 {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. device_type = "mdio";
  61. compatible = "gianfar";
  62. reg = <24520 20>;
  63. linux,phandle = <24520>;
  64. ethernet-phy@0 {
  65. linux,phandle = <2452000>;
  66. interrupt-parent = <40000>;
  67. interrupts = <35 0>;
  68. reg = <0>;
  69. device_type = "ethernet-phy";
  70. };
  71. ethernet-phy@1 {
  72. linux,phandle = <2452001>;
  73. interrupt-parent = <40000>;
  74. interrupts = <35 0>;
  75. reg = <1>;
  76. device_type = "ethernet-phy";
  77. };
  78. ethernet-phy@2 {
  79. linux,phandle = <2452002>;
  80. interrupt-parent = <40000>;
  81. interrupts = <35 0>;
  82. reg = <2>;
  83. device_type = "ethernet-phy";
  84. };
  85. ethernet-phy@3 {
  86. linux,phandle = <2452003>;
  87. interrupt-parent = <40000>;
  88. interrupts = <35 0>;
  89. reg = <3>;
  90. device_type = "ethernet-phy";
  91. };
  92. };
  93. ethernet@24000 {
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96. device_type = "network";
  97. model = "eTSEC";
  98. compatible = "gianfar";
  99. reg = <24000 1000>;
  100. local-mac-address = [ 00 E0 0C 00 73 00 ];
  101. interrupts = <d 2 e 2 12 2>;
  102. interrupt-parent = <40000>;
  103. phy-handle = <2452000>;
  104. };
  105. ethernet@25000 {
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. device_type = "network";
  109. model = "eTSEC";
  110. compatible = "gianfar";
  111. reg = <25000 1000>;
  112. local-mac-address = [ 00 E0 0C 00 73 01 ];
  113. interrupts = <13 2 14 2 18 2>;
  114. interrupt-parent = <40000>;
  115. phy-handle = <2452001>;
  116. };
  117. ethernet@26000 {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. device_type = "network";
  121. model = "eTSEC";
  122. compatible = "gianfar";
  123. reg = <26000 1000>;
  124. local-mac-address = [ 00 E0 0C 00 73 02 ];
  125. interrupts = <f 2 10 2 11 2>;
  126. interrupt-parent = <40000>;
  127. phy-handle = <2452001>;
  128. };
  129. /* eTSEC 4 is currently broken
  130. ethernet@27000 {
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. device_type = "network";
  134. model = "eTSEC";
  135. compatible = "gianfar";
  136. reg = <27000 1000>;
  137. local-mac-address = [ 00 E0 0C 00 73 03 ];
  138. interrupts = <15 2 16 2 17 2>;
  139. interrupt-parent = <40000>;
  140. phy-handle = <2452001>;
  141. };
  142. */
  143. serial@4500 {
  144. device_type = "serial";
  145. compatible = "ns16550";
  146. reg = <4500 100>; // reg base, size
  147. clock-frequency = <0>; // should we fill in in uboot?
  148. interrupts = <1a 2>;
  149. interrupt-parent = <40000>;
  150. };
  151. serial@4600 {
  152. device_type = "serial";
  153. compatible = "ns16550";
  154. reg = <4600 100>; // reg base, size
  155. clock-frequency = <0>; // should we fill in in uboot?
  156. interrupts = <1a 2>;
  157. interrupt-parent = <40000>;
  158. };
  159. pci@8000 {
  160. linux,phandle = <8000>;
  161. interrupt-map-mask = <1f800 0 0 7>;
  162. interrupt-map = <
  163. /* IDSEL 0x10 */
  164. 08000 0 0 1 40000 30 1
  165. 08000 0 0 2 40000 31 1
  166. 08000 0 0 3 40000 32 1
  167. 08000 0 0 4 40000 33 1
  168. /* IDSEL 0x11 */
  169. 08800 0 0 1 40000 30 1
  170. 08800 0 0 2 40000 31 1
  171. 08800 0 0 3 40000 32 1
  172. 08800 0 0 4 40000 33 1
  173. /* IDSEL 0x12 (Slot 1) */
  174. 09000 0 0 1 40000 30 1
  175. 09000 0 0 2 40000 31 1
  176. 09000 0 0 3 40000 32 1
  177. 09000 0 0 4 40000 33 1
  178. /* IDSEL 0x13 (Slot 2) */
  179. 09800 0 0 1 40000 31 1
  180. 09800 0 0 2 40000 32 1
  181. 09800 0 0 3 40000 33 1
  182. 09800 0 0 4 40000 30 1
  183. /* IDSEL 0x14 (Slot 3) */
  184. 0a000 0 0 1 40000 32 1
  185. 0a000 0 0 2 40000 33 1
  186. 0a000 0 0 3 40000 30 1
  187. 0a000 0 0 4 40000 31 1
  188. /* IDSEL 0x15 (Slot 4) */
  189. 0a800 0 0 1 40000 33 1
  190. 0a800 0 0 2 40000 30 1
  191. 0a800 0 0 3 40000 31 1
  192. 0a800 0 0 4 40000 32 1
  193. /* Bus 1 (Tundra Bridge) */
  194. /* IDSEL 0x12 (ISA bridge) */
  195. 19000 0 0 1 40000 30 1
  196. 19000 0 0 2 40000 31 1
  197. 19000 0 0 3 40000 32 1
  198. 19000 0 0 4 40000 33 1>;
  199. interrupt-parent = <40000>;
  200. interrupts = <08 2>;
  201. bus-range = <0 0>;
  202. ranges = <02000000 0 80000000 80000000 0 20000000
  203. 01000000 0 00000000 e2000000 0 00100000>;
  204. clock-frequency = <3f940aa>;
  205. #interrupt-cells = <1>;
  206. #size-cells = <2>;
  207. #address-cells = <3>;
  208. reg = <8000 1000>;
  209. compatible = "85xx";
  210. device_type = "pci";
  211. i8259@19000 {
  212. clock-frequency = <0>;
  213. interrupt-controller;
  214. device_type = "interrupt-controller";
  215. reg = <19000 0 0 0 1>;
  216. #address-cells = <0>;
  217. #interrupt-cells = <2>;
  218. built-in;
  219. compatible = "chrp,iic";
  220. big-endian;
  221. interrupts = <1>;
  222. interrupt-parent = <8000>;
  223. };
  224. };
  225. pci@9000 {
  226. linux,phandle = <9000>;
  227. interrupt-map-mask = <f800 0 0 7>;
  228. interrupt-map = <
  229. /* IDSEL 0x15 */
  230. a800 0 0 1 40000 3b 1
  231. a800 0 0 2 40000 3b 1
  232. a800 0 0 3 40000 3b 1
  233. a800 0 0 4 40000 3b 1>;
  234. interrupt-parent = <40000>;
  235. interrupts = <09 2>;
  236. bus-range = <0 0>;
  237. ranges = <02000000 0 a0000000 a0000000 0 20000000
  238. 01000000 0 00000000 e3000000 0 00100000>;
  239. clock-frequency = <3f940aa>;
  240. #interrupt-cells = <1>;
  241. #size-cells = <2>;
  242. #address-cells = <3>;
  243. reg = <9000 1000>;
  244. compatible = "85xx";
  245. device_type = "pci";
  246. };
  247. pic@40000 {
  248. linux,phandle = <40000>;
  249. clock-frequency = <0>;
  250. interrupt-controller;
  251. #address-cells = <0>;
  252. #interrupt-cells = <2>;
  253. reg = <40000 40000>;
  254. built-in;
  255. compatible = "chrp,open-pic";
  256. device_type = "open-pic";
  257. big-endian;
  258. };
  259. };
  260. };