mpc8360emds.dts 8.2 KB

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  1. /*
  2. * MPC8360E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /*
  12. /memreserve/ 00000000 1000000;
  13. */
  14. / {
  15. model = "MPC8360EPB";
  16. compatible = "MPC83xx";
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. linux,phandle = <100>;
  20. cpus {
  21. #cpus = <1>;
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. linux,phandle = <200>;
  25. PowerPC,8360@0 {
  26. device_type = "cpu";
  27. reg = <0>;
  28. d-cache-line-size = <20>; // 32 bytes
  29. i-cache-line-size = <20>; // 32 bytes
  30. d-cache-size = <8000>; // L1, 32K
  31. i-cache-size = <8000>; // L1, 32K
  32. timebase-frequency = <3EF1480>;
  33. bus-frequency = <FBC5200>;
  34. clock-frequency = <1F78A400>;
  35. 32-bit;
  36. linux,phandle = <201>;
  37. linux,boot-cpu;
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. linux,phandle = <300>;
  43. reg = <00000000 10000000>;
  44. };
  45. bcsr@f8000000 {
  46. device_type = "board-control";
  47. reg = <f8000000 8000>;
  48. };
  49. soc8360@e0000000 {
  50. #address-cells = <1>;
  51. #size-cells = <1>;
  52. #interrupt-cells = <2>;
  53. device_type = "soc";
  54. ranges = <0 e0000000 00100000>;
  55. reg = <e0000000 00000200>;
  56. bus-frequency = <FBC5200>;
  57. wdt@200 {
  58. device_type = "watchdog";
  59. compatible = "mpc83xx_wdt";
  60. reg = <200 100>;
  61. };
  62. i2c@3000 {
  63. device_type = "i2c";
  64. compatible = "fsl-i2c";
  65. reg = <3000 100>;
  66. interrupts = <e 8>;
  67. interrupt-parent = <700>;
  68. dfsrr;
  69. };
  70. i2c@3100 {
  71. device_type = "i2c";
  72. compatible = "fsl-i2c";
  73. reg = <3100 100>;
  74. interrupts = <f 8>;
  75. interrupt-parent = <700>;
  76. dfsrr;
  77. };
  78. serial@4500 {
  79. device_type = "serial";
  80. compatible = "ns16550";
  81. reg = <4500 100>;
  82. clock-frequency = <FBC5200>;
  83. interrupts = <9 8>;
  84. interrupt-parent = <700>;
  85. };
  86. serial@4600 {
  87. device_type = "serial";
  88. compatible = "ns16550";
  89. reg = <4600 100>;
  90. clock-frequency = <FBC5200>;
  91. interrupts = <a 8>;
  92. interrupt-parent = <700>;
  93. };
  94. crypto@30000 {
  95. device_type = "crypto";
  96. model = "SEC2";
  97. compatible = "talitos";
  98. reg = <30000 10000>;
  99. interrupts = <b 8>;
  100. interrupt-parent = <700>;
  101. num-channels = <4>;
  102. channel-fifo-len = <18>;
  103. exec-units-mask = <0000007e>;
  104. /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
  105. descriptor-types-mask = <01010ebf>;
  106. };
  107. pci@8500 {
  108. linux,phandle = <8500>;
  109. interrupt-map-mask = <f800 0 0 7>;
  110. interrupt-map = <
  111. /* IDSEL 0x11 AD17 */
  112. 8800 0 0 1 700 14 8
  113. 8800 0 0 2 700 15 8
  114. 8800 0 0 3 700 16 8
  115. 8800 0 0 4 700 17 8
  116. /* IDSEL 0x12 AD18 */
  117. 9000 0 0 1 700 16 8
  118. 9000 0 0 2 700 17 8
  119. 9000 0 0 3 700 14 8
  120. 9000 0 0 4 700 15 8
  121. /* IDSEL 0x13 AD19 */
  122. 9800 0 0 1 700 17 8
  123. 9800 0 0 2 700 14 8
  124. 9800 0 0 3 700 15 8
  125. 9800 0 0 4 700 16 8
  126. /* IDSEL 0x15 AD21*/
  127. a800 0 0 1 700 14 8
  128. a800 0 0 2 700 15 8
  129. a800 0 0 3 700 16 8
  130. a800 0 0 4 700 17 8
  131. /* IDSEL 0x16 AD22*/
  132. b000 0 0 1 700 17 8
  133. b000 0 0 2 700 14 8
  134. b000 0 0 3 700 15 8
  135. b000 0 0 4 700 16 8
  136. /* IDSEL 0x17 AD23*/
  137. b800 0 0 1 700 16 8
  138. b800 0 0 2 700 17 8
  139. b800 0 0 3 700 14 8
  140. b800 0 0 4 700 15 8
  141. /* IDSEL 0x18 AD24*/
  142. c000 0 0 1 700 15 8
  143. c000 0 0 2 700 16 8
  144. c000 0 0 3 700 17 8
  145. c000 0 0 4 700 14 8>;
  146. interrupt-parent = <700>;
  147. interrupts = <42 8>;
  148. bus-range = <0 0>;
  149. ranges = <02000000 0 a0000000 a0000000 0 10000000
  150. 42000000 0 80000000 80000000 0 10000000
  151. 01000000 0 00000000 e2000000 0 00100000>;
  152. clock-frequency = <3f940aa>;
  153. #interrupt-cells = <1>;
  154. #size-cells = <2>;
  155. #address-cells = <3>;
  156. reg = <8500 100>;
  157. compatible = "83xx";
  158. device_type = "pci";
  159. };
  160. pic@700 {
  161. linux,phandle = <700>;
  162. interrupt-controller;
  163. #address-cells = <0>;
  164. #interrupt-cells = <2>;
  165. reg = <700 100>;
  166. built-in;
  167. device_type = "ipic";
  168. };
  169. par_io@1400 {
  170. reg = <1400 100>;
  171. device_type = "par_io";
  172. num-ports = <7>;
  173. ucc_pin@01 {
  174. linux,phandle = <140001>;
  175. pio-map = <
  176. /* port pin dir open_drain assignment has_irq */
  177. 0 3 1 0 1 0 /* TxD0 */
  178. 0 4 1 0 1 0 /* TxD1 */
  179. 0 5 1 0 1 0 /* TxD2 */
  180. 0 6 1 0 1 0 /* TxD3 */
  181. 1 6 1 0 3 0 /* TxD4 */
  182. 1 7 1 0 1 0 /* TxD5 */
  183. 1 9 1 0 2 0 /* TxD6 */
  184. 1 a 1 0 2 0 /* TxD7 */
  185. 0 9 2 0 1 0 /* RxD0 */
  186. 0 a 2 0 1 0 /* RxD1 */
  187. 0 b 2 0 1 0 /* RxD2 */
  188. 0 c 2 0 1 0 /* RxD3 */
  189. 0 d 2 0 1 0 /* RxD4 */
  190. 1 1 2 0 2 0 /* RxD5 */
  191. 1 0 2 0 2 0 /* RxD6 */
  192. 1 4 2 0 2 0 /* RxD7 */
  193. 0 7 1 0 1 0 /* TX_EN */
  194. 0 8 1 0 1 0 /* TX_ER */
  195. 0 f 2 0 1 0 /* RX_DV */
  196. 0 10 2 0 1 0 /* RX_ER */
  197. 0 0 2 0 1 0 /* RX_CLK */
  198. 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
  199. 2 8 2 0 1 0>; /* GTX125 - CLK9 */
  200. };
  201. ucc_pin@02 {
  202. linux,phandle = <140002>;
  203. pio-map = <
  204. /* port pin dir open_drain assignment has_irq */
  205. 0 11 1 0 1 0 /* TxD0 */
  206. 0 12 1 0 1 0 /* TxD1 */
  207. 0 13 1 0 1 0 /* TxD2 */
  208. 0 14 1 0 1 0 /* TxD3 */
  209. 1 2 1 0 1 0 /* TxD4 */
  210. 1 3 1 0 2 0 /* TxD5 */
  211. 1 5 1 0 3 0 /* TxD6 */
  212. 1 8 1 0 3 0 /* TxD7 */
  213. 0 17 2 0 1 0 /* RxD0 */
  214. 0 18 2 0 1 0 /* RxD1 */
  215. 0 19 2 0 1 0 /* RxD2 */
  216. 0 1a 2 0 1 0 /* RxD3 */
  217. 0 1b 2 0 1 0 /* RxD4 */
  218. 1 c 2 0 2 0 /* RxD5 */
  219. 1 d 2 0 3 0 /* RxD6 */
  220. 1 b 2 0 2 0 /* RxD7 */
  221. 0 15 1 0 1 0 /* TX_EN */
  222. 0 16 1 0 1 0 /* TX_ER */
  223. 0 1d 2 0 1 0 /* RX_DV */
  224. 0 1e 2 0 1 0 /* RX_ER */
  225. 0 1f 2 0 1 0 /* RX_CLK */
  226. 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
  227. 2 3 2 0 1 0 /* GTX125 - CLK4 */
  228. 0 1 3 0 2 0 /* MDIO */
  229. 0 2 1 0 1 0>; /* MDC */
  230. };
  231. };
  232. };
  233. qe@e0100000 {
  234. #address-cells = <1>;
  235. #size-cells = <1>;
  236. device_type = "qe";
  237. model = "QE";
  238. ranges = <0 e0100000 00100000>;
  239. reg = <e0100000 480>;
  240. brg-frequency = <0>;
  241. bus-frequency = <179A7B00>;
  242. muram@10000 {
  243. device_type = "muram";
  244. ranges = <0 00010000 0000c000>;
  245. data-only@0{
  246. reg = <0 c000>;
  247. };
  248. };
  249. spi@4c0 {
  250. device_type = "spi";
  251. compatible = "fsl_spi";
  252. reg = <4c0 40>;
  253. interrupts = <2>;
  254. interrupt-parent = <80>;
  255. mode = "cpu";
  256. };
  257. spi@500 {
  258. device_type = "spi";
  259. compatible = "fsl_spi";
  260. reg = <500 40>;
  261. interrupts = <1>;
  262. interrupt-parent = <80>;
  263. mode = "cpu";
  264. };
  265. usb@6c0 {
  266. device_type = "usb";
  267. compatible = "qe_udc";
  268. reg = <6c0 40 8B00 100>;
  269. interrupts = <b>;
  270. interrupt-parent = <80>;
  271. mode = "slave";
  272. };
  273. ucc@2000 {
  274. device_type = "network";
  275. compatible = "ucc_geth";
  276. model = "UCC";
  277. device-id = <1>;
  278. reg = <2000 200>;
  279. interrupts = <20>;
  280. interrupt-parent = <80>;
  281. mac-address = [ 00 04 9f 00 23 23 ];
  282. rx-clock = <0>;
  283. tx-clock = <19>;
  284. phy-handle = <212000>;
  285. pio-handle = <140001>;
  286. };
  287. ucc@3000 {
  288. device_type = "network";
  289. compatible = "ucc_geth";
  290. model = "UCC";
  291. device-id = <2>;
  292. reg = <3000 200>;
  293. interrupts = <21>;
  294. interrupt-parent = <80>;
  295. mac-address = [ 00 11 22 33 44 55 ];
  296. rx-clock = <0>;
  297. tx-clock = <14>;
  298. phy-handle = <212001>;
  299. pio-handle = <140002>;
  300. };
  301. mdio@2120 {
  302. #address-cells = <1>;
  303. #size-cells = <0>;
  304. reg = <2120 18>;
  305. device_type = "mdio";
  306. compatible = "ucc_geth_phy";
  307. ethernet-phy@00 {
  308. linux,phandle = <212000>;
  309. interrupt-parent = <700>;
  310. interrupts = <11 2>;
  311. reg = <0>;
  312. device_type = "ethernet-phy";
  313. interface = <6>; //ENET_1000_GMII
  314. };
  315. ethernet-phy@01 {
  316. linux,phandle = <212001>;
  317. interrupt-parent = <700>;
  318. interrupts = <12 2>;
  319. reg = <1>;
  320. device_type = "ethernet-phy";
  321. interface = <6>;
  322. };
  323. };
  324. qeic@80 {
  325. linux,phandle = <80>;
  326. interrupt-controller;
  327. device_type = "qeic";
  328. #address-cells = <0>;
  329. #interrupt-cells = <1>;
  330. reg = <80 80>;
  331. built-in;
  332. big-endian;
  333. interrupts = <20 8 21 8>; //high:32 low:33
  334. interrupt-parent = <700>;
  335. };
  336. };
  337. };