mpc8323emds.dts 7.5 KB

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  1. /*
  2. * MPC8323E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8323EMDS";
  13. compatible = "MPC83xx";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. linux,phandle = <100>;
  17. cpus {
  18. #cpus = <1>;
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. linux,phandle = <200>;
  22. PowerPC,8323@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. d-cache-line-size = <20>; // 32 bytes
  26. i-cache-line-size = <20>; // 32 bytes
  27. d-cache-size = <4000>; // L1, 16K
  28. i-cache-size = <4000>; // L1, 16K
  29. timebase-frequency = <0>;
  30. bus-frequency = <0>;
  31. clock-frequency = <0>;
  32. 32-bit;
  33. linux,phandle = <201>;
  34. linux,boot-cpu;
  35. };
  36. };
  37. memory {
  38. device_type = "memory";
  39. linux,phandle = <300>;
  40. reg = <00000000 08000000>;
  41. };
  42. bcsr@f8000000 {
  43. device_type = "board-control";
  44. reg = <f8000000 8000>;
  45. };
  46. soc8323@e0000000 {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. #interrupt-cells = <2>;
  50. device_type = "soc";
  51. ranges = <0 e0000000 00100000>;
  52. reg = <e0000000 00000200>;
  53. bus-frequency = <7DE2900>;
  54. wdt@200 {
  55. device_type = "watchdog";
  56. compatible = "mpc83xx_wdt";
  57. reg = <200 100>;
  58. };
  59. i2c@3000 {
  60. device_type = "i2c";
  61. compatible = "fsl-i2c";
  62. reg = <3000 100>;
  63. interrupts = <e 8>;
  64. interrupt-parent = <700>;
  65. dfsrr;
  66. };
  67. serial@4500 {
  68. device_type = "serial";
  69. compatible = "ns16550";
  70. reg = <4500 100>;
  71. clock-frequency = <0>;
  72. interrupts = <9 8>;
  73. interrupt-parent = <700>;
  74. };
  75. serial@4600 {
  76. device_type = "serial";
  77. compatible = "ns16550";
  78. reg = <4600 100>;
  79. clock-frequency = <0>;
  80. interrupts = <a 8>;
  81. interrupt-parent = <700>;
  82. };
  83. crypto@30000 {
  84. device_type = "crypto";
  85. model = "SEC2";
  86. compatible = "talitos";
  87. reg = <30000 7000>;
  88. interrupts = <b 8>;
  89. interrupt-parent = <700>;
  90. /* Rev. 2.2 */
  91. num-channels = <1>;
  92. channel-fifo-len = <18>;
  93. exec-units-mask = <0000004c>;
  94. descriptor-types-mask = <0122003f>;
  95. };
  96. pci@8500 {
  97. linux,phandle = <8500>;
  98. interrupt-map-mask = <f800 0 0 7>;
  99. interrupt-map = <
  100. /* IDSEL 0x11 AD17 */
  101. 8800 0 0 1 700 14 8
  102. 8800 0 0 2 700 15 8
  103. 8800 0 0 3 700 16 8
  104. 8800 0 0 4 700 17 8
  105. /* IDSEL 0x12 AD18 */
  106. 9000 0 0 1 700 16 8
  107. 9000 0 0 2 700 17 8
  108. 9000 0 0 3 700 14 8
  109. 9000 0 0 4 700 15 8
  110. /* IDSEL 0x13 AD19 */
  111. 9800 0 0 1 700 17 8
  112. 9800 0 0 2 700 14 8
  113. 9800 0 0 3 700 15 8
  114. 9800 0 0 4 700 16 8
  115. /* IDSEL 0x15 AD21*/
  116. a800 0 0 1 700 14 8
  117. a800 0 0 2 700 15 8
  118. a800 0 0 3 700 16 8
  119. a800 0 0 4 700 17 8
  120. /* IDSEL 0x16 AD22*/
  121. b000 0 0 1 700 17 8
  122. b000 0 0 2 700 14 8
  123. b000 0 0 3 700 15 8
  124. b000 0 0 4 700 16 8
  125. /* IDSEL 0x17 AD23*/
  126. b800 0 0 1 700 16 8
  127. b800 0 0 2 700 17 8
  128. b800 0 0 3 700 14 8
  129. b800 0 0 4 700 15 8
  130. /* IDSEL 0x18 AD24*/
  131. c000 0 0 1 700 15 8
  132. c000 0 0 2 700 16 8
  133. c000 0 0 3 700 17 8
  134. c000 0 0 4 700 14 8>;
  135. interrupt-parent = <700>;
  136. interrupts = <42 8>;
  137. bus-range = <0 0>;
  138. ranges = <02000000 0 a0000000 90000000 0 10000000
  139. 42000000 0 80000000 80000000 0 10000000
  140. 01000000 0 00000000 d0000000 0 00100000>;
  141. clock-frequency = <0>;
  142. #interrupt-cells = <1>;
  143. #size-cells = <2>;
  144. #address-cells = <3>;
  145. reg = <8500 100>;
  146. compatible = "83xx";
  147. device_type = "pci";
  148. };
  149. pic@700 {
  150. linux,phandle = <700>;
  151. interrupt-controller;
  152. #address-cells = <0>;
  153. #interrupt-cells = <2>;
  154. reg = <700 100>;
  155. built-in;
  156. device_type = "ipic";
  157. };
  158. par_io@1400 {
  159. reg = <1400 100>;
  160. device_type = "par_io";
  161. num-ports = <7>;
  162. ucc_pin@03 {
  163. linux,phandle = <140003>;
  164. pio-map = <
  165. /* port pin dir open_drain assignment has_irq */
  166. 3 4 3 0 2 0 /* MDIO */
  167. 3 5 1 0 2 0 /* MDC */
  168. 0 d 2 0 1 0 /* RX_CLK (CLK9) */
  169. 3 18 2 0 1 0 /* TX_CLK (CLK10) */
  170. 1 1 1 0 1 0 /* TxD1 */
  171. 1 0 1 0 1 0 /* TxD0 */
  172. 1 1 1 0 1 0 /* TxD1 */
  173. 1 2 1 0 1 0 /* TxD2 */
  174. 1 3 1 0 1 0 /* TxD3 */
  175. 1 4 2 0 1 0 /* RxD0 */
  176. 1 5 2 0 1 0 /* RxD1 */
  177. 1 6 2 0 1 0 /* RxD2 */
  178. 1 7 2 0 1 0 /* RxD3 */
  179. 1 8 2 0 1 0 /* RX_ER */
  180. 1 9 1 0 1 0 /* TX_ER */
  181. 1 a 2 0 1 0 /* RX_DV */
  182. 1 b 2 0 1 0 /* COL */
  183. 1 c 1 0 1 0 /* TX_EN */
  184. 1 d 2 0 1 0>;/* CRS */
  185. };
  186. ucc_pin@04 {
  187. linux,phandle = <140004>;
  188. pio-map = <
  189. /* port pin dir open_drain assignment has_irq */
  190. 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
  191. 3 6 2 0 1 0 /* TX_CLK (CLK8) */
  192. 1 12 1 0 1 0 /* TxD0 */
  193. 1 13 1 0 1 0 /* TxD1 */
  194. 1 14 1 0 1 0 /* TxD2 */
  195. 1 15 1 0 1 0 /* TxD3 */
  196. 1 16 2 0 1 0 /* RxD0 */
  197. 1 17 2 0 1 0 /* RxD1 */
  198. 1 18 2 0 1 0 /* RxD2 */
  199. 1 19 2 0 1 0 /* RxD3 */
  200. 1 1a 2 0 1 0 /* RX_ER */
  201. 1 1b 1 0 1 0 /* TX_ER */
  202. 1 1c 2 0 1 0 /* RX_DV */
  203. 1 1d 2 0 1 0 /* COL */
  204. 1 1e 1 0 1 0 /* TX_EN */
  205. 1 1f 2 0 1 0>;/* CRS */
  206. };
  207. };
  208. };
  209. qe@e0100000 {
  210. #address-cells = <1>;
  211. #size-cells = <1>;
  212. device_type = "qe";
  213. model = "QE";
  214. ranges = <0 e0100000 00100000>;
  215. reg = <e0100000 480>;
  216. brg-frequency = <0>;
  217. bus-frequency = <BCD3D80>;
  218. muram@10000 {
  219. device_type = "muram";
  220. ranges = <0 00010000 00004000>;
  221. data-only@0 {
  222. reg = <0 4000>;
  223. };
  224. };
  225. spi@4c0 {
  226. device_type = "spi";
  227. compatible = "fsl_spi";
  228. reg = <4c0 40>;
  229. interrupts = <2>;
  230. interrupt-parent = <80>;
  231. mode = "cpu";
  232. };
  233. spi@500 {
  234. device_type = "spi";
  235. compatible = "fsl_spi";
  236. reg = <500 40>;
  237. interrupts = <1>;
  238. interrupt-parent = <80>;
  239. mode = "cpu";
  240. };
  241. usb@6c0 {
  242. device_type = "usb";
  243. compatible = "qe_udc";
  244. reg = <6c0 40 8B00 100>;
  245. interrupts = <b>;
  246. interrupt-parent = <80>;
  247. mode = "slave";
  248. };
  249. ucc@2200 {
  250. device_type = "network";
  251. compatible = "ucc_geth";
  252. model = "UCC";
  253. device-id = <3>;
  254. reg = <2200 200>;
  255. interrupts = <22>;
  256. interrupt-parent = <80>;
  257. mac-address = [ 00 04 9f 00 23 23 ];
  258. rx-clock = <19>;
  259. tx-clock = <1a>;
  260. phy-handle = <212003>;
  261. pio-handle = <140003>;
  262. };
  263. ucc@3200 {
  264. device_type = "network";
  265. compatible = "ucc_geth";
  266. model = "UCC";
  267. device-id = <4>;
  268. reg = <3000 200>;
  269. interrupts = <23>;
  270. interrupt-parent = <80>;
  271. mac-address = [ 00 11 22 33 44 55 ];
  272. rx-clock = <17>;
  273. tx-clock = <18>;
  274. phy-handle = <212004>;
  275. pio-handle = <140004>;
  276. };
  277. mdio@2320 {
  278. #address-cells = <1>;
  279. #size-cells = <0>;
  280. reg = <2320 18>;
  281. device_type = "mdio";
  282. compatible = "ucc_geth_phy";
  283. ethernet-phy@03 {
  284. linux,phandle = <212003>;
  285. interrupt-parent = <700>;
  286. interrupts = <11 2>;
  287. reg = <3>;
  288. device_type = "ethernet-phy";
  289. interface = <3>; //ENET_100_MII
  290. };
  291. ethernet-phy@04 {
  292. linux,phandle = <212004>;
  293. interrupt-parent = <700>;
  294. interrupts = <12 2>;
  295. reg = <4>;
  296. device_type = "ethernet-phy";
  297. interface = <3>;
  298. };
  299. };
  300. qeic@80 {
  301. linux,phandle = <80>;
  302. interrupt-controller;
  303. device_type = "qeic";
  304. #address-cells = <0>;
  305. #interrupt-cells = <1>;
  306. reg = <80 80>;
  307. built-in;
  308. big-endian;
  309. interrupts = <20 8 21 8>; //high:32 low:33
  310. interrupt-parent = <700>;
  311. };
  312. };
  313. };