ip22-int.c 8.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350
  1. /*
  2. * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
  3. * found on INDY and Indigo2 workstations.
  4. *
  5. * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  6. * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
  7. * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
  8. * - Indigo2 changes
  9. * - Interrupt handling fixes
  10. * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
  11. */
  12. #include <linux/types.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel_stat.h>
  15. #include <linux/signal.h>
  16. #include <linux/sched.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <asm/mipsregs.h>
  20. #include <asm/addrspace.h>
  21. #include <asm/irq_cpu.h>
  22. #include <asm/sgi/ioc.h>
  23. #include <asm/sgi/hpc3.h>
  24. #include <asm/sgi/ip22.h>
  25. /* #define DEBUG_SGINT */
  26. /* So far nothing hangs here */
  27. #undef USE_LIO3_IRQ
  28. struct sgint_regs *sgint;
  29. static char lc0msk_to_irqnr[256];
  30. static char lc1msk_to_irqnr[256];
  31. static char lc2msk_to_irqnr[256];
  32. static char lc3msk_to_irqnr[256];
  33. extern int ip22_eisa_init(void);
  34. static void enable_local0_irq(unsigned int irq)
  35. {
  36. /* don't allow mappable interrupt to be enabled from setup_irq,
  37. * we have our own way to do so */
  38. if (irq != SGI_MAP_0_IRQ)
  39. sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
  40. }
  41. static void disable_local0_irq(unsigned int irq)
  42. {
  43. sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
  44. }
  45. static struct irq_chip ip22_local0_irq_type = {
  46. .name = "IP22 local 0",
  47. .ack = disable_local0_irq,
  48. .mask = disable_local0_irq,
  49. .mask_ack = disable_local0_irq,
  50. .unmask = enable_local0_irq,
  51. };
  52. static void enable_local1_irq(unsigned int irq)
  53. {
  54. /* don't allow mappable interrupt to be enabled from setup_irq,
  55. * we have our own way to do so */
  56. if (irq != SGI_MAP_1_IRQ)
  57. sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
  58. }
  59. void disable_local1_irq(unsigned int irq)
  60. {
  61. sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
  62. }
  63. static struct irq_chip ip22_local1_irq_type = {
  64. .name = "IP22 local 1",
  65. .ack = disable_local1_irq,
  66. .mask = disable_local1_irq,
  67. .mask_ack = disable_local1_irq,
  68. .unmask = enable_local1_irq,
  69. };
  70. static void enable_local2_irq(unsigned int irq)
  71. {
  72. sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
  73. sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
  74. }
  75. void disable_local2_irq(unsigned int irq)
  76. {
  77. sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
  78. if (!sgint->cmeimask0)
  79. sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
  80. }
  81. static struct irq_chip ip22_local2_irq_type = {
  82. .name = "IP22 local 2",
  83. .ack = disable_local2_irq,
  84. .mask = disable_local2_irq,
  85. .mask_ack = disable_local2_irq,
  86. .unmask = enable_local2_irq,
  87. };
  88. static void enable_local3_irq(unsigned int irq)
  89. {
  90. sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
  91. sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
  92. }
  93. void disable_local3_irq(unsigned int irq)
  94. {
  95. sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
  96. if (!sgint->cmeimask1)
  97. sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
  98. }
  99. static struct irq_chip ip22_local3_irq_type = {
  100. .name = "IP22 local 3",
  101. .ack = disable_local3_irq,
  102. .mask = disable_local3_irq,
  103. .mask_ack = disable_local3_irq,
  104. .unmask = enable_local3_irq,
  105. };
  106. static void indy_local0_irqdispatch(void)
  107. {
  108. u8 mask = sgint->istat0 & sgint->imask0;
  109. u8 mask2;
  110. int irq;
  111. if (mask & SGINT_ISTAT0_LIO2) {
  112. mask2 = sgint->vmeistat & sgint->cmeimask0;
  113. irq = lc2msk_to_irqnr[mask2];
  114. } else
  115. irq = lc0msk_to_irqnr[mask];
  116. /* if irq == 0, then the interrupt has already been cleared */
  117. if (irq)
  118. do_IRQ(irq);
  119. }
  120. static void indy_local1_irqdispatch(void)
  121. {
  122. u8 mask = sgint->istat1 & sgint->imask1;
  123. u8 mask2;
  124. int irq;
  125. if (mask & SGINT_ISTAT1_LIO3) {
  126. mask2 = sgint->vmeistat & sgint->cmeimask1;
  127. irq = lc3msk_to_irqnr[mask2];
  128. } else
  129. irq = lc1msk_to_irqnr[mask];
  130. /* if irq == 0, then the interrupt has already been cleared */
  131. if (irq)
  132. do_IRQ(irq);
  133. }
  134. extern void ip22_be_interrupt(int irq);
  135. static void indy_buserror_irq(void)
  136. {
  137. int irq = SGI_BUSERR_IRQ;
  138. irq_enter();
  139. kstat_this_cpu.irqs[irq]++;
  140. ip22_be_interrupt(irq);
  141. irq_exit();
  142. }
  143. static struct irqaction local0_cascade = {
  144. .handler = no_action,
  145. .flags = IRQF_DISABLED,
  146. .name = "local0 cascade",
  147. };
  148. static struct irqaction local1_cascade = {
  149. .handler = no_action,
  150. .flags = IRQF_DISABLED,
  151. .name = "local1 cascade",
  152. };
  153. static struct irqaction buserr = {
  154. .handler = no_action,
  155. .flags = IRQF_DISABLED,
  156. .name = "Bus Error",
  157. };
  158. static struct irqaction map0_cascade = {
  159. .handler = no_action,
  160. .flags = IRQF_DISABLED,
  161. .name = "mapable0 cascade",
  162. };
  163. #ifdef USE_LIO3_IRQ
  164. static struct irqaction map1_cascade = {
  165. .handler = no_action,
  166. .flags = IRQF_DISABLED,
  167. .name = "mapable1 cascade",
  168. };
  169. #define SGI_INTERRUPTS SGINT_END
  170. #else
  171. #define SGI_INTERRUPTS SGINT_LOCAL3
  172. #endif
  173. extern void indy_r4k_timer_interrupt(void);
  174. extern void indy_8254timer_irq(void);
  175. /*
  176. * IRQs on the INDY look basically (barring software IRQs which we don't use
  177. * at all) like:
  178. *
  179. * MIPS IRQ Source
  180. * -------- ------
  181. * 0 Software (ignored)
  182. * 1 Software (ignored)
  183. * 2 Local IRQ level zero
  184. * 3 Local IRQ level one
  185. * 4 8254 Timer zero
  186. * 5 8254 Timer one
  187. * 6 Bus Error
  188. * 7 R4k timer (what we use)
  189. *
  190. * We handle the IRQ according to _our_ priority which is:
  191. *
  192. * Highest ---- R4k Timer
  193. * Local IRQ zero
  194. * Local IRQ one
  195. * Bus Error
  196. * 8254 Timer zero
  197. * Lowest ---- 8254 Timer one
  198. *
  199. * then we just return, if multiple IRQs are pending then we will just take
  200. * another exception, big deal.
  201. */
  202. asmlinkage void plat_irq_dispatch(void)
  203. {
  204. unsigned int pending = read_c0_cause();
  205. /*
  206. * First we check for r4k counter/timer IRQ.
  207. */
  208. if (pending & CAUSEF_IP7)
  209. indy_r4k_timer_interrupt();
  210. else if (pending & CAUSEF_IP2)
  211. indy_local0_irqdispatch();
  212. else if (pending & CAUSEF_IP3)
  213. indy_local1_irqdispatch();
  214. else if (pending & CAUSEF_IP6)
  215. indy_buserror_irq();
  216. else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
  217. indy_8254timer_irq();
  218. }
  219. void __init arch_init_irq(void)
  220. {
  221. int i;
  222. /* Init local mask --> irq tables. */
  223. for (i = 0; i < 256; i++) {
  224. if (i & 0x80) {
  225. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
  226. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
  227. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
  228. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
  229. } else if (i & 0x40) {
  230. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
  231. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
  232. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
  233. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
  234. } else if (i & 0x20) {
  235. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
  236. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
  237. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
  238. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
  239. } else if (i & 0x10) {
  240. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
  241. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
  242. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
  243. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
  244. } else if (i & 0x08) {
  245. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
  246. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
  247. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
  248. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
  249. } else if (i & 0x04) {
  250. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
  251. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
  252. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
  253. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
  254. } else if (i & 0x02) {
  255. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
  256. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
  257. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
  258. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
  259. } else if (i & 0x01) {
  260. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
  261. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
  262. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
  263. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
  264. } else {
  265. lc0msk_to_irqnr[i] = 0;
  266. lc1msk_to_irqnr[i] = 0;
  267. lc2msk_to_irqnr[i] = 0;
  268. lc3msk_to_irqnr[i] = 0;
  269. }
  270. }
  271. /* Mask out all interrupts. */
  272. sgint->imask0 = 0;
  273. sgint->imask1 = 0;
  274. sgint->cmeimask0 = 0;
  275. sgint->cmeimask1 = 0;
  276. /* init CPU irqs */
  277. mips_cpu_irq_init();
  278. for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
  279. struct irq_chip *handler;
  280. if (i < SGINT_LOCAL1)
  281. handler = &ip22_local0_irq_type;
  282. else if (i < SGINT_LOCAL2)
  283. handler = &ip22_local1_irq_type;
  284. else if (i < SGINT_LOCAL3)
  285. handler = &ip22_local2_irq_type;
  286. else
  287. handler = &ip22_local3_irq_type;
  288. set_irq_chip_and_handler(i, handler, handle_level_irq);
  289. }
  290. /* vector handler. this register the IRQ as non-sharable */
  291. setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
  292. setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
  293. setup_irq(SGI_BUSERR_IRQ, &buserr);
  294. /* cascade in cascade. i love Indy ;-) */
  295. setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
  296. #ifdef USE_LIO3_IRQ
  297. setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
  298. #endif
  299. #ifdef CONFIG_EISA
  300. if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
  301. ip22_eisa_init ();
  302. #endif
  303. }