ops-tx4938.c 4.4 KB

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  1. /*
  2. * Define the pci_ops for the Toshiba rbtx4938
  3. * Copyright (C) 2000-2001 Toshiba Corporation
  4. *
  5. * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
  6. * terms of the GNU General Public License version 2. This program is
  7. * licensed "as is" without any warranty of any kind, whether express
  8. * or implied.
  9. *
  10. * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  11. */
  12. #include <linux/types.h>
  13. #include <linux/pci.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <asm/addrspace.h>
  17. #include <asm/tx4938/rbtx4938.h>
  18. /* initialize in setup */
  19. struct resource pci_io_resource = {
  20. .name = "pci IO space",
  21. .start = 0,
  22. .end = 0,
  23. .flags = IORESOURCE_IO
  24. };
  25. /* initialize in setup */
  26. struct resource pci_mem_resource = {
  27. .name = "pci memory space",
  28. .start = 0,
  29. .end = 0,
  30. .flags = IORESOURCE_MEM
  31. };
  32. struct resource tx4938_pcic1_pci_io_resource = {
  33. .name = "PCI1 IO",
  34. .start = 0,
  35. .end = 0,
  36. .flags = IORESOURCE_IO
  37. };
  38. struct resource tx4938_pcic1_pci_mem_resource = {
  39. .name = "PCI1 mem",
  40. .start = 0,
  41. .end = 0,
  42. .flags = IORESOURCE_MEM
  43. };
  44. static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
  45. {
  46. if (bus > 0) {
  47. /* Type 1 configuration */
  48. tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
  49. ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
  50. } else {
  51. if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
  52. return -1;
  53. /* Type 0 configuration */
  54. tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
  55. ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
  56. }
  57. /* clear M_ABORT and Disable M_ABORT Int. */
  58. tx4938_pcicptr->pcistatus =
  59. (tx4938_pcicptr->pcistatus & 0x0000ffff) |
  60. (PCI_STATUS_REC_MASTER_ABORT << 16);
  61. tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
  62. return 0;
  63. }
  64. static int check_abort(int flags)
  65. {
  66. int code = PCIBIOS_SUCCESSFUL;
  67. /* wait write cycle completion before checking error status */
  68. while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
  69. ;
  70. if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
  71. tx4938_pcicptr->pcistatus =
  72. (tx4938_pcicptr->
  73. pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
  74. << 16);
  75. tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
  76. code = PCIBIOS_DEVICE_NOT_FOUND;
  77. }
  78. return code;
  79. }
  80. static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
  81. int where, int size, u32 * val)
  82. {
  83. int flags, retval, dev, busno, func;
  84. dev = PCI_SLOT(devfn);
  85. func = PCI_FUNC(devfn);
  86. /* check if the bus is top-level */
  87. if (bus->parent != NULL)
  88. busno = bus->number;
  89. else {
  90. busno = 0;
  91. }
  92. if (mkaddr(busno, devfn, where, &flags))
  93. return -1;
  94. switch (size) {
  95. case 1:
  96. *val = *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
  97. #ifdef __BIG_ENDIAN
  98. ((where & 3) ^ 3));
  99. #else
  100. (where & 3));
  101. #endif
  102. break;
  103. case 2:
  104. *val = *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
  105. #ifdef __BIG_ENDIAN
  106. ((where & 3) ^ 2));
  107. #else
  108. (where & 3));
  109. #endif
  110. break;
  111. case 4:
  112. *val = tx4938_pcicptr->g2pcfgdata;
  113. break;
  114. }
  115. retval = check_abort(flags);
  116. if (retval == PCIBIOS_DEVICE_NOT_FOUND)
  117. *val = 0xffffffff;
  118. return retval;
  119. }
  120. static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  121. int size, u32 val)
  122. {
  123. int flags, dev, busno, func;
  124. busno = bus->number;
  125. dev = PCI_SLOT(devfn);
  126. func = PCI_FUNC(devfn);
  127. /* check if the bus is top-level */
  128. if (bus->parent != NULL) {
  129. busno = bus->number;
  130. } else {
  131. busno = 0;
  132. }
  133. if (mkaddr(busno, devfn, where, &flags))
  134. return -1;
  135. switch (size) {
  136. case 1:
  137. *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
  138. #ifdef __BIG_ENDIAN
  139. ((where & 3) ^ 3)) = val;
  140. #else
  141. (where & 3)) = val;
  142. #endif
  143. break;
  144. case 2:
  145. *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
  146. #ifdef __BIG_ENDIAN
  147. ((where & 0x3) ^ 0x2)) = val;
  148. #else
  149. (where & 3)) = val;
  150. #endif
  151. break;
  152. case 4:
  153. tx4938_pcicptr->g2pcfgdata = val;
  154. break;
  155. }
  156. return check_abort(flags);
  157. }
  158. struct pci_ops tx4938_pci_ops = {
  159. tx4938_pcibios_read_config,
  160. tx4938_pcibios_write_config
  161. };
  162. struct pci_controller tx4938_pci_controller[] = {
  163. /* h/w only supports devices 0x00 to 0x14 */
  164. {
  165. .pci_ops = &tx4938_pci_ops,
  166. .io_resource = &pci_io_resource,
  167. .mem_resource = &pci_mem_resource,
  168. },
  169. /* h/w only supports devices 0x00 to 0x14 */
  170. {
  171. .pci_ops = &tx4938_pci_ops,
  172. .io_resource = &tx4938_pcic1_pci_io_resource,
  173. .mem_resource = &tx4938_pcic1_pci_mem_resource,
  174. }
  175. };