proc.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166
  1. /*
  2. * linux/arch/mips/kernel/proc.c
  3. *
  4. * Copyright (C) 1995, 1996, 2001 Ralf Baechle
  5. * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
  6. * Copyright (C) 2004 Maciej W. Rozycki
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/kernel.h>
  10. #include <linux/sched.h>
  11. #include <linux/seq_file.h>
  12. #include <asm/bootinfo.h>
  13. #include <asm/cpu.h>
  14. #include <asm/cpu-features.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/processor.h>
  17. #include <asm/watch.h>
  18. unsigned int vced_count, vcei_count;
  19. static const char *cpu_name[] = {
  20. [CPU_UNKNOWN] = "unknown",
  21. [CPU_R2000] = "R2000",
  22. [CPU_R3000] = "R3000",
  23. [CPU_R3000A] = "R3000A",
  24. [CPU_R3041] = "R3041",
  25. [CPU_R3051] = "R3051",
  26. [CPU_R3052] = "R3052",
  27. [CPU_R3081] = "R3081",
  28. [CPU_R3081E] = "R3081E",
  29. [CPU_R4000PC] = "R4000PC",
  30. [CPU_R4000SC] = "R4000SC",
  31. [CPU_R4000MC] = "R4000MC",
  32. [CPU_R4200] = "R4200",
  33. [CPU_R4400PC] = "R4400PC",
  34. [CPU_R4400SC] = "R4400SC",
  35. [CPU_R4400MC] = "R4400MC",
  36. [CPU_R4600] = "R4600",
  37. [CPU_R6000] = "R6000",
  38. [CPU_R6000A] = "R6000A",
  39. [CPU_R8000] = "R8000",
  40. [CPU_R10000] = "R10000",
  41. [CPU_R12000] = "R12000",
  42. [CPU_R14000] = "R14000",
  43. [CPU_R4300] = "R4300",
  44. [CPU_R4650] = "R4650",
  45. [CPU_R4700] = "R4700",
  46. [CPU_R5000] = "R5000",
  47. [CPU_R5000A] = "R5000A",
  48. [CPU_R4640] = "R4640",
  49. [CPU_NEVADA] = "Nevada",
  50. [CPU_RM7000] = "RM7000",
  51. [CPU_RM9000] = "RM9000",
  52. [CPU_R5432] = "R5432",
  53. [CPU_4KC] = "MIPS 4Kc",
  54. [CPU_5KC] = "MIPS 5Kc",
  55. [CPU_R4310] = "R4310",
  56. [CPU_SB1] = "SiByte SB1",
  57. [CPU_SB1A] = "SiByte SB1A",
  58. [CPU_TX3912] = "TX3912",
  59. [CPU_TX3922] = "TX3922",
  60. [CPU_TX3927] = "TX3927",
  61. [CPU_AU1000] = "Au1000",
  62. [CPU_AU1500] = "Au1500",
  63. [CPU_AU1100] = "Au1100",
  64. [CPU_AU1550] = "Au1550",
  65. [CPU_AU1200] = "Au1200",
  66. [CPU_4KEC] = "MIPS 4KEc",
  67. [CPU_4KSC] = "MIPS 4KSc",
  68. [CPU_VR41XX] = "NEC Vr41xx",
  69. [CPU_R5500] = "R5500",
  70. [CPU_TX49XX] = "TX49xx",
  71. [CPU_20KC] = "MIPS 20Kc",
  72. [CPU_24K] = "MIPS 24K",
  73. [CPU_25KF] = "MIPS 25Kf",
  74. [CPU_34K] = "MIPS 34K",
  75. [CPU_74K] = "MIPS 74K",
  76. [CPU_VR4111] = "NEC VR4111",
  77. [CPU_VR4121] = "NEC VR4121",
  78. [CPU_VR4122] = "NEC VR4122",
  79. [CPU_VR4131] = "NEC VR4131",
  80. [CPU_VR4133] = "NEC VR4133",
  81. [CPU_VR4181] = "NEC VR4181",
  82. [CPU_VR4181A] = "NEC VR4181A",
  83. [CPU_SR71000] = "Sandcraft SR71000",
  84. [CPU_PR4450] = "Philips PR4450",
  85. };
  86. static int show_cpuinfo(struct seq_file *m, void *v)
  87. {
  88. unsigned long n = (unsigned long) v - 1;
  89. unsigned int version = cpu_data[n].processor_id;
  90. unsigned int fp_vers = cpu_data[n].fpu_id;
  91. char fmt [64];
  92. #ifdef CONFIG_SMP
  93. if (!cpu_isset(n, cpu_online_map))
  94. return 0;
  95. #endif
  96. /*
  97. * For the first processor also print the system type
  98. */
  99. if (n == 0)
  100. seq_printf(m, "system type\t\t: %s\n", get_system_type());
  101. seq_printf(m, "processor\t\t: %ld\n", n);
  102. sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
  103. cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
  104. seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ?
  105. cpu_data[n].cputype : CPU_UNKNOWN],
  106. (version >> 4) & 0x0f, version & 0x0f,
  107. (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
  108. seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
  109. cpu_data[n].udelay_val / (500000/HZ),
  110. (cpu_data[n].udelay_val / (5000/HZ)) % 100);
  111. seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
  112. seq_printf(m, "microsecond timers\t: %s\n",
  113. cpu_has_counter ? "yes" : "no");
  114. seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
  115. seq_printf(m, "extra interrupt vector\t: %s\n",
  116. cpu_has_divec ? "yes" : "no");
  117. seq_printf(m, "hardware watchpoint\t: %s\n",
  118. cpu_has_watch ? "yes" : "no");
  119. seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
  120. cpu_has_mips16 ? " mips16" : "",
  121. cpu_has_mdmx ? " mdmx" : "",
  122. cpu_has_mips3d ? " mips3d" : "",
  123. cpu_has_smartmips ? " smartmips" : "",
  124. cpu_has_dsp ? " dsp" : "",
  125. cpu_has_mipsmt ? " mt" : ""
  126. );
  127. sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
  128. cpu_has_vce ? "%u" : "not available");
  129. seq_printf(m, fmt, 'D', vced_count);
  130. seq_printf(m, fmt, 'I', vcei_count);
  131. seq_printf(m, "\n");
  132. return 0;
  133. }
  134. static void *c_start(struct seq_file *m, loff_t *pos)
  135. {
  136. unsigned long i = *pos;
  137. return i < NR_CPUS ? (void *) (i + 1) : NULL;
  138. }
  139. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  140. {
  141. ++*pos;
  142. return c_start(m, pos);
  143. }
  144. static void c_stop(struct seq_file *m, void *v)
  145. {
  146. }
  147. struct seq_operations cpuinfo_op = {
  148. .start = c_start,
  149. .next = c_next,
  150. .stop = c_stop,
  151. .show = show_cpuinfo,
  152. };