irq-mv6434x.c 2.9 KB

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  1. /*
  2. * Copyright 2002 Momentum Computer
  3. * Author: mdharm@momenco.com
  4. * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/kernel_stat.h>
  15. #include <linux/mv643xx.h>
  16. #include <linux/sched.h>
  17. #include <asm/io.h>
  18. #include <asm/irq.h>
  19. #include <asm/marvell.h>
  20. static unsigned int irq_base;
  21. static inline int ls1bit32(unsigned int x)
  22. {
  23. int b = 31, s;
  24. s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
  25. s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
  26. s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
  27. s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
  28. s = 1; if (x << 1 == 0) s = 0; b -= s;
  29. return b;
  30. }
  31. /* mask off an interrupt -- 1 is enable, 0 is disable */
  32. static inline void mask_mv64340_irq(unsigned int irq)
  33. {
  34. uint32_t value;
  35. if (irq < (irq_base + 32)) {
  36. value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
  37. value &= ~(1 << (irq - irq_base));
  38. MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
  39. } else {
  40. value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
  41. value &= ~(1 << (irq - irq_base - 32));
  42. MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
  43. }
  44. }
  45. /* unmask an interrupt -- 1 is enable, 0 is disable */
  46. static inline void unmask_mv64340_irq(unsigned int irq)
  47. {
  48. uint32_t value;
  49. if (irq < (irq_base + 32)) {
  50. value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
  51. value |= 1 << (irq - irq_base);
  52. MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
  53. } else {
  54. value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
  55. value |= 1 << (irq - irq_base - 32);
  56. MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
  57. }
  58. }
  59. /*
  60. * Interrupt handler for interrupts coming from the Marvell chip.
  61. * It could be built in ethernet ports etc...
  62. */
  63. void ll_mv64340_irq(void)
  64. {
  65. unsigned int irq_src_low, irq_src_high;
  66. unsigned int irq_mask_low, irq_mask_high;
  67. /* read the interrupt status registers */
  68. irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
  69. irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
  70. irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW);
  71. irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH);
  72. /* mask for just the interrupts we want */
  73. irq_src_low &= irq_mask_low;
  74. irq_src_high &= irq_mask_high;
  75. if (irq_src_low)
  76. do_IRQ(ls1bit32(irq_src_low) + irq_base);
  77. else
  78. do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
  79. }
  80. struct irq_chip mv64340_irq_type = {
  81. .name = "MV-64340",
  82. .ack = mask_mv64340_irq,
  83. .mask = mask_mv64340_irq,
  84. .mask_ack = mask_mv64340_irq,
  85. .unmask = unmask_mv64340_irq,
  86. };
  87. void __init mv64340_irq_init(unsigned int base)
  88. {
  89. int i;
  90. for (i = base; i < base + 64; i++)
  91. set_irq_chip_and_handler(i, &mv64340_irq_type,
  92. handle_level_irq);
  93. irq_base = base;
  94. }