h3600.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906
  1. /*
  2. * Hardware definitions for Compaq iPAQ H3xxx Handheld Computers
  3. *
  4. * Copyright 2000,1 Compaq Computer Corporation.
  5. *
  6. * Use consistent with the GNU GPL is permitted,
  7. * provided that this copyright notice is
  8. * preserved in its entirety in all copies and derived works.
  9. *
  10. * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
  11. * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
  12. * FITNESS FOR ANY PARTICULAR PURPOSE.
  13. *
  14. * Author: Jamey Hicks.
  15. *
  16. * History:
  17. *
  18. * 2001-10-?? Andrew Christian Added support for iPAQ H3800
  19. * and abstracted EGPIO interface.
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/init.h>
  24. #include <linux/kernel.h>
  25. #include <linux/tty.h>
  26. #include <linux/pm.h>
  27. #include <linux/device.h>
  28. #include <linux/mtd/mtd.h>
  29. #include <linux/mtd/partitions.h>
  30. #include <linux/serial_core.h>
  31. #include <asm/irq.h>
  32. #include <asm/hardware.h>
  33. #include <asm/mach-types.h>
  34. #include <asm/setup.h>
  35. #include <asm/mach/irq.h>
  36. #include <asm/mach/arch.h>
  37. #include <asm/mach/flash.h>
  38. #include <asm/mach/irda.h>
  39. #include <asm/mach/map.h>
  40. #include <asm/mach/serial_sa1100.h>
  41. #include <asm/arch/h3600.h>
  42. #if defined (CONFIG_SA1100_H3600) || defined (CONFIG_SA1100_H3100)
  43. #include <asm/arch/h3600_gpio.h>
  44. #endif
  45. #ifdef CONFIG_SA1100_H3800
  46. #include <asm/arch/h3600_asic.h>
  47. #endif
  48. #include "generic.h"
  49. struct ipaq_model_ops ipaq_model_ops;
  50. EXPORT_SYMBOL(ipaq_model_ops);
  51. static struct mtd_partition h3xxx_partitions[] = {
  52. {
  53. .name = "H3XXX boot firmware",
  54. .size = 0x00040000,
  55. .offset = 0,
  56. .mask_flags = MTD_WRITEABLE, /* force read-only */
  57. }, {
  58. #ifdef CONFIG_MTD_2PARTS_IPAQ
  59. .name = "H3XXX root jffs2",
  60. .size = MTDPART_SIZ_FULL,
  61. .offset = 0x00040000,
  62. #else
  63. .name = "H3XXX kernel",
  64. .size = 0x00080000,
  65. .offset = 0x00040000,
  66. }, {
  67. .name = "H3XXX params",
  68. .size = 0x00040000,
  69. .offset = 0x000C0000,
  70. }, {
  71. #ifdef CONFIG_JFFS2_FS
  72. .name = "H3XXX root jffs2",
  73. .size = MTDPART_SIZ_FULL,
  74. .offset = 0x00100000,
  75. #else
  76. .name = "H3XXX initrd",
  77. .size = 0x00100000,
  78. .offset = 0x00100000,
  79. }, {
  80. .name = "H3XXX root cramfs",
  81. .size = 0x00300000,
  82. .offset = 0x00200000,
  83. }, {
  84. .name = "H3XXX usr cramfs",
  85. .size = 0x00800000,
  86. .offset = 0x00500000,
  87. }, {
  88. .name = "H3XXX usr local",
  89. .size = MTDPART_SIZ_FULL,
  90. .offset = 0x00d00000,
  91. #endif
  92. #endif
  93. }
  94. };
  95. static void h3xxx_set_vpp(int vpp)
  96. {
  97. assign_h3600_egpio(IPAQ_EGPIO_VPP_ON, vpp);
  98. }
  99. static struct flash_platform_data h3xxx_flash_data = {
  100. .map_name = "cfi_probe",
  101. .set_vpp = h3xxx_set_vpp,
  102. .parts = h3xxx_partitions,
  103. .nr_parts = ARRAY_SIZE(h3xxx_partitions),
  104. };
  105. static struct resource h3xxx_flash_resource = {
  106. .start = SA1100_CS0_PHYS,
  107. .end = SA1100_CS0_PHYS + SZ_32M - 1,
  108. .flags = IORESOURCE_MEM,
  109. };
  110. /*
  111. * This turns the IRDA power on or off on the Compaq H3600
  112. */
  113. static int h3600_irda_set_power(struct device *dev, unsigned int state)
  114. {
  115. assign_h3600_egpio( IPAQ_EGPIO_IR_ON, state );
  116. return 0;
  117. }
  118. static void h3600_irda_set_speed(struct device *dev, unsigned int speed)
  119. {
  120. if (speed < 4000000) {
  121. clr_h3600_egpio(IPAQ_EGPIO_IR_FSEL);
  122. } else {
  123. set_h3600_egpio(IPAQ_EGPIO_IR_FSEL);
  124. }
  125. }
  126. static struct irda_platform_data h3600_irda_data = {
  127. .set_power = h3600_irda_set_power,
  128. .set_speed = h3600_irda_set_speed,
  129. };
  130. static void h3xxx_mach_init(void)
  131. {
  132. sa11x0_set_flash_data(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
  133. sa11x0_set_irda_data(&h3600_irda_data);
  134. }
  135. /*
  136. * low-level UART features
  137. */
  138. static void h3600_uart_set_mctrl(struct uart_port *port, u_int mctrl)
  139. {
  140. if (port->mapbase == _Ser3UTCR0) {
  141. if (mctrl & TIOCM_RTS)
  142. GPCR = GPIO_H3600_COM_RTS;
  143. else
  144. GPSR = GPIO_H3600_COM_RTS;
  145. }
  146. }
  147. static u_int h3600_uart_get_mctrl(struct uart_port *port)
  148. {
  149. u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
  150. if (port->mapbase == _Ser3UTCR0) {
  151. int gplr = GPLR;
  152. /* DCD and CTS bits are inverted in GPLR by RS232 transceiver */
  153. if (gplr & GPIO_H3600_COM_DCD)
  154. ret &= ~TIOCM_CD;
  155. if (gplr & GPIO_H3600_COM_CTS)
  156. ret &= ~TIOCM_CTS;
  157. }
  158. return ret;
  159. }
  160. static void h3600_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
  161. {
  162. if (port->mapbase == _Ser2UTCR0) { /* TODO: REMOVE THIS */
  163. assign_h3600_egpio(IPAQ_EGPIO_IR_ON, !state);
  164. } else if (port->mapbase == _Ser3UTCR0) {
  165. assign_h3600_egpio(IPAQ_EGPIO_RS232_ON, !state);
  166. }
  167. }
  168. /*
  169. * Enable/Disable wake up events for this serial port.
  170. * Obviously, we only support this on the normal COM port.
  171. */
  172. static int h3600_uart_set_wake(struct uart_port *port, u_int enable)
  173. {
  174. int err = -EINVAL;
  175. if (port->mapbase == _Ser3UTCR0) {
  176. if (enable)
  177. PWER |= PWER_GPIO23 | PWER_GPIO25; /* DCD and CTS */
  178. else
  179. PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */
  180. err = 0;
  181. }
  182. return err;
  183. }
  184. static struct sa1100_port_fns h3600_port_fns __initdata = {
  185. .set_mctrl = h3600_uart_set_mctrl,
  186. .get_mctrl = h3600_uart_get_mctrl,
  187. .pm = h3600_uart_pm,
  188. .set_wake = h3600_uart_set_wake,
  189. };
  190. /*
  191. * helper for sa1100fb
  192. */
  193. static void h3xxx_lcd_power(int enable)
  194. {
  195. assign_h3600_egpio(IPAQ_EGPIO_LCD_POWER, enable);
  196. }
  197. static struct map_desc h3600_io_desc[] __initdata = {
  198. { /* static memory bank 2 CS#2 */
  199. .virtual = H3600_BANK_2_VIRT,
  200. .pfn = __phys_to_pfn(SA1100_CS2_PHYS),
  201. .length = 0x02800000,
  202. .type = MT_DEVICE
  203. }, { /* static memory bank 4 CS#4 */
  204. .virtual = H3600_BANK_4_VIRT,
  205. .pfn = __phys_to_pfn(SA1100_CS4_PHYS),
  206. .length = 0x00800000,
  207. .type = MT_DEVICE
  208. }, { /* EGPIO 0 CS#5 */
  209. .virtual = H3600_EGPIO_VIRT,
  210. .pfn = __phys_to_pfn(H3600_EGPIO_PHYS),
  211. .length = 0x01000000,
  212. .type = MT_DEVICE
  213. }
  214. };
  215. /*
  216. * Common map_io initialization
  217. */
  218. static void __init h3xxx_map_io(void)
  219. {
  220. sa1100_map_io();
  221. iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc));
  222. sa1100_register_uart_fns(&h3600_port_fns);
  223. sa1100_register_uart(0, 3); /* Common serial port */
  224. // sa1100_register_uart(1, 1); /* Microcontroller on 3100/3600 */
  225. /* Ensure those pins are outputs and driving low */
  226. PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
  227. PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
  228. /* Configure suspend conditions */
  229. PGSR = 0;
  230. PWER = PWER_GPIO0 | PWER_RTC;
  231. PCFR = PCFR_OPDE;
  232. PSDR = 0;
  233. sa1100fb_lcd_power = h3xxx_lcd_power;
  234. }
  235. static __inline__ void do_blank(int setp)
  236. {
  237. if (ipaq_model_ops.blank_callback)
  238. ipaq_model_ops.blank_callback(1-setp);
  239. }
  240. /************************* H3100 *************************/
  241. #ifdef CONFIG_SA1100_H3100
  242. #define H3100_EGPIO (*(volatile unsigned int *)H3600_EGPIO_VIRT)
  243. static unsigned int h3100_egpio = 0;
  244. static void h3100_control_egpio(enum ipaq_egpio_type x, int setp)
  245. {
  246. unsigned int egpio = 0;
  247. long gpio = 0;
  248. unsigned long flags;
  249. switch (x) {
  250. case IPAQ_EGPIO_LCD_POWER:
  251. egpio |= EGPIO_H3600_LCD_ON;
  252. gpio |= GPIO_H3100_LCD_3V_ON;
  253. do_blank(setp);
  254. break;
  255. case IPAQ_EGPIO_LCD_ENABLE:
  256. break;
  257. case IPAQ_EGPIO_CODEC_NRESET:
  258. egpio |= EGPIO_H3600_CODEC_NRESET;
  259. break;
  260. case IPAQ_EGPIO_AUDIO_ON:
  261. gpio |= GPIO_H3100_AUD_PWR_ON
  262. | GPIO_H3100_AUD_ON;
  263. break;
  264. case IPAQ_EGPIO_QMUTE:
  265. gpio |= GPIO_H3100_QMUTE;
  266. break;
  267. case IPAQ_EGPIO_OPT_NVRAM_ON:
  268. egpio |= EGPIO_H3600_OPT_NVRAM_ON;
  269. break;
  270. case IPAQ_EGPIO_OPT_ON:
  271. egpio |= EGPIO_H3600_OPT_ON;
  272. break;
  273. case IPAQ_EGPIO_CARD_RESET:
  274. egpio |= EGPIO_H3600_CARD_RESET;
  275. break;
  276. case IPAQ_EGPIO_OPT_RESET:
  277. egpio |= EGPIO_H3600_OPT_RESET;
  278. break;
  279. case IPAQ_EGPIO_IR_ON:
  280. gpio |= GPIO_H3100_IR_ON;
  281. break;
  282. case IPAQ_EGPIO_IR_FSEL:
  283. gpio |= GPIO_H3100_IR_FSEL;
  284. break;
  285. case IPAQ_EGPIO_RS232_ON:
  286. egpio |= EGPIO_H3600_RS232_ON;
  287. break;
  288. case IPAQ_EGPIO_VPP_ON:
  289. egpio |= EGPIO_H3600_VPP_ON;
  290. break;
  291. }
  292. if (egpio || gpio) {
  293. local_irq_save(flags);
  294. if (setp) {
  295. h3100_egpio |= egpio;
  296. GPSR = gpio;
  297. } else {
  298. h3100_egpio &= ~egpio;
  299. GPCR = gpio;
  300. }
  301. H3100_EGPIO = h3100_egpio;
  302. local_irq_restore(flags);
  303. }
  304. }
  305. static unsigned long h3100_read_egpio(void)
  306. {
  307. return h3100_egpio;
  308. }
  309. static int h3100_pm_callback(int req)
  310. {
  311. if (ipaq_model_ops.pm_callback_aux)
  312. return ipaq_model_ops.pm_callback_aux(req);
  313. return 0;
  314. }
  315. static struct ipaq_model_ops h3100_model_ops __initdata = {
  316. .generic_name = "3100",
  317. .control = h3100_control_egpio,
  318. .read = h3100_read_egpio,
  319. .pm_callback = h3100_pm_callback
  320. };
  321. #define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON \
  322. | GPIO_H3100_GPIO3 \
  323. | GPIO_H3100_QMUTE \
  324. | GPIO_H3100_LCD_3V_ON \
  325. | GPIO_H3100_AUD_ON \
  326. | GPIO_H3100_AUD_PWR_ON \
  327. | GPIO_H3100_IR_ON \
  328. | GPIO_H3100_IR_FSEL)
  329. static void __init h3100_map_io(void)
  330. {
  331. h3xxx_map_io();
  332. /* Initialize h3100-specific values here */
  333. GPCR = 0x0fffffff; /* All outputs are set low by default */
  334. GPDR = GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK |
  335. GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA |
  336. GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 |
  337. H3100_DIRECT_EGPIO;
  338. /* Older bootldrs put GPIO2-9 in alternate mode on the
  339. assumption that they are used for video */
  340. GAFR &= ~H3100_DIRECT_EGPIO;
  341. H3100_EGPIO = h3100_egpio;
  342. ipaq_model_ops = h3100_model_ops;
  343. }
  344. MACHINE_START(H3100, "Compaq iPAQ H3100")
  345. .phys_io = 0x80000000,
  346. .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
  347. .boot_params = 0xc0000100,
  348. .map_io = h3100_map_io,
  349. .init_irq = sa1100_init_irq,
  350. .timer = &sa1100_timer,
  351. .init_machine = h3xxx_mach_init,
  352. MACHINE_END
  353. #endif /* CONFIG_SA1100_H3100 */
  354. /************************* H3600 *************************/
  355. #ifdef CONFIG_SA1100_H3600
  356. #define H3600_EGPIO (*(volatile unsigned int *)H3600_EGPIO_VIRT)
  357. static unsigned int h3600_egpio = EGPIO_H3600_RS232_ON;
  358. static void h3600_control_egpio(enum ipaq_egpio_type x, int setp)
  359. {
  360. unsigned int egpio = 0;
  361. unsigned long flags;
  362. switch (x) {
  363. case IPAQ_EGPIO_LCD_POWER:
  364. egpio |= EGPIO_H3600_LCD_ON |
  365. EGPIO_H3600_LCD_PCI |
  366. EGPIO_H3600_LCD_5V_ON |
  367. EGPIO_H3600_LVDD_ON;
  368. do_blank(setp);
  369. break;
  370. case IPAQ_EGPIO_LCD_ENABLE:
  371. break;
  372. case IPAQ_EGPIO_CODEC_NRESET:
  373. egpio |= EGPIO_H3600_CODEC_NRESET;
  374. break;
  375. case IPAQ_EGPIO_AUDIO_ON:
  376. egpio |= EGPIO_H3600_AUD_AMP_ON |
  377. EGPIO_H3600_AUD_PWR_ON;
  378. break;
  379. case IPAQ_EGPIO_QMUTE:
  380. egpio |= EGPIO_H3600_QMUTE;
  381. break;
  382. case IPAQ_EGPIO_OPT_NVRAM_ON:
  383. egpio |= EGPIO_H3600_OPT_NVRAM_ON;
  384. break;
  385. case IPAQ_EGPIO_OPT_ON:
  386. egpio |= EGPIO_H3600_OPT_ON;
  387. break;
  388. case IPAQ_EGPIO_CARD_RESET:
  389. egpio |= EGPIO_H3600_CARD_RESET;
  390. break;
  391. case IPAQ_EGPIO_OPT_RESET:
  392. egpio |= EGPIO_H3600_OPT_RESET;
  393. break;
  394. case IPAQ_EGPIO_IR_ON:
  395. egpio |= EGPIO_H3600_IR_ON;
  396. break;
  397. case IPAQ_EGPIO_IR_FSEL:
  398. egpio |= EGPIO_H3600_IR_FSEL;
  399. break;
  400. case IPAQ_EGPIO_RS232_ON:
  401. egpio |= EGPIO_H3600_RS232_ON;
  402. break;
  403. case IPAQ_EGPIO_VPP_ON:
  404. egpio |= EGPIO_H3600_VPP_ON;
  405. break;
  406. }
  407. if (egpio) {
  408. local_irq_save(flags);
  409. if (setp)
  410. h3600_egpio |= egpio;
  411. else
  412. h3600_egpio &= ~egpio;
  413. H3600_EGPIO = h3600_egpio;
  414. local_irq_restore(flags);
  415. }
  416. }
  417. static unsigned long h3600_read_egpio(void)
  418. {
  419. return h3600_egpio;
  420. }
  421. static int h3600_pm_callback(int req)
  422. {
  423. if (ipaq_model_ops.pm_callback_aux)
  424. return ipaq_model_ops.pm_callback_aux(req);
  425. return 0;
  426. }
  427. static struct ipaq_model_ops h3600_model_ops __initdata = {
  428. .generic_name = "3600",
  429. .control = h3600_control_egpio,
  430. .read = h3600_read_egpio,
  431. .pm_callback = h3600_pm_callback
  432. };
  433. static void __init h3600_map_io(void)
  434. {
  435. h3xxx_map_io();
  436. /* Initialize h3600-specific values here */
  437. GPCR = 0x0fffffff; /* All outputs are set low by default */
  438. GPDR = GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK |
  439. GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA |
  440. GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 |
  441. GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
  442. GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
  443. H3600_EGPIO = h3600_egpio; /* Maintains across sleep? */
  444. ipaq_model_ops = h3600_model_ops;
  445. }
  446. MACHINE_START(H3600, "Compaq iPAQ H3600")
  447. .phys_io = 0x80000000,
  448. .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
  449. .boot_params = 0xc0000100,
  450. .map_io = h3600_map_io,
  451. .init_irq = sa1100_init_irq,
  452. .timer = &sa1100_timer,
  453. .init_machine = h3xxx_mach_init,
  454. MACHINE_END
  455. #endif /* CONFIG_SA1100_H3600 */
  456. #ifdef CONFIG_SA1100_H3800
  457. #define SET_ASIC1(x) \
  458. do {if (setp) { H3800_ASIC1_GPIO_OUT |= (x); } else { H3800_ASIC1_GPIO_OUT &= ~(x); }} while(0)
  459. #define SET_ASIC2(x) \
  460. do {if (setp) { H3800_ASIC2_GPIOPIOD |= (x); } else { H3800_ASIC2_GPIOPIOD &= ~(x); }} while(0)
  461. #define CLEAR_ASIC1(x) \
  462. do {if (setp) { H3800_ASIC1_GPIO_OUT &= ~(x); } else { H3800_ASIC1_GPIO_OUT |= (x); }} while(0)
  463. #define CLEAR_ASIC2(x) \
  464. do {if (setp) { H3800_ASIC2_GPIOPIOD &= ~(x); } else { H3800_ASIC2_GPIOPIOD |= (x); }} while(0)
  465. /*
  466. On screen enable, we get
  467. h3800_video_power_on(1)
  468. LCD controller starts
  469. h3800_video_lcd_enable(1)
  470. On screen disable, we get
  471. h3800_video_lcd_enable(0)
  472. LCD controller stops
  473. h3800_video_power_on(0)
  474. */
  475. static void h3800_video_power_on(int setp)
  476. {
  477. if (setp) {
  478. H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_ON;
  479. msleep(30);
  480. H3800_ASIC1_GPIO_OUT |= GPIO1_VGL_ON;
  481. msleep(5);
  482. H3800_ASIC1_GPIO_OUT |= GPIO1_VGH_ON;
  483. msleep(50);
  484. H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_5V_ON;
  485. msleep(5);
  486. } else {
  487. msleep(5);
  488. H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_5V_ON;
  489. msleep(50);
  490. H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGL_ON;
  491. msleep(5);
  492. H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGH_ON;
  493. msleep(100);
  494. H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_ON;
  495. }
  496. }
  497. static void h3800_video_lcd_enable(int setp)
  498. {
  499. if (setp) {
  500. msleep(17); // Wait one from before turning on
  501. H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_PCI;
  502. } else {
  503. H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_PCI;
  504. msleep(30); // Wait before turning off
  505. }
  506. }
  507. static void h3800_control_egpio(enum ipaq_egpio_type x, int setp)
  508. {
  509. switch (x) {
  510. case IPAQ_EGPIO_LCD_POWER:
  511. h3800_video_power_on(setp);
  512. break;
  513. case IPAQ_EGPIO_LCD_ENABLE:
  514. h3800_video_lcd_enable(setp);
  515. break;
  516. case IPAQ_EGPIO_CODEC_NRESET:
  517. case IPAQ_EGPIO_AUDIO_ON:
  518. case IPAQ_EGPIO_QMUTE:
  519. printk("%s: error - should not be called\n", __FUNCTION__);
  520. break;
  521. case IPAQ_EGPIO_OPT_NVRAM_ON:
  522. SET_ASIC2(GPIO2_OPT_ON_NVRAM);
  523. break;
  524. case IPAQ_EGPIO_OPT_ON:
  525. SET_ASIC2(GPIO2_OPT_ON);
  526. break;
  527. case IPAQ_EGPIO_CARD_RESET:
  528. SET_ASIC2(GPIO2_OPT_PCM_RESET);
  529. break;
  530. case IPAQ_EGPIO_OPT_RESET:
  531. SET_ASIC2(GPIO2_OPT_RESET);
  532. break;
  533. case IPAQ_EGPIO_IR_ON:
  534. CLEAR_ASIC1(GPIO1_IR_ON_N);
  535. break;
  536. case IPAQ_EGPIO_IR_FSEL:
  537. break;
  538. case IPAQ_EGPIO_RS232_ON:
  539. SET_ASIC1(GPIO1_RS232_ON);
  540. break;
  541. case IPAQ_EGPIO_VPP_ON:
  542. H3800_ASIC2_FlashWP_VPP_ON = setp;
  543. break;
  544. }
  545. }
  546. static unsigned long h3800_read_egpio(void)
  547. {
  548. return H3800_ASIC1_GPIO_OUT | (H3800_ASIC2_GPIOPIOD << 16);
  549. }
  550. /* We need to fix ASIC2 GPIO over suspend/resume. At the moment,
  551. it doesn't appear that ASIC1 GPIO has the same problem */
  552. static int h3800_pm_callback(int req)
  553. {
  554. static u16 asic1_data;
  555. static u16 asic2_data;
  556. int result = 0;
  557. printk("%s %d\n", __FUNCTION__, req);
  558. switch (req) {
  559. case PM_RESUME:
  560. MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000; /* Set MSC2 correctly */
  561. H3800_ASIC2_GPIOPIOD = asic2_data;
  562. H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ
  563. | GPIO2_SD_DETECT
  564. | GPIO2_EAR_IN_N
  565. | GPIO2_USB_DETECT_N
  566. | GPIO2_SD_CON_SLT;
  567. H3800_ASIC1_GPIO_OUT = asic1_data;
  568. if (ipaq_model_ops.pm_callback_aux)
  569. result = ipaq_model_ops.pm_callback_aux(req);
  570. break;
  571. case PM_SUSPEND:
  572. if (ipaq_model_ops.pm_callback_aux &&
  573. ((result = ipaq_model_ops.pm_callback_aux(req)) != 0))
  574. return result;
  575. asic1_data = H3800_ASIC1_GPIO_OUT;
  576. asic2_data = H3800_ASIC2_GPIOPIOD;
  577. break;
  578. default:
  579. printk("%s: unrecognized PM callback\n", __FUNCTION__);
  580. break;
  581. }
  582. return result;
  583. }
  584. static struct ipaq_model_ops h3800_model_ops __initdata = {
  585. .generic_name = "3800",
  586. .control = h3800_control_egpio,
  587. .read = h3800_read_egpio,
  588. .pm_callback = h3800_pm_callback
  589. };
  590. #define MAX_ASIC_ISR_LOOPS 20
  591. /* The order of these is important - see #include <asm/arch/irqs.h> */
  592. static u32 kpio_irq_mask[] = {
  593. KPIO_KEY_ALL,
  594. KPIO_SPI_INT,
  595. KPIO_OWM_INT,
  596. KPIO_ADC_INT,
  597. KPIO_UART_0_INT,
  598. KPIO_UART_1_INT,
  599. KPIO_TIMER_0_INT,
  600. KPIO_TIMER_1_INT,
  601. KPIO_TIMER_2_INT
  602. };
  603. static u32 gpio_irq_mask[] = {
  604. GPIO2_PEN_IRQ,
  605. GPIO2_SD_DETECT,
  606. GPIO2_EAR_IN_N,
  607. GPIO2_USB_DETECT_N,
  608. GPIO2_SD_CON_SLT,
  609. };
  610. static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc)
  611. {
  612. int i;
  613. if (0) printk("%s: interrupt received\n", __FUNCTION__);
  614. desc->chip->ack(irq);
  615. for (i = 0; i < MAX_ASIC_ISR_LOOPS && (GPLR & GPIO_H3800_ASIC); i++) {
  616. u32 irq;
  617. int j;
  618. /* KPIO */
  619. irq = H3800_ASIC2_KPIINTFLAG;
  620. if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq);
  621. for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
  622. if (irq & kpio_irq_mask[j])
  623. handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
  624. /* GPIO2 */
  625. irq = H3800_ASIC2_GPIINTFLAG;
  626. if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq);
  627. for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
  628. if (irq & gpio_irq_mask[j])
  629. handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
  630. }
  631. if (i >= MAX_ASIC_ISR_LOOPS)
  632. printk("%s: interrupt processing overrun\n", __FUNCTION__);
  633. /* For level-based interrupts */
  634. desc->chip->unmask(irq);
  635. }
  636. static struct irqaction h3800_irq = {
  637. .name = "h3800_asic",
  638. .handler = h3800_IRQ_demux,
  639. .flags = IRQF_DISABLED | IRQF_TIMER,
  640. };
  641. u32 kpio_int_shadow = 0;
  642. /* mask_ack <- IRQ is first serviced.
  643. mask <- IRQ is disabled.
  644. unmask <- IRQ is enabled
  645. The INTCLR registers are poorly documented. I believe that writing
  646. a "1" to the register clears the specific interrupt, but the documentation
  647. indicates writing a "0" clears the interrupt. In any case, they shouldn't
  648. be read (that's the INTFLAG register)
  649. */
  650. static void h3800_mask_ack_kpio_irq(unsigned int irq)
  651. {
  652. u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START];
  653. kpio_int_shadow &= ~mask;
  654. H3800_ASIC2_KPIINTSTAT = kpio_int_shadow;
  655. H3800_ASIC2_KPIINTCLR = mask;
  656. }
  657. static void h3800_mask_kpio_irq(unsigned int irq)
  658. {
  659. u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START];
  660. kpio_int_shadow &= ~mask;
  661. H3800_ASIC2_KPIINTSTAT = kpio_int_shadow;
  662. }
  663. static void h3800_unmask_kpio_irq(unsigned int irq)
  664. {
  665. u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START];
  666. kpio_int_shadow |= mask;
  667. H3800_ASIC2_KPIINTSTAT = kpio_int_shadow;
  668. }
  669. static void h3800_mask_ack_gpio_irq(unsigned int irq)
  670. {
  671. u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START];
  672. H3800_ASIC2_GPIINTSTAT &= ~mask;
  673. H3800_ASIC2_GPIINTCLR = mask;
  674. }
  675. static void h3800_mask_gpio_irq(unsigned int irq)
  676. {
  677. u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START];
  678. H3800_ASIC2_GPIINTSTAT &= ~mask;
  679. }
  680. static void h3800_unmask_gpio_irq(unsigned int irq)
  681. {
  682. u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START];
  683. H3800_ASIC2_GPIINTSTAT |= mask;
  684. }
  685. static void __init h3800_init_irq(void)
  686. {
  687. int i;
  688. /* Initialize standard IRQs */
  689. sa1100_init_irq();
  690. /* Disable all IRQs and set up clock */
  691. H3800_ASIC2_KPIINTSTAT = 0; /* Disable all interrupts */
  692. H3800_ASIC2_GPIINTSTAT = 0;
  693. H3800_ASIC2_KPIINTCLR = 0; /* Clear all KPIO interrupts */
  694. H3800_ASIC2_GPIINTCLR = 0; /* Clear all GPIO interrupts */
  695. // H3800_ASIC2_KPIINTCLR = 0xffff; /* Clear all KPIO interrupts */
  696. // H3800_ASIC2_GPIINTCLR = 0xffff; /* Clear all GPIO interrupts */
  697. H3800_ASIC2_CLOCK_Enable |= ASIC2_CLOCK_EX0; /* 32 kHZ crystal on */
  698. H3800_ASIC2_INTR_ClockPrescale |= ASIC2_INTCPS_SET;
  699. H3800_ASIC2_INTR_ClockPrescale = ASIC2_INTCPS_CPS(0x0e) | ASIC2_INTCPS_SET;
  700. H3800_ASIC2_INTR_TimerSet = 1;
  701. #if 0
  702. for (i = 0; i < H3800_KPIO_IRQ_COUNT; i++) {
  703. int irq = i + H3800_KPIO_IRQ_START;
  704. irq_desc[irq].valid = 1;
  705. irq_desc[irq].probe_ok = 1;
  706. set_irq_chip(irq, &h3800_kpio_irqchip);
  707. }
  708. for (i = 0; i < H3800_GPIO_IRQ_COUNT; i++) {
  709. int irq = i + H3800_GPIO_IRQ_START;
  710. irq_desc[irq].valid = 1;
  711. irq_desc[irq].probe_ok = 1;
  712. set_irq_chip(irq, &h3800_gpio_irqchip);
  713. }
  714. #endif
  715. set_irq_type(IRQ_GPIO_H3800_ASIC, IRQT_RISING);
  716. set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux);
  717. }
  718. #define ASIC1_OUTPUTS 0x7fff /* First 15 bits are used */
  719. static void __init h3800_map_io(void)
  720. {
  721. h3xxx_map_io();
  722. /* Add wakeup on AC plug/unplug */
  723. PWER |= PWER_GPIO12;
  724. /* Initialize h3800-specific values here */
  725. GPCR = 0x0fffffff; /* All outputs are set low by default */
  726. GAFR = GPIO_H3800_CLK_OUT |
  727. GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
  728. GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
  729. GPDR = GPIO_H3800_CLK_OUT |
  730. GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK |
  731. GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA |
  732. GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
  733. GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
  734. TUCR = TUCR_3_6864MHz; /* Seems to be used only for the Bluetooth UART */
  735. /* Fix the memory bus */
  736. MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000;
  737. /* Set up ASIC #1 */
  738. H3800_ASIC1_GPIO_DIR = ASIC1_OUTPUTS; /* All outputs */
  739. H3800_ASIC1_GPIO_MASK = ASIC1_OUTPUTS; /* No interrupts */
  740. H3800_ASIC1_GPIO_SLEEP_MASK = ASIC1_OUTPUTS;
  741. H3800_ASIC1_GPIO_SLEEP_DIR = ASIC1_OUTPUTS;
  742. H3800_ASIC1_GPIO_SLEEP_OUT = GPIO1_EAR_ON_N;
  743. H3800_ASIC1_GPIO_BATT_FAULT_DIR = ASIC1_OUTPUTS;
  744. H3800_ASIC1_GPIO_BATT_FAULT_OUT = GPIO1_EAR_ON_N;
  745. H3800_ASIC1_GPIO_OUT = GPIO1_IR_ON_N
  746. | GPIO1_RS232_ON
  747. | GPIO1_EAR_ON_N;
  748. /* Set up ASIC #2 */
  749. H3800_ASIC2_GPIOPIOD = GPIO2_IN_Y1_N | GPIO2_IN_X1_N;
  750. H3800_ASIC2_GPOBFSTAT = GPIO2_IN_Y1_N | GPIO2_IN_X1_N;
  751. H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ
  752. | GPIO2_SD_DETECT
  753. | GPIO2_EAR_IN_N
  754. | GPIO2_USB_DETECT_N
  755. | GPIO2_SD_CON_SLT;
  756. /* TODO : Set sleep states & battery fault states */
  757. /* Clear VPP Enable */
  758. H3800_ASIC2_FlashWP_VPP_ON = 0;
  759. ipaq_model_ops = h3800_model_ops;
  760. }
  761. MACHINE_START(H3800, "Compaq iPAQ H3800")
  762. .phys_io = 0x80000000,
  763. .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
  764. .boot_params = 0xc0000100,
  765. .map_io = h3800_map_io,
  766. .init_irq = h3800_init_irq,
  767. .timer = &sa1100_timer,
  768. .init_machine = h3xxx_mach_init,
  769. MACHINE_END
  770. #endif /* CONFIG_SA1100_H3800 */