devs.c 12 KB

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  1. /* linux/arch/arm/mach-s3c2410/devs.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Base S3C24XX platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <asm/mach/arch.h>
  22. #include <asm/mach/map.h>
  23. #include <asm/mach/irq.h>
  24. #include <asm/arch/fb.h>
  25. #include <asm/hardware.h>
  26. #include <asm/io.h>
  27. #include <asm/irq.h>
  28. #include <asm/arch/regs-serial.h>
  29. #include "devs.h"
  30. #include "cpu.h"
  31. /* Serial port registrations */
  32. static struct resource s3c2410_uart0_resource[] = {
  33. [0] = {
  34. .start = S3C2410_PA_UART0,
  35. .end = S3C2410_PA_UART0 + 0x3fff,
  36. .flags = IORESOURCE_MEM,
  37. },
  38. [1] = {
  39. .start = IRQ_S3CUART_RX0,
  40. .end = IRQ_S3CUART_ERR0,
  41. .flags = IORESOURCE_IRQ,
  42. }
  43. };
  44. static struct resource s3c2410_uart1_resource[] = {
  45. [0] = {
  46. .start = S3C2410_PA_UART1,
  47. .end = S3C2410_PA_UART1 + 0x3fff,
  48. .flags = IORESOURCE_MEM,
  49. },
  50. [1] = {
  51. .start = IRQ_S3CUART_RX1,
  52. .end = IRQ_S3CUART_ERR1,
  53. .flags = IORESOURCE_IRQ,
  54. }
  55. };
  56. static struct resource s3c2410_uart2_resource[] = {
  57. [0] = {
  58. .start = S3C2410_PA_UART2,
  59. .end = S3C2410_PA_UART2 + 0x3fff,
  60. .flags = IORESOURCE_MEM,
  61. },
  62. [1] = {
  63. .start = IRQ_S3CUART_RX2,
  64. .end = IRQ_S3CUART_ERR2,
  65. .flags = IORESOURCE_IRQ,
  66. }
  67. };
  68. struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
  69. [0] = {
  70. .resources = s3c2410_uart0_resource,
  71. .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
  72. },
  73. [1] = {
  74. .resources = s3c2410_uart1_resource,
  75. .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
  76. },
  77. [2] = {
  78. .resources = s3c2410_uart2_resource,
  79. .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
  80. },
  81. };
  82. /* yart devices */
  83. static struct platform_device s3c24xx_uart_device0 = {
  84. .id = 0,
  85. };
  86. static struct platform_device s3c24xx_uart_device1 = {
  87. .id = 1,
  88. };
  89. static struct platform_device s3c24xx_uart_device2 = {
  90. .id = 2,
  91. };
  92. struct platform_device *s3c24xx_uart_src[3] = {
  93. &s3c24xx_uart_device0,
  94. &s3c24xx_uart_device1,
  95. &s3c24xx_uart_device2,
  96. };
  97. struct platform_device *s3c24xx_uart_devs[3] = {
  98. };
  99. /* USB Host Controller */
  100. static struct resource s3c_usb_resource[] = {
  101. [0] = {
  102. .start = S3C24XX_PA_USBHOST,
  103. .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
  104. .flags = IORESOURCE_MEM,
  105. },
  106. [1] = {
  107. .start = IRQ_USBH,
  108. .end = IRQ_USBH,
  109. .flags = IORESOURCE_IRQ,
  110. }
  111. };
  112. static u64 s3c_device_usb_dmamask = 0xffffffffUL;
  113. struct platform_device s3c_device_usb = {
  114. .name = "s3c2410-ohci",
  115. .id = -1,
  116. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  117. .resource = s3c_usb_resource,
  118. .dev = {
  119. .dma_mask = &s3c_device_usb_dmamask,
  120. .coherent_dma_mask = 0xffffffffUL
  121. }
  122. };
  123. EXPORT_SYMBOL(s3c_device_usb);
  124. /* LCD Controller */
  125. static struct resource s3c_lcd_resource[] = {
  126. [0] = {
  127. .start = S3C24XX_PA_LCD,
  128. .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
  129. .flags = IORESOURCE_MEM,
  130. },
  131. [1] = {
  132. .start = IRQ_LCD,
  133. .end = IRQ_LCD,
  134. .flags = IORESOURCE_IRQ,
  135. }
  136. };
  137. static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
  138. struct platform_device s3c_device_lcd = {
  139. .name = "s3c2410-lcd",
  140. .id = -1,
  141. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  142. .resource = s3c_lcd_resource,
  143. .dev = {
  144. .dma_mask = &s3c_device_lcd_dmamask,
  145. .coherent_dma_mask = 0xffffffffUL
  146. }
  147. };
  148. EXPORT_SYMBOL(s3c_device_lcd);
  149. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  150. {
  151. struct s3c2410fb_mach_info *npd;
  152. npd = kmalloc(sizeof(*npd), GFP_KERNEL);
  153. if (npd) {
  154. memcpy(npd, pd, sizeof(*npd));
  155. s3c_device_lcd.dev.platform_data = npd;
  156. } else {
  157. printk(KERN_ERR "no memory for LCD platform data\n");
  158. }
  159. }
  160. /* NAND Controller */
  161. static struct resource s3c_nand_resource[] = {
  162. [0] = {
  163. .start = S3C2410_PA_NAND,
  164. .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
  165. .flags = IORESOURCE_MEM,
  166. }
  167. };
  168. struct platform_device s3c_device_nand = {
  169. .name = "s3c2410-nand",
  170. .id = -1,
  171. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  172. .resource = s3c_nand_resource,
  173. };
  174. EXPORT_SYMBOL(s3c_device_nand);
  175. /* USB Device (Gadget)*/
  176. static struct resource s3c_usbgadget_resource[] = {
  177. [0] = {
  178. .start = S3C24XX_PA_USBDEV,
  179. .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
  180. .flags = IORESOURCE_MEM,
  181. },
  182. [1] = {
  183. .start = IRQ_USBD,
  184. .end = IRQ_USBD,
  185. .flags = IORESOURCE_IRQ,
  186. }
  187. };
  188. struct platform_device s3c_device_usbgadget = {
  189. .name = "s3c2410-usbgadget",
  190. .id = -1,
  191. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  192. .resource = s3c_usbgadget_resource,
  193. };
  194. EXPORT_SYMBOL(s3c_device_usbgadget);
  195. /* Watchdog */
  196. static struct resource s3c_wdt_resource[] = {
  197. [0] = {
  198. .start = S3C24XX_PA_WATCHDOG,
  199. .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
  200. .flags = IORESOURCE_MEM,
  201. },
  202. [1] = {
  203. .start = IRQ_WDT,
  204. .end = IRQ_WDT,
  205. .flags = IORESOURCE_IRQ,
  206. }
  207. };
  208. struct platform_device s3c_device_wdt = {
  209. .name = "s3c2410-wdt",
  210. .id = -1,
  211. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  212. .resource = s3c_wdt_resource,
  213. };
  214. EXPORT_SYMBOL(s3c_device_wdt);
  215. /* I2C */
  216. static struct resource s3c_i2c_resource[] = {
  217. [0] = {
  218. .start = S3C24XX_PA_IIC,
  219. .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
  220. .flags = IORESOURCE_MEM,
  221. },
  222. [1] = {
  223. .start = IRQ_IIC,
  224. .end = IRQ_IIC,
  225. .flags = IORESOURCE_IRQ,
  226. }
  227. };
  228. struct platform_device s3c_device_i2c = {
  229. .name = "s3c2410-i2c",
  230. .id = -1,
  231. .num_resources = ARRAY_SIZE(s3c_i2c_resource),
  232. .resource = s3c_i2c_resource,
  233. };
  234. EXPORT_SYMBOL(s3c_device_i2c);
  235. /* IIS */
  236. static struct resource s3c_iis_resource[] = {
  237. [0] = {
  238. .start = S3C24XX_PA_IIS,
  239. .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
  240. .flags = IORESOURCE_MEM,
  241. }
  242. };
  243. static u64 s3c_device_iis_dmamask = 0xffffffffUL;
  244. struct platform_device s3c_device_iis = {
  245. .name = "s3c2410-iis",
  246. .id = -1,
  247. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  248. .resource = s3c_iis_resource,
  249. .dev = {
  250. .dma_mask = &s3c_device_iis_dmamask,
  251. .coherent_dma_mask = 0xffffffffUL
  252. }
  253. };
  254. EXPORT_SYMBOL(s3c_device_iis);
  255. /* RTC */
  256. static struct resource s3c_rtc_resource[] = {
  257. [0] = {
  258. .start = S3C24XX_PA_RTC,
  259. .end = S3C24XX_PA_RTC + 0xff,
  260. .flags = IORESOURCE_MEM,
  261. },
  262. [1] = {
  263. .start = IRQ_RTC,
  264. .end = IRQ_RTC,
  265. .flags = IORESOURCE_IRQ,
  266. },
  267. [2] = {
  268. .start = IRQ_TICK,
  269. .end = IRQ_TICK,
  270. .flags = IORESOURCE_IRQ
  271. }
  272. };
  273. struct platform_device s3c_device_rtc = {
  274. .name = "s3c2410-rtc",
  275. .id = -1,
  276. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  277. .resource = s3c_rtc_resource,
  278. };
  279. EXPORT_SYMBOL(s3c_device_rtc);
  280. /* ADC */
  281. static struct resource s3c_adc_resource[] = {
  282. [0] = {
  283. .start = S3C24XX_PA_ADC,
  284. .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
  285. .flags = IORESOURCE_MEM,
  286. },
  287. [1] = {
  288. .start = IRQ_TC,
  289. .end = IRQ_TC,
  290. .flags = IORESOURCE_IRQ,
  291. },
  292. [2] = {
  293. .start = IRQ_ADC,
  294. .end = IRQ_ADC,
  295. .flags = IORESOURCE_IRQ,
  296. }
  297. };
  298. struct platform_device s3c_device_adc = {
  299. .name = "s3c2410-adc",
  300. .id = -1,
  301. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  302. .resource = s3c_adc_resource,
  303. };
  304. /* SDI */
  305. static struct resource s3c_sdi_resource[] = {
  306. [0] = {
  307. .start = S3C2410_PA_SDI,
  308. .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
  309. .flags = IORESOURCE_MEM,
  310. },
  311. [1] = {
  312. .start = IRQ_SDI,
  313. .end = IRQ_SDI,
  314. .flags = IORESOURCE_IRQ,
  315. }
  316. };
  317. struct platform_device s3c_device_sdi = {
  318. .name = "s3c2410-sdi",
  319. .id = -1,
  320. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  321. .resource = s3c_sdi_resource,
  322. };
  323. EXPORT_SYMBOL(s3c_device_sdi);
  324. /* SPI (0) */
  325. static struct resource s3c_spi0_resource[] = {
  326. [0] = {
  327. .start = S3C24XX_PA_SPI,
  328. .end = S3C24XX_PA_SPI + 0x1f,
  329. .flags = IORESOURCE_MEM,
  330. },
  331. [1] = {
  332. .start = IRQ_SPI0,
  333. .end = IRQ_SPI0,
  334. .flags = IORESOURCE_IRQ,
  335. }
  336. };
  337. static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
  338. struct platform_device s3c_device_spi0 = {
  339. .name = "s3c2410-spi",
  340. .id = 0,
  341. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  342. .resource = s3c_spi0_resource,
  343. .dev = {
  344. .dma_mask = &s3c_device_spi0_dmamask,
  345. .coherent_dma_mask = 0xffffffffUL
  346. }
  347. };
  348. EXPORT_SYMBOL(s3c_device_spi0);
  349. /* SPI (1) */
  350. static struct resource s3c_spi1_resource[] = {
  351. [0] = {
  352. .start = S3C24XX_PA_SPI + 0x20,
  353. .end = S3C24XX_PA_SPI + 0x20 + 0x1f,
  354. .flags = IORESOURCE_MEM,
  355. },
  356. [1] = {
  357. .start = IRQ_SPI1,
  358. .end = IRQ_SPI1,
  359. .flags = IORESOURCE_IRQ,
  360. }
  361. };
  362. static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
  363. struct platform_device s3c_device_spi1 = {
  364. .name = "s3c2410-spi",
  365. .id = 1,
  366. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  367. .resource = s3c_spi1_resource,
  368. .dev = {
  369. .dma_mask = &s3c_device_spi1_dmamask,
  370. .coherent_dma_mask = 0xffffffffUL
  371. }
  372. };
  373. EXPORT_SYMBOL(s3c_device_spi1);
  374. /* pwm timer blocks */
  375. static struct resource s3c_timer0_resource[] = {
  376. [0] = {
  377. .start = S3C24XX_PA_TIMER + 0x0C,
  378. .end = S3C24XX_PA_TIMER + 0x0C + 0xB,
  379. .flags = IORESOURCE_MEM,
  380. },
  381. [1] = {
  382. .start = IRQ_TIMER0,
  383. .end = IRQ_TIMER0,
  384. .flags = IORESOURCE_IRQ,
  385. }
  386. };
  387. struct platform_device s3c_device_timer0 = {
  388. .name = "s3c2410-timer",
  389. .id = 0,
  390. .num_resources = ARRAY_SIZE(s3c_timer0_resource),
  391. .resource = s3c_timer0_resource,
  392. };
  393. EXPORT_SYMBOL(s3c_device_timer0);
  394. /* timer 1 */
  395. static struct resource s3c_timer1_resource[] = {
  396. [0] = {
  397. .start = S3C24XX_PA_TIMER + 0x18,
  398. .end = S3C24XX_PA_TIMER + 0x23,
  399. .flags = IORESOURCE_MEM,
  400. },
  401. [1] = {
  402. .start = IRQ_TIMER1,
  403. .end = IRQ_TIMER1,
  404. .flags = IORESOURCE_IRQ,
  405. }
  406. };
  407. struct platform_device s3c_device_timer1 = {
  408. .name = "s3c2410-timer",
  409. .id = 1,
  410. .num_resources = ARRAY_SIZE(s3c_timer1_resource),
  411. .resource = s3c_timer1_resource,
  412. };
  413. EXPORT_SYMBOL(s3c_device_timer1);
  414. /* timer 2 */
  415. static struct resource s3c_timer2_resource[] = {
  416. [0] = {
  417. .start = S3C24XX_PA_TIMER + 0x24,
  418. .end = S3C24XX_PA_TIMER + 0x2F,
  419. .flags = IORESOURCE_MEM,
  420. },
  421. [1] = {
  422. .start = IRQ_TIMER2,
  423. .end = IRQ_TIMER2,
  424. .flags = IORESOURCE_IRQ,
  425. }
  426. };
  427. struct platform_device s3c_device_timer2 = {
  428. .name = "s3c2410-timer",
  429. .id = 2,
  430. .num_resources = ARRAY_SIZE(s3c_timer2_resource),
  431. .resource = s3c_timer2_resource,
  432. };
  433. EXPORT_SYMBOL(s3c_device_timer2);
  434. /* timer 3 */
  435. static struct resource s3c_timer3_resource[] = {
  436. [0] = {
  437. .start = S3C24XX_PA_TIMER + 0x30,
  438. .end = S3C24XX_PA_TIMER + 0x3B,
  439. .flags = IORESOURCE_MEM,
  440. },
  441. [1] = {
  442. .start = IRQ_TIMER3,
  443. .end = IRQ_TIMER3,
  444. .flags = IORESOURCE_IRQ,
  445. }
  446. };
  447. struct platform_device s3c_device_timer3 = {
  448. .name = "s3c2410-timer",
  449. .id = 3,
  450. .num_resources = ARRAY_SIZE(s3c_timer3_resource),
  451. .resource = s3c_timer3_resource,
  452. };
  453. EXPORT_SYMBOL(s3c_device_timer3);
  454. #ifdef CONFIG_CPU_S3C2440
  455. /* Camif Controller */
  456. static struct resource s3c_camif_resource[] = {
  457. [0] = {
  458. .start = S3C2440_PA_CAMIF,
  459. .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
  460. .flags = IORESOURCE_MEM,
  461. },
  462. [1] = {
  463. .start = IRQ_CAM,
  464. .end = IRQ_CAM,
  465. .flags = IORESOURCE_IRQ,
  466. }
  467. };
  468. static u64 s3c_device_camif_dmamask = 0xffffffffUL;
  469. struct platform_device s3c_device_camif = {
  470. .name = "s3c2440-camif",
  471. .id = -1,
  472. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  473. .resource = s3c_camif_resource,
  474. .dev = {
  475. .dma_mask = &s3c_device_camif_dmamask,
  476. .coherent_dma_mask = 0xffffffffUL
  477. }
  478. };
  479. EXPORT_SYMBOL(s3c_device_camif);
  480. #endif // CONFIG_CPU_S32440