at91sam9261.c 6.7 KB

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  1. /*
  2. * arch/arm/mach-at91rm9200/at91sam9261.c
  3. *
  4. * Copyright (C) 2005 SAN People
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. */
  12. #include <linux/module.h>
  13. #include <asm/mach/arch.h>
  14. #include <asm/mach/map.h>
  15. #include <asm/arch/at91sam9261.h>
  16. #include <asm/arch/at91_pmc.h>
  17. #include <asm/arch/at91_rstc.h>
  18. #include "generic.h"
  19. #include "clock.h"
  20. static struct map_desc at91sam9261_io_desc[] __initdata = {
  21. {
  22. .virtual = AT91_VA_BASE_SYS,
  23. .pfn = __phys_to_pfn(AT91_BASE_SYS),
  24. .length = SZ_16K,
  25. .type = MT_DEVICE,
  26. }, {
  27. .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
  28. .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
  29. .length = AT91SAM9261_SRAM_SIZE,
  30. .type = MT_DEVICE,
  31. },
  32. };
  33. /* --------------------------------------------------------------------
  34. * Clocks
  35. * -------------------------------------------------------------------- */
  36. /*
  37. * The peripheral clocks.
  38. */
  39. static struct clk pioA_clk = {
  40. .name = "pioA_clk",
  41. .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
  42. .type = CLK_TYPE_PERIPHERAL,
  43. };
  44. static struct clk pioB_clk = {
  45. .name = "pioB_clk",
  46. .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
  47. .type = CLK_TYPE_PERIPHERAL,
  48. };
  49. static struct clk pioC_clk = {
  50. .name = "pioC_clk",
  51. .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
  52. .type = CLK_TYPE_PERIPHERAL,
  53. };
  54. static struct clk usart0_clk = {
  55. .name = "usart0_clk",
  56. .pmc_mask = 1 << AT91SAM9261_ID_US0,
  57. .type = CLK_TYPE_PERIPHERAL,
  58. };
  59. static struct clk usart1_clk = {
  60. .name = "usart1_clk",
  61. .pmc_mask = 1 << AT91SAM9261_ID_US1,
  62. .type = CLK_TYPE_PERIPHERAL,
  63. };
  64. static struct clk usart2_clk = {
  65. .name = "usart2_clk",
  66. .pmc_mask = 1 << AT91SAM9261_ID_US2,
  67. .type = CLK_TYPE_PERIPHERAL,
  68. };
  69. static struct clk mmc_clk = {
  70. .name = "mci_clk",
  71. .pmc_mask = 1 << AT91SAM9261_ID_MCI,
  72. .type = CLK_TYPE_PERIPHERAL,
  73. };
  74. static struct clk udc_clk = {
  75. .name = "udc_clk",
  76. .pmc_mask = 1 << AT91SAM9261_ID_UDP,
  77. .type = CLK_TYPE_PERIPHERAL,
  78. };
  79. static struct clk twi_clk = {
  80. .name = "twi_clk",
  81. .pmc_mask = 1 << AT91SAM9261_ID_TWI,
  82. .type = CLK_TYPE_PERIPHERAL,
  83. };
  84. static struct clk spi0_clk = {
  85. .name = "spi0_clk",
  86. .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
  87. .type = CLK_TYPE_PERIPHERAL,
  88. };
  89. static struct clk spi1_clk = {
  90. .name = "spi1_clk",
  91. .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
  92. .type = CLK_TYPE_PERIPHERAL,
  93. };
  94. static struct clk ohci_clk = {
  95. .name = "ohci_clk",
  96. .pmc_mask = 1 << AT91SAM9261_ID_UHP,
  97. .type = CLK_TYPE_PERIPHERAL,
  98. };
  99. static struct clk lcdc_clk = {
  100. .name = "lcdc_clk",
  101. .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
  102. .type = CLK_TYPE_PERIPHERAL,
  103. };
  104. static struct clk *periph_clocks[] __initdata = {
  105. &pioA_clk,
  106. &pioB_clk,
  107. &pioC_clk,
  108. &usart0_clk,
  109. &usart1_clk,
  110. &usart2_clk,
  111. &mmc_clk,
  112. &udc_clk,
  113. &twi_clk,
  114. &spi0_clk,
  115. &spi1_clk,
  116. // ssc 0 .. ssc2
  117. // tc0 .. tc2
  118. &ohci_clk,
  119. &lcdc_clk,
  120. // irq0 .. irq2
  121. };
  122. /*
  123. * The four programmable clocks.
  124. * You must configure pin multiplexing to bring these signals out.
  125. */
  126. static struct clk pck0 = {
  127. .name = "pck0",
  128. .pmc_mask = AT91_PMC_PCK0,
  129. .type = CLK_TYPE_PROGRAMMABLE,
  130. .id = 0,
  131. };
  132. static struct clk pck1 = {
  133. .name = "pck1",
  134. .pmc_mask = AT91_PMC_PCK1,
  135. .type = CLK_TYPE_PROGRAMMABLE,
  136. .id = 1,
  137. };
  138. static struct clk pck2 = {
  139. .name = "pck2",
  140. .pmc_mask = AT91_PMC_PCK2,
  141. .type = CLK_TYPE_PROGRAMMABLE,
  142. .id = 2,
  143. };
  144. static struct clk pck3 = {
  145. .name = "pck3",
  146. .pmc_mask = AT91_PMC_PCK3,
  147. .type = CLK_TYPE_PROGRAMMABLE,
  148. .id = 3,
  149. };
  150. /* HClocks */
  151. static struct clk hck0 = {
  152. .name = "hck0",
  153. .pmc_mask = AT91_PMC_HCK0,
  154. .type = CLK_TYPE_SYSTEM,
  155. .id = 0,
  156. };
  157. static struct clk hck1 = {
  158. .name = "hck1",
  159. .pmc_mask = AT91_PMC_HCK1,
  160. .type = CLK_TYPE_SYSTEM,
  161. .id = 1,
  162. };
  163. static void __init at91sam9261_register_clocks(void)
  164. {
  165. int i;
  166. for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
  167. clk_register(periph_clocks[i]);
  168. clk_register(&pck0);
  169. clk_register(&pck1);
  170. clk_register(&pck2);
  171. clk_register(&pck3);
  172. clk_register(&hck0);
  173. clk_register(&hck1);
  174. }
  175. /* --------------------------------------------------------------------
  176. * GPIO
  177. * -------------------------------------------------------------------- */
  178. static struct at91_gpio_bank at91sam9261_gpio[] = {
  179. {
  180. .id = AT91SAM9261_ID_PIOA,
  181. .offset = AT91_PIOA,
  182. .clock = &pioA_clk,
  183. }, {
  184. .id = AT91SAM9261_ID_PIOB,
  185. .offset = AT91_PIOB,
  186. .clock = &pioB_clk,
  187. }, {
  188. .id = AT91SAM9261_ID_PIOC,
  189. .offset = AT91_PIOC,
  190. .clock = &pioC_clk,
  191. }
  192. };
  193. static void at91sam9261_reset(void)
  194. {
  195. at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
  196. }
  197. /* --------------------------------------------------------------------
  198. * AT91SAM9261 processor initialization
  199. * -------------------------------------------------------------------- */
  200. void __init at91sam9261_initialize(unsigned long main_clock)
  201. {
  202. /* Map peripherals */
  203. iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
  204. at91_arch_reset = at91sam9261_reset;
  205. at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
  206. | (1 << AT91SAM9261_ID_IRQ2);
  207. /* Init clock subsystem */
  208. at91_clock_init(main_clock);
  209. /* Register the processor-specific clocks */
  210. at91sam9261_register_clocks();
  211. /* Register GPIO subsystem */
  212. at91_gpio_init(at91sam9261_gpio, 3);
  213. }
  214. /* --------------------------------------------------------------------
  215. * Interrupt initialization
  216. * -------------------------------------------------------------------- */
  217. /*
  218. * The default interrupt priority levels (0 = lowest, 7 = highest).
  219. */
  220. static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
  221. 7, /* Advanced Interrupt Controller */
  222. 7, /* System Peripherals */
  223. 0, /* Parallel IO Controller A */
  224. 0, /* Parallel IO Controller B */
  225. 0, /* Parallel IO Controller C */
  226. 0,
  227. 6, /* USART 0 */
  228. 6, /* USART 1 */
  229. 6, /* USART 2 */
  230. 0, /* Multimedia Card Interface */
  231. 4, /* USB Device Port */
  232. 0, /* Two-Wire Interface */
  233. 6, /* Serial Peripheral Interface 0 */
  234. 6, /* Serial Peripheral Interface 1 */
  235. 5, /* Serial Synchronous Controller 0 */
  236. 5, /* Serial Synchronous Controller 1 */
  237. 5, /* Serial Synchronous Controller 2 */
  238. 0, /* Timer Counter 0 */
  239. 0, /* Timer Counter 1 */
  240. 0, /* Timer Counter 2 */
  241. 3, /* USB Host port */
  242. 3, /* LCD Controller */
  243. 0,
  244. 0,
  245. 0,
  246. 0,
  247. 0,
  248. 0,
  249. 0,
  250. 0, /* Advanced Interrupt Controller */
  251. 0, /* Advanced Interrupt Controller */
  252. 0, /* Advanced Interrupt Controller */
  253. };
  254. void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
  255. {
  256. if (!priority)
  257. priority = at91sam9261_default_irq_priority;
  258. /* Initialize the AIC interrupt controller */
  259. at91_aic_init(priority);
  260. /* Enable GPIO interrupts */
  261. at91_gpio_irq_setup();
  262. }