sys_nautilus.c 6.2 KB

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  1. /*
  2. * linux/arch/alpha/kernel/sys_nautilus.c
  3. *
  4. * Copyright (C) 1995 David A Rusling
  5. * Copyright (C) 1998 Richard Henderson
  6. * Copyright (C) 1999 Alpha Processor, Inc.,
  7. * (David Daniel, Stig Telfer, Soohoon Lee)
  8. *
  9. * Code supporting NAUTILUS systems.
  10. *
  11. *
  12. * NAUTILUS has the following I/O features:
  13. *
  14. * a) Driven by AMD 751 aka IRONGATE (northbridge):
  15. * 4 PCI slots
  16. * 1 AGP slot
  17. *
  18. * b) Driven by ALI M1543C (southbridge)
  19. * 2 ISA slots
  20. * 2 IDE connectors
  21. * 1 dual drive capable FDD controller
  22. * 2 serial ports
  23. * 1 ECP/EPP/SP parallel port
  24. * 2 USB ports
  25. */
  26. #include <linux/kernel.h>
  27. #include <linux/types.h>
  28. #include <linux/mm.h>
  29. #include <linux/sched.h>
  30. #include <linux/pci.h>
  31. #include <linux/init.h>
  32. #include <linux/reboot.h>
  33. #include <linux/bootmem.h>
  34. #include <linux/bitops.h>
  35. #include <asm/ptrace.h>
  36. #include <asm/system.h>
  37. #include <asm/dma.h>
  38. #include <asm/irq.h>
  39. #include <asm/mmu_context.h>
  40. #include <asm/io.h>
  41. #include <asm/pci.h>
  42. #include <asm/pgtable.h>
  43. #include <asm/core_irongate.h>
  44. #include <asm/hwrpb.h>
  45. #include <asm/tlbflush.h>
  46. #include "proto.h"
  47. #include "err_impl.h"
  48. #include "irq_impl.h"
  49. #include "pci_impl.h"
  50. #include "machvec_impl.h"
  51. static void __init
  52. nautilus_init_irq(void)
  53. {
  54. if (alpha_using_srm) {
  55. alpha_mv.device_interrupt = srm_device_interrupt;
  56. }
  57. init_i8259a_irqs();
  58. common_init_isa_dma();
  59. }
  60. static int __init
  61. nautilus_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  62. {
  63. /* Preserve the IRQ set up by the console. */
  64. u8 irq;
  65. pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
  66. return irq;
  67. }
  68. void
  69. nautilus_kill_arch(int mode)
  70. {
  71. struct pci_bus *bus = pci_isa_hose->bus;
  72. u32 pmuport;
  73. int off;
  74. switch (mode) {
  75. case LINUX_REBOOT_CMD_RESTART:
  76. if (! alpha_using_srm) {
  77. u8 t8;
  78. pci_bus_read_config_byte(bus, 0x38, 0x43, &t8);
  79. pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80);
  80. outb(1, 0x92);
  81. outb(0, 0x92);
  82. /* NOTREACHED */
  83. }
  84. break;
  85. case LINUX_REBOOT_CMD_POWER_OFF:
  86. /* Assume M1543C */
  87. off = 0x2000; /* SLP_TYPE = 0, SLP_EN = 1 */
  88. pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport);
  89. if (!pmuport) {
  90. /* M1535D/D+ */
  91. off = 0x3400; /* SLP_TYPE = 5, SLP_EN = 1 */
  92. pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport);
  93. }
  94. pmuport &= 0xfffe;
  95. outw(0xffff, pmuport); /* Clear pending events. */
  96. outw(off, pmuport + 4);
  97. /* NOTREACHED */
  98. break;
  99. }
  100. }
  101. /* Perform analysis of a machine check that arrived from the system (NMI) */
  102. static void
  103. naut_sys_machine_check(unsigned long vector, unsigned long la_ptr,
  104. struct pt_regs *regs)
  105. {
  106. printk("PC %lx RA %lx\n", regs->pc, regs->r26);
  107. irongate_pci_clr_err();
  108. }
  109. /* Machine checks can come from two sources - those on the CPU and those
  110. in the system. They are analysed separately but all starts here. */
  111. void
  112. nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
  113. {
  114. char *mchk_class;
  115. /* Now for some analysis. Machine checks fall into two classes --
  116. those picked up by the system, and those picked up by the CPU.
  117. Add to that the two levels of severity - correctable or not. */
  118. if (vector == SCB_Q_SYSMCHK
  119. && ((IRONGATE0->dramms & 0x300) == 0x300)) {
  120. unsigned long nmi_ctl;
  121. /* Clear ALI NMI */
  122. nmi_ctl = inb(0x61);
  123. nmi_ctl |= 0x0c;
  124. outb(nmi_ctl, 0x61);
  125. nmi_ctl &= ~0x0c;
  126. outb(nmi_ctl, 0x61);
  127. /* Write again clears error bits. */
  128. IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
  129. mb();
  130. IRONGATE0->stat_cmd;
  131. /* Write again clears error bits. */
  132. IRONGATE0->dramms = IRONGATE0->dramms;
  133. mb();
  134. IRONGATE0->dramms;
  135. draina();
  136. wrmces(0x7);
  137. mb();
  138. return;
  139. }
  140. if (vector == SCB_Q_SYSERR)
  141. mchk_class = "Correctable";
  142. else if (vector == SCB_Q_SYSMCHK)
  143. mchk_class = "Fatal";
  144. else {
  145. ev6_machine_check(vector, la_ptr);
  146. return;
  147. }
  148. printk(KERN_CRIT "NAUTILUS Machine check 0x%lx "
  149. "[%s System Machine Check (NMI)]\n",
  150. vector, mchk_class);
  151. naut_sys_machine_check(vector, la_ptr, get_irq_regs());
  152. /* Tell the PALcode to clear the machine check */
  153. draina();
  154. wrmces(0x7);
  155. mb();
  156. }
  157. extern void free_reserved_mem(void *, void *);
  158. static struct resource irongate_mem = {
  159. .name = "Irongate PCI MEM",
  160. .flags = IORESOURCE_MEM,
  161. };
  162. void __init
  163. nautilus_init_pci(void)
  164. {
  165. struct pci_controller *hose = hose_head;
  166. struct pci_bus *bus;
  167. struct pci_dev *irongate;
  168. unsigned long bus_align, bus_size, pci_mem;
  169. unsigned long memtop = max_low_pfn << PAGE_SHIFT;
  170. /* Scan our single hose. */
  171. bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
  172. hose->bus = bus;
  173. irongate = pci_get_bus_and_slot(0, 0);
  174. bus->self = irongate;
  175. bus->resource[1] = &irongate_mem;
  176. pci_bus_size_bridges(bus);
  177. /* IO port range. */
  178. bus->resource[0]->start = 0;
  179. bus->resource[0]->end = 0xffff;
  180. /* Set up PCI memory range - limit is hardwired to 0xffffffff,
  181. base must be at aligned to 16Mb. */
  182. bus_align = bus->resource[1]->start;
  183. bus_size = bus->resource[1]->end + 1 - bus_align;
  184. if (bus_align < 0x1000000UL)
  185. bus_align = 0x1000000UL;
  186. pci_mem = (0x100000000UL - bus_size) & -bus_align;
  187. bus->resource[1]->start = pci_mem;
  188. bus->resource[1]->end = 0xffffffffUL;
  189. if (request_resource(&iomem_resource, bus->resource[1]) < 0)
  190. printk(KERN_ERR "Failed to request MEM on hose 0\n");
  191. if (pci_mem < memtop)
  192. memtop = pci_mem;
  193. if (memtop > alpha_mv.min_mem_address) {
  194. free_reserved_mem(__va(alpha_mv.min_mem_address),
  195. __va(memtop));
  196. printk("nautilus_init_pci: %ldk freed\n",
  197. (memtop - alpha_mv.min_mem_address) >> 10);
  198. }
  199. if ((IRONGATE0->dev_vendor >> 16) > 0x7006) /* Albacore? */
  200. IRONGATE0->pci_mem = pci_mem;
  201. pci_bus_assign_resources(bus);
  202. pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
  203. }
  204. /*
  205. * The System Vectors
  206. */
  207. struct alpha_machine_vector nautilus_mv __initmv = {
  208. .vector_name = "Nautilus",
  209. DO_EV6_MMU,
  210. DO_DEFAULT_RTC,
  211. DO_IRONGATE_IO,
  212. .machine_check = nautilus_machine_check,
  213. .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
  214. .min_io_address = DEFAULT_IO_BASE,
  215. .min_mem_address = IRONGATE_DEFAULT_MEM_BASE,
  216. .nr_irqs = 16,
  217. .device_interrupt = isa_device_interrupt,
  218. .init_arch = irongate_init_arch,
  219. .init_irq = nautilus_init_irq,
  220. .init_rtc = common_init_rtc,
  221. .init_pci = nautilus_init_pci,
  222. .kill_arch = nautilus_kill_arch,
  223. .pci_map_irq = nautilus_map_irq,
  224. .pci_swizzle = common_swizzle,
  225. };
  226. ALIAS_MV(nautilus)