omap-mcpdm.c 14 KB

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  1. /*
  2. * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
  3. *
  4. * Copyright (C) 2009 - 2011 Texas Instruments
  5. *
  6. * Author: Misael Lopez Cruz <misael.lopez@ti.com>
  7. * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
  8. * Margarita Olaya <magi.olaya@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/err.h>
  31. #include <linux/io.h>
  32. #include <linux/irq.h>
  33. #include <linux/slab.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/of_device.h>
  36. #include <sound/core.h>
  37. #include <sound/pcm.h>
  38. #include <sound/pcm_params.h>
  39. #include <sound/soc.h>
  40. #include "omap-mcpdm.h"
  41. #include "omap-pcm.h"
  42. struct mcpdm_link_config {
  43. u32 link_mask; /* channel mask for the direction */
  44. u32 threshold; /* FIFO threshold */
  45. };
  46. struct omap_mcpdm {
  47. struct device *dev;
  48. unsigned long phys_base;
  49. void __iomem *io_base;
  50. int irq;
  51. struct mutex mutex;
  52. /* Playback/Capture configuration */
  53. struct mcpdm_link_config config[2];
  54. /* McPDM dn offsets for rx1, and 2 channels */
  55. u32 dn_rx_offset;
  56. /* McPDM needs to be restarted due to runtime reconfiguration */
  57. bool restart;
  58. };
  59. /*
  60. * Stream DMA parameters
  61. */
  62. static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
  63. {
  64. .name = "Audio playback",
  65. },
  66. {
  67. .name = "Audio capture",
  68. },
  69. };
  70. static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
  71. {
  72. __raw_writel(val, mcpdm->io_base + reg);
  73. }
  74. static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
  75. {
  76. return __raw_readl(mcpdm->io_base + reg);
  77. }
  78. #ifdef DEBUG
  79. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
  80. {
  81. dev_dbg(mcpdm->dev, "***********************\n");
  82. dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
  83. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
  84. dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
  85. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
  86. dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
  87. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
  88. dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
  89. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
  90. dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
  91. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
  92. dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
  93. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
  94. dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
  95. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
  96. dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
  97. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
  98. dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
  99. omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
  100. dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
  101. omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
  102. dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
  103. omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
  104. dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
  105. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
  106. dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
  107. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
  108. dev_dbg(mcpdm->dev, "***********************\n");
  109. }
  110. #else
  111. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
  112. #endif
  113. /*
  114. * Enables the transfer through the PDM interface to/from the Phoenix
  115. * codec by enabling the corresponding UP or DN channels.
  116. */
  117. static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
  118. {
  119. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  120. u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
  121. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  122. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  123. ctrl |= link_mask;
  124. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  125. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  126. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  127. }
  128. /*
  129. * Disables the transfer through the PDM interface to/from the Phoenix
  130. * codec by disabling the corresponding UP or DN channels.
  131. */
  132. static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
  133. {
  134. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  135. u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
  136. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  137. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  138. ctrl &= ~(link_mask);
  139. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  140. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  141. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  142. }
  143. /*
  144. * Is the physical McPDM interface active.
  145. */
  146. static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
  147. {
  148. return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
  149. (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
  150. }
  151. /*
  152. * Configures McPDM uplink, and downlink for audio.
  153. * This function should be called before omap_mcpdm_start.
  154. */
  155. static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
  156. {
  157. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
  158. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
  159. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  160. /* Enable DN RX1/2 offset cancellation feature, if configured */
  161. if (mcpdm->dn_rx_offset) {
  162. u32 dn_offset = mcpdm->dn_rx_offset;
  163. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  164. dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
  165. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  166. }
  167. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
  168. mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
  169. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
  170. mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
  171. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
  172. MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
  173. }
  174. /*
  175. * Cleans McPDM uplink, and downlink configuration.
  176. * This function should be called when the stream is closed.
  177. */
  178. static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
  179. {
  180. /* Disable irq request generation for downlink */
  181. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  182. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
  183. /* Disable DMA request generation for downlink */
  184. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
  185. /* Disable irq request generation for uplink */
  186. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  187. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  188. /* Disable DMA request generation for uplink */
  189. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
  190. /* Disable RX1/2 offset cancellation */
  191. if (mcpdm->dn_rx_offset)
  192. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
  193. }
  194. static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
  195. {
  196. struct omap_mcpdm *mcpdm = dev_id;
  197. int irq_status;
  198. irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
  199. /* Acknowledge irq event */
  200. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
  201. if (irq_status & MCPDM_DN_IRQ_FULL)
  202. dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
  203. if (irq_status & MCPDM_DN_IRQ_EMPTY)
  204. dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
  205. if (irq_status & MCPDM_DN_IRQ)
  206. dev_dbg(mcpdm->dev, "DN (playback) write request\n");
  207. if (irq_status & MCPDM_UP_IRQ_FULL)
  208. dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
  209. if (irq_status & MCPDM_UP_IRQ_EMPTY)
  210. dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
  211. if (irq_status & MCPDM_UP_IRQ)
  212. dev_dbg(mcpdm->dev, "UP (capture) write request\n");
  213. return IRQ_HANDLED;
  214. }
  215. static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
  216. struct snd_soc_dai *dai)
  217. {
  218. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  219. mutex_lock(&mcpdm->mutex);
  220. if (!dai->active) {
  221. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  222. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
  223. omap_mcpdm_open_streams(mcpdm);
  224. }
  225. mutex_unlock(&mcpdm->mutex);
  226. snd_soc_dai_set_dma_data(dai, substream,
  227. &omap_mcpdm_dai_dma_params[substream->stream]);
  228. return 0;
  229. }
  230. static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
  231. struct snd_soc_dai *dai)
  232. {
  233. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  234. mutex_lock(&mcpdm->mutex);
  235. if (!dai->active) {
  236. if (omap_mcpdm_active(mcpdm)) {
  237. omap_mcpdm_stop(mcpdm);
  238. omap_mcpdm_close_streams(mcpdm);
  239. mcpdm->config[0].link_mask = 0;
  240. mcpdm->config[1].link_mask = 0;
  241. }
  242. }
  243. mutex_unlock(&mcpdm->mutex);
  244. }
  245. static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
  246. struct snd_pcm_hw_params *params,
  247. struct snd_soc_dai *dai)
  248. {
  249. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  250. int stream = substream->stream;
  251. struct omap_pcm_dma_data *dma_data;
  252. u32 threshold;
  253. int channels;
  254. int link_mask = 0;
  255. channels = params_channels(params);
  256. switch (channels) {
  257. case 5:
  258. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  259. /* up to 3 channels for capture */
  260. return -EINVAL;
  261. link_mask |= 1 << 4;
  262. case 4:
  263. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  264. /* up to 3 channels for capture */
  265. return -EINVAL;
  266. link_mask |= 1 << 3;
  267. case 3:
  268. link_mask |= 1 << 2;
  269. case 2:
  270. link_mask |= 1 << 1;
  271. case 1:
  272. link_mask |= 1 << 0;
  273. break;
  274. default:
  275. /* unsupported number of channels */
  276. return -EINVAL;
  277. }
  278. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  279. threshold = mcpdm->config[stream].threshold;
  280. /* Configure McPDM channels, and DMA packet size */
  281. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  282. link_mask <<= 3;
  283. /* If capture is not running assume a stereo stream to come */
  284. if (!mcpdm->config[!stream].link_mask)
  285. mcpdm->config[!stream].link_mask = 0x3;
  286. dma_data->packet_size =
  287. (MCPDM_DN_THRES_MAX - threshold) * channels;
  288. } else {
  289. /* If playback is not running assume a stereo stream to come */
  290. if (!mcpdm->config[!stream].link_mask)
  291. mcpdm->config[!stream].link_mask = (0x3 << 3);
  292. dma_data->packet_size = threshold * channels;
  293. }
  294. /* Check if we need to restart McPDM with this stream */
  295. if (mcpdm->config[stream].link_mask &&
  296. mcpdm->config[stream].link_mask != link_mask)
  297. mcpdm->restart = true;
  298. mcpdm->config[stream].link_mask = link_mask;
  299. return 0;
  300. }
  301. static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
  302. struct snd_soc_dai *dai)
  303. {
  304. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  305. if (!omap_mcpdm_active(mcpdm)) {
  306. omap_mcpdm_start(mcpdm);
  307. omap_mcpdm_reg_dump(mcpdm);
  308. } else if (mcpdm->restart) {
  309. omap_mcpdm_stop(mcpdm);
  310. omap_mcpdm_start(mcpdm);
  311. mcpdm->restart = false;
  312. omap_mcpdm_reg_dump(mcpdm);
  313. }
  314. return 0;
  315. }
  316. static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
  317. .startup = omap_mcpdm_dai_startup,
  318. .shutdown = omap_mcpdm_dai_shutdown,
  319. .hw_params = omap_mcpdm_dai_hw_params,
  320. .prepare = omap_mcpdm_prepare,
  321. };
  322. static int omap_mcpdm_probe(struct snd_soc_dai *dai)
  323. {
  324. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  325. int ret;
  326. pm_runtime_enable(mcpdm->dev);
  327. /* Disable lines while request is ongoing */
  328. pm_runtime_get_sync(mcpdm->dev);
  329. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
  330. ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
  331. 0, "McPDM", (void *)mcpdm);
  332. pm_runtime_put_sync(mcpdm->dev);
  333. if (ret) {
  334. dev_err(mcpdm->dev, "Request for IRQ failed\n");
  335. pm_runtime_disable(mcpdm->dev);
  336. }
  337. /* Configure McPDM threshold values */
  338. mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
  339. mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
  340. MCPDM_UP_THRES_MAX - 3;
  341. return ret;
  342. }
  343. static int omap_mcpdm_remove(struct snd_soc_dai *dai)
  344. {
  345. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  346. pm_runtime_disable(mcpdm->dev);
  347. return 0;
  348. }
  349. #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  350. #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
  351. static struct snd_soc_dai_driver omap_mcpdm_dai = {
  352. .probe = omap_mcpdm_probe,
  353. .remove = omap_mcpdm_remove,
  354. .probe_order = SND_SOC_COMP_ORDER_LATE,
  355. .remove_order = SND_SOC_COMP_ORDER_EARLY,
  356. .playback = {
  357. .channels_min = 1,
  358. .channels_max = 5,
  359. .rates = OMAP_MCPDM_RATES,
  360. .formats = OMAP_MCPDM_FORMATS,
  361. .sig_bits = 24,
  362. },
  363. .capture = {
  364. .channels_min = 1,
  365. .channels_max = 3,
  366. .rates = OMAP_MCPDM_RATES,
  367. .formats = OMAP_MCPDM_FORMATS,
  368. .sig_bits = 24,
  369. },
  370. .ops = &omap_mcpdm_dai_ops,
  371. };
  372. void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
  373. u8 rx1, u8 rx2)
  374. {
  375. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  376. mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
  377. }
  378. EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
  379. static int asoc_mcpdm_probe(struct platform_device *pdev)
  380. {
  381. struct omap_mcpdm *mcpdm;
  382. struct resource *res;
  383. mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
  384. if (!mcpdm)
  385. return -ENOMEM;
  386. platform_set_drvdata(pdev, mcpdm);
  387. mutex_init(&mcpdm->mutex);
  388. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  389. if (res == NULL)
  390. return -ENOMEM;
  391. omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
  392. omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;
  393. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
  394. if (!res)
  395. return -ENODEV;
  396. omap_mcpdm_dai_dma_params[0].dma_req = res->start;
  397. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
  398. if (!res)
  399. return -ENODEV;
  400. omap_mcpdm_dai_dma_params[1].dma_req = res->start;
  401. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  402. if (res == NULL)
  403. return -ENOMEM;
  404. mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
  405. if (IS_ERR(mcpdm->io_base))
  406. return PTR_ERR(mcpdm->io_base);
  407. mcpdm->irq = platform_get_irq(pdev, 0);
  408. if (mcpdm->irq < 0)
  409. return mcpdm->irq;
  410. mcpdm->dev = &pdev->dev;
  411. return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
  412. }
  413. static int asoc_mcpdm_remove(struct platform_device *pdev)
  414. {
  415. snd_soc_unregister_dai(&pdev->dev);
  416. return 0;
  417. }
  418. static const struct of_device_id omap_mcpdm_of_match[] = {
  419. { .compatible = "ti,omap4-mcpdm", },
  420. { }
  421. };
  422. MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
  423. static struct platform_driver asoc_mcpdm_driver = {
  424. .driver = {
  425. .name = "omap-mcpdm",
  426. .owner = THIS_MODULE,
  427. .of_match_table = omap_mcpdm_of_match,
  428. },
  429. .probe = asoc_mcpdm_probe,
  430. .remove = asoc_mcpdm_remove,
  431. };
  432. module_platform_driver(asoc_mcpdm_driver);
  433. MODULE_ALIAS("platform:omap-mcpdm");
  434. MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
  435. MODULE_DESCRIPTION("OMAP PDM SoC Interface");
  436. MODULE_LICENSE("GPL");