proc.c 9.5 KB

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  1. /*
  2. * Procfs interface for the PCI bus.
  3. *
  4. * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
  5. */
  6. #include <linux/init.h>
  7. #include <linux/pci.h>
  8. #include <linux/slab.h>
  9. #include <linux/module.h>
  10. #include <linux/proc_fs.h>
  11. #include <linux/seq_file.h>
  12. #include <linux/capability.h>
  13. #include <asm/uaccess.h>
  14. #include <asm/byteorder.h>
  15. #include "pci.h"
  16. static int proc_initialized; /* = 0 */
  17. static loff_t
  18. proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
  19. {
  20. loff_t new = -1;
  21. struct inode *inode = file_inode(file);
  22. mutex_lock(&inode->i_mutex);
  23. switch (whence) {
  24. case 0:
  25. new = off;
  26. break;
  27. case 1:
  28. new = file->f_pos + off;
  29. break;
  30. case 2:
  31. new = inode->i_size + off;
  32. break;
  33. }
  34. if (new < 0 || new > inode->i_size)
  35. new = -EINVAL;
  36. else
  37. file->f_pos = new;
  38. mutex_unlock(&inode->i_mutex);
  39. return new;
  40. }
  41. static ssize_t
  42. proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
  43. {
  44. struct pci_dev *dev = PDE_DATA(file_inode(file));
  45. unsigned int pos = *ppos;
  46. unsigned int cnt, size;
  47. /*
  48. * Normal users can read only the standardized portion of the
  49. * configuration space as several chips lock up when trying to read
  50. * undefined locations (think of Intel PIIX4 as a typical example).
  51. */
  52. if (capable(CAP_SYS_ADMIN))
  53. size = dev->cfg_size;
  54. else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
  55. size = 128;
  56. else
  57. size = 64;
  58. if (pos >= size)
  59. return 0;
  60. if (nbytes >= size)
  61. nbytes = size;
  62. if (pos + nbytes > size)
  63. nbytes = size - pos;
  64. cnt = nbytes;
  65. if (!access_ok(VERIFY_WRITE, buf, cnt))
  66. return -EINVAL;
  67. pci_config_pm_runtime_get(dev);
  68. if ((pos & 1) && cnt) {
  69. unsigned char val;
  70. pci_user_read_config_byte(dev, pos, &val);
  71. __put_user(val, buf);
  72. buf++;
  73. pos++;
  74. cnt--;
  75. }
  76. if ((pos & 3) && cnt > 2) {
  77. unsigned short val;
  78. pci_user_read_config_word(dev, pos, &val);
  79. __put_user(cpu_to_le16(val), (__le16 __user *) buf);
  80. buf += 2;
  81. pos += 2;
  82. cnt -= 2;
  83. }
  84. while (cnt >= 4) {
  85. unsigned int val;
  86. pci_user_read_config_dword(dev, pos, &val);
  87. __put_user(cpu_to_le32(val), (__le32 __user *) buf);
  88. buf += 4;
  89. pos += 4;
  90. cnt -= 4;
  91. }
  92. if (cnt >= 2) {
  93. unsigned short val;
  94. pci_user_read_config_word(dev, pos, &val);
  95. __put_user(cpu_to_le16(val), (__le16 __user *) buf);
  96. buf += 2;
  97. pos += 2;
  98. cnt -= 2;
  99. }
  100. if (cnt) {
  101. unsigned char val;
  102. pci_user_read_config_byte(dev, pos, &val);
  103. __put_user(val, buf);
  104. buf++;
  105. pos++;
  106. cnt--;
  107. }
  108. pci_config_pm_runtime_put(dev);
  109. *ppos = pos;
  110. return nbytes;
  111. }
  112. static ssize_t
  113. proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, loff_t *ppos)
  114. {
  115. struct inode *ino = file_inode(file);
  116. struct pci_dev *dev = PDE_DATA(ino);
  117. int pos = *ppos;
  118. int size = dev->cfg_size;
  119. int cnt;
  120. if (pos >= size)
  121. return 0;
  122. if (nbytes >= size)
  123. nbytes = size;
  124. if (pos + nbytes > size)
  125. nbytes = size - pos;
  126. cnt = nbytes;
  127. if (!access_ok(VERIFY_READ, buf, cnt))
  128. return -EINVAL;
  129. pci_config_pm_runtime_get(dev);
  130. if ((pos & 1) && cnt) {
  131. unsigned char val;
  132. __get_user(val, buf);
  133. pci_user_write_config_byte(dev, pos, val);
  134. buf++;
  135. pos++;
  136. cnt--;
  137. }
  138. if ((pos & 3) && cnt > 2) {
  139. __le16 val;
  140. __get_user(val, (__le16 __user *) buf);
  141. pci_user_write_config_word(dev, pos, le16_to_cpu(val));
  142. buf += 2;
  143. pos += 2;
  144. cnt -= 2;
  145. }
  146. while (cnt >= 4) {
  147. __le32 val;
  148. __get_user(val, (__le32 __user *) buf);
  149. pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
  150. buf += 4;
  151. pos += 4;
  152. cnt -= 4;
  153. }
  154. if (cnt >= 2) {
  155. __le16 val;
  156. __get_user(val, (__le16 __user *) buf);
  157. pci_user_write_config_word(dev, pos, le16_to_cpu(val));
  158. buf += 2;
  159. pos += 2;
  160. cnt -= 2;
  161. }
  162. if (cnt) {
  163. unsigned char val;
  164. __get_user(val, buf);
  165. pci_user_write_config_byte(dev, pos, val);
  166. buf++;
  167. pos++;
  168. cnt--;
  169. }
  170. pci_config_pm_runtime_put(dev);
  171. *ppos = pos;
  172. i_size_write(ino, dev->cfg_size);
  173. return nbytes;
  174. }
  175. struct pci_filp_private {
  176. enum pci_mmap_state mmap_state;
  177. int write_combine;
  178. };
  179. static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
  180. unsigned long arg)
  181. {
  182. struct pci_dev *dev = PDE_DATA(file_inode(file));
  183. #ifdef HAVE_PCI_MMAP
  184. struct pci_filp_private *fpriv = file->private_data;
  185. #endif /* HAVE_PCI_MMAP */
  186. int ret = 0;
  187. switch (cmd) {
  188. case PCIIOC_CONTROLLER:
  189. ret = pci_domain_nr(dev->bus);
  190. break;
  191. #ifdef HAVE_PCI_MMAP
  192. case PCIIOC_MMAP_IS_IO:
  193. fpriv->mmap_state = pci_mmap_io;
  194. break;
  195. case PCIIOC_MMAP_IS_MEM:
  196. fpriv->mmap_state = pci_mmap_mem;
  197. break;
  198. case PCIIOC_WRITE_COMBINE:
  199. if (arg)
  200. fpriv->write_combine = 1;
  201. else
  202. fpriv->write_combine = 0;
  203. break;
  204. #endif /* HAVE_PCI_MMAP */
  205. default:
  206. ret = -EINVAL;
  207. break;
  208. };
  209. return ret;
  210. }
  211. #ifdef HAVE_PCI_MMAP
  212. static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
  213. {
  214. struct pci_dev *dev = PDE_DATA(file_inode(file));
  215. struct pci_filp_private *fpriv = file->private_data;
  216. int i, ret;
  217. if (!capable(CAP_SYS_RAWIO))
  218. return -EPERM;
  219. /* Make sure the caller is mapping a real resource for this device */
  220. for (i = 0; i < PCI_ROM_RESOURCE; i++) {
  221. if (pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
  222. break;
  223. }
  224. if (i >= PCI_ROM_RESOURCE)
  225. return -ENODEV;
  226. ret = pci_mmap_page_range(dev, vma,
  227. fpriv->mmap_state,
  228. fpriv->write_combine);
  229. if (ret < 0)
  230. return ret;
  231. return 0;
  232. }
  233. static int proc_bus_pci_open(struct inode *inode, struct file *file)
  234. {
  235. struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
  236. if (!fpriv)
  237. return -ENOMEM;
  238. fpriv->mmap_state = pci_mmap_io;
  239. fpriv->write_combine = 0;
  240. file->private_data = fpriv;
  241. return 0;
  242. }
  243. static int proc_bus_pci_release(struct inode *inode, struct file *file)
  244. {
  245. kfree(file->private_data);
  246. file->private_data = NULL;
  247. return 0;
  248. }
  249. #endif /* HAVE_PCI_MMAP */
  250. static const struct file_operations proc_bus_pci_operations = {
  251. .owner = THIS_MODULE,
  252. .llseek = proc_bus_pci_lseek,
  253. .read = proc_bus_pci_read,
  254. .write = proc_bus_pci_write,
  255. .unlocked_ioctl = proc_bus_pci_ioctl,
  256. .compat_ioctl = proc_bus_pci_ioctl,
  257. #ifdef HAVE_PCI_MMAP
  258. .open = proc_bus_pci_open,
  259. .release = proc_bus_pci_release,
  260. .mmap = proc_bus_pci_mmap,
  261. #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
  262. .get_unmapped_area = get_pci_unmapped_area,
  263. #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
  264. #endif /* HAVE_PCI_MMAP */
  265. };
  266. /* iterator */
  267. static void *pci_seq_start(struct seq_file *m, loff_t *pos)
  268. {
  269. struct pci_dev *dev = NULL;
  270. loff_t n = *pos;
  271. for_each_pci_dev(dev) {
  272. if (!n--)
  273. break;
  274. }
  275. return dev;
  276. }
  277. static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
  278. {
  279. struct pci_dev *dev = v;
  280. (*pos)++;
  281. dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
  282. return dev;
  283. }
  284. static void pci_seq_stop(struct seq_file *m, void *v)
  285. {
  286. if (v) {
  287. struct pci_dev *dev = v;
  288. pci_dev_put(dev);
  289. }
  290. }
  291. static int show_device(struct seq_file *m, void *v)
  292. {
  293. const struct pci_dev *dev = v;
  294. const struct pci_driver *drv;
  295. int i;
  296. if (dev == NULL)
  297. return 0;
  298. drv = pci_dev_driver(dev);
  299. seq_printf(m, "%02x%02x\t%04x%04x\t%x",
  300. dev->bus->number,
  301. dev->devfn,
  302. dev->vendor,
  303. dev->device,
  304. dev->irq);
  305. /* only print standard and ROM resources to preserve compatibility */
  306. for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
  307. resource_size_t start, end;
  308. pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
  309. seq_printf(m, "\t%16llx",
  310. (unsigned long long)(start |
  311. (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
  312. }
  313. for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
  314. resource_size_t start, end;
  315. pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
  316. seq_printf(m, "\t%16llx",
  317. dev->resource[i].start < dev->resource[i].end ?
  318. (unsigned long long)(end - start) + 1 : 0);
  319. }
  320. seq_putc(m, '\t');
  321. if (drv)
  322. seq_printf(m, "%s", drv->name);
  323. seq_putc(m, '\n');
  324. return 0;
  325. }
  326. static const struct seq_operations proc_bus_pci_devices_op = {
  327. .start = pci_seq_start,
  328. .next = pci_seq_next,
  329. .stop = pci_seq_stop,
  330. .show = show_device
  331. };
  332. static struct proc_dir_entry *proc_bus_pci_dir;
  333. int pci_proc_attach_device(struct pci_dev *dev)
  334. {
  335. struct pci_bus *bus = dev->bus;
  336. struct proc_dir_entry *e;
  337. char name[16];
  338. if (!proc_initialized)
  339. return -EACCES;
  340. if (!bus->procdir) {
  341. if (pci_proc_domain(bus)) {
  342. sprintf(name, "%04x:%02x", pci_domain_nr(bus),
  343. bus->number);
  344. } else {
  345. sprintf(name, "%02x", bus->number);
  346. }
  347. bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
  348. if (!bus->procdir)
  349. return -ENOMEM;
  350. }
  351. sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
  352. e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
  353. &proc_bus_pci_operations, dev);
  354. if (!e)
  355. return -ENOMEM;
  356. proc_set_size(e, dev->cfg_size);
  357. dev->procent = e;
  358. return 0;
  359. }
  360. int pci_proc_detach_device(struct pci_dev *dev)
  361. {
  362. struct proc_dir_entry *e;
  363. if ((e = dev->procent)) {
  364. remove_proc_entry(e->name, dev->bus->procdir);
  365. dev->procent = NULL;
  366. }
  367. return 0;
  368. }
  369. int pci_proc_detach_bus(struct pci_bus* bus)
  370. {
  371. struct proc_dir_entry *de = bus->procdir;
  372. if (de)
  373. remove_proc_entry(de->name, proc_bus_pci_dir);
  374. return 0;
  375. }
  376. static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
  377. {
  378. return seq_open(file, &proc_bus_pci_devices_op);
  379. }
  380. static const struct file_operations proc_bus_pci_dev_operations = {
  381. .owner = THIS_MODULE,
  382. .open = proc_bus_pci_dev_open,
  383. .read = seq_read,
  384. .llseek = seq_lseek,
  385. .release = seq_release,
  386. };
  387. static int __init pci_proc_init(void)
  388. {
  389. struct pci_dev *dev = NULL;
  390. proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
  391. proc_create("devices", 0, proc_bus_pci_dir,
  392. &proc_bus_pci_dev_operations);
  393. proc_initialized = 1;
  394. for_each_pci_dev(dev)
  395. pci_proc_attach_device(dev);
  396. return 0;
  397. }
  398. device_initcall(pci_proc_init);