sa1100.c 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930
  1. /*
  2. * linux/drivers/char/sa1100.c
  3. *
  4. * Driver for SA11x0 serial ports
  5. *
  6. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  7. *
  8. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. * $Id: sa1100.c,v 1.50 2002/07/29 14:41:04 rmk Exp $
  25. *
  26. */
  27. #include <linux/config.h>
  28. #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  29. #define SUPPORT_SYSRQ
  30. #endif
  31. #include <linux/module.h>
  32. #include <linux/ioport.h>
  33. #include <linux/init.h>
  34. #include <linux/console.h>
  35. #include <linux/sysrq.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/tty.h>
  38. #include <linux/tty_flip.h>
  39. #include <linux/serial_core.h>
  40. #include <linux/serial.h>
  41. #include <asm/io.h>
  42. #include <asm/irq.h>
  43. #include <asm/hardware.h>
  44. #include <asm/mach/serial_sa1100.h>
  45. /* We've been assigned a range on the "Low-density serial ports" major */
  46. #define SERIAL_SA1100_MAJOR 204
  47. #define MINOR_START 5
  48. #define NR_PORTS 3
  49. #define SA1100_ISR_PASS_LIMIT 256
  50. /*
  51. * Convert from ignore_status_mask or read_status_mask to UTSR[01]
  52. */
  53. #define SM_TO_UTSR0(x) ((x) & 0xff)
  54. #define SM_TO_UTSR1(x) ((x) >> 8)
  55. #define UTSR0_TO_SM(x) ((x))
  56. #define UTSR1_TO_SM(x) ((x) << 8)
  57. #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
  58. #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
  59. #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
  60. #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
  61. #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
  62. #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
  63. #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
  64. #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
  65. #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
  66. #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
  67. #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
  68. #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
  69. #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
  70. #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
  71. /*
  72. * This is the size of our serial port register set.
  73. */
  74. #define UART_PORT_SIZE 0x24
  75. /*
  76. * This determines how often we check the modem status signals
  77. * for any change. They generally aren't connected to an IRQ
  78. * so we have to poll them. We also check immediately before
  79. * filling the TX fifo incase CTS has been dropped.
  80. */
  81. #define MCTRL_TIMEOUT (250*HZ/1000)
  82. struct sa1100_port {
  83. struct uart_port port;
  84. struct timer_list timer;
  85. unsigned int old_status;
  86. };
  87. /*
  88. * Handle any change of modem status signal since we were last called.
  89. */
  90. static void sa1100_mctrl_check(struct sa1100_port *sport)
  91. {
  92. unsigned int status, changed;
  93. status = sport->port.ops->get_mctrl(&sport->port);
  94. changed = status ^ sport->old_status;
  95. if (changed == 0)
  96. return;
  97. sport->old_status = status;
  98. if (changed & TIOCM_RI)
  99. sport->port.icount.rng++;
  100. if (changed & TIOCM_DSR)
  101. sport->port.icount.dsr++;
  102. if (changed & TIOCM_CAR)
  103. uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
  104. if (changed & TIOCM_CTS)
  105. uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
  106. wake_up_interruptible(&sport->port.info->delta_msr_wait);
  107. }
  108. /*
  109. * This is our per-port timeout handler, for checking the
  110. * modem status signals.
  111. */
  112. static void sa1100_timeout(unsigned long data)
  113. {
  114. struct sa1100_port *sport = (struct sa1100_port *)data;
  115. unsigned long flags;
  116. if (sport->port.info) {
  117. spin_lock_irqsave(&sport->port.lock, flags);
  118. sa1100_mctrl_check(sport);
  119. spin_unlock_irqrestore(&sport->port.lock, flags);
  120. mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
  121. }
  122. }
  123. /*
  124. * interrupts disabled on entry
  125. */
  126. static void sa1100_stop_tx(struct uart_port *port)
  127. {
  128. struct sa1100_port *sport = (struct sa1100_port *)port;
  129. u32 utcr3;
  130. utcr3 = UART_GET_UTCR3(sport);
  131. UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
  132. sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
  133. }
  134. /*
  135. * port locked and interrupts disabled
  136. */
  137. static void sa1100_start_tx(struct uart_port *port)
  138. {
  139. struct sa1100_port *sport = (struct sa1100_port *)port;
  140. unsigned long flags;
  141. u32 utcr3;
  142. utcr3 = UART_GET_UTCR3(sport);
  143. sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
  144. UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
  145. }
  146. /*
  147. * Interrupts enabled
  148. */
  149. static void sa1100_stop_rx(struct uart_port *port)
  150. {
  151. struct sa1100_port *sport = (struct sa1100_port *)port;
  152. u32 utcr3;
  153. utcr3 = UART_GET_UTCR3(sport);
  154. UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
  155. }
  156. /*
  157. * Set the modem control timer to fire immediately.
  158. */
  159. static void sa1100_enable_ms(struct uart_port *port)
  160. {
  161. struct sa1100_port *sport = (struct sa1100_port *)port;
  162. mod_timer(&sport->timer, jiffies);
  163. }
  164. static void
  165. sa1100_rx_chars(struct sa1100_port *sport, struct pt_regs *regs)
  166. {
  167. struct tty_struct *tty = sport->port.info->tty;
  168. unsigned int status, ch, flg;
  169. status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
  170. UTSR0_TO_SM(UART_GET_UTSR0(sport));
  171. while (status & UTSR1_TO_SM(UTSR1_RNE)) {
  172. ch = UART_GET_CHAR(sport);
  173. if (tty->flip.count >= TTY_FLIPBUF_SIZE)
  174. goto ignore_char;
  175. sport->port.icount.rx++;
  176. flg = TTY_NORMAL;
  177. /*
  178. * note that the error handling code is
  179. * out of the main execution path
  180. */
  181. if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
  182. if (status & UTSR1_TO_SM(UTSR1_PRE))
  183. sport->port.icount.parity++;
  184. else if (status & UTSR1_TO_SM(UTSR1_FRE))
  185. sport->port.icount.frame++;
  186. if (status & UTSR1_TO_SM(UTSR1_ROR))
  187. sport->port.icount.overrun++;
  188. status &= sport->port.read_status_mask;
  189. if (status & UTSR1_TO_SM(UTSR1_PRE))
  190. flg = TTY_PARITY;
  191. else if (status & UTSR1_TO_SM(UTSR1_FRE))
  192. flg = TTY_FRAME;
  193. #ifdef SUPPORT_SYSRQ
  194. sport->port.sysrq = 0;
  195. #endif
  196. }
  197. if (uart_handle_sysrq_char(&sport->port, ch, regs))
  198. goto ignore_char;
  199. uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
  200. ignore_char:
  201. status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
  202. UTSR0_TO_SM(UART_GET_UTSR0(sport));
  203. }
  204. tty_flip_buffer_push(tty);
  205. }
  206. static void sa1100_tx_chars(struct sa1100_port *sport)
  207. {
  208. struct circ_buf *xmit = &sport->port.info->xmit;
  209. if (sport->port.x_char) {
  210. UART_PUT_CHAR(sport, sport->port.x_char);
  211. sport->port.icount.tx++;
  212. sport->port.x_char = 0;
  213. return;
  214. }
  215. /*
  216. * Check the modem control lines before
  217. * transmitting anything.
  218. */
  219. sa1100_mctrl_check(sport);
  220. if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
  221. sa1100_stop_tx(&sport->port);
  222. return;
  223. }
  224. /*
  225. * Tried using FIFO (not checking TNF) for fifo fill:
  226. * still had the '4 bytes repeated' problem.
  227. */
  228. while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
  229. UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
  230. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  231. sport->port.icount.tx++;
  232. if (uart_circ_empty(xmit))
  233. break;
  234. }
  235. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  236. uart_write_wakeup(&sport->port);
  237. if (uart_circ_empty(xmit))
  238. sa1100_stop_tx(&sport->port);
  239. }
  240. static irqreturn_t sa1100_int(int irq, void *dev_id, struct pt_regs *regs)
  241. {
  242. struct sa1100_port *sport = dev_id;
  243. unsigned int status, pass_counter = 0;
  244. spin_lock(&sport->port.lock);
  245. status = UART_GET_UTSR0(sport);
  246. status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
  247. do {
  248. if (status & (UTSR0_RFS | UTSR0_RID)) {
  249. /* Clear the receiver idle bit, if set */
  250. if (status & UTSR0_RID)
  251. UART_PUT_UTSR0(sport, UTSR0_RID);
  252. sa1100_rx_chars(sport, regs);
  253. }
  254. /* Clear the relevant break bits */
  255. if (status & (UTSR0_RBB | UTSR0_REB))
  256. UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
  257. if (status & UTSR0_RBB)
  258. sport->port.icount.brk++;
  259. if (status & UTSR0_REB)
  260. uart_handle_break(&sport->port);
  261. if (status & UTSR0_TFS)
  262. sa1100_tx_chars(sport);
  263. if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
  264. break;
  265. status = UART_GET_UTSR0(sport);
  266. status &= SM_TO_UTSR0(sport->port.read_status_mask) |
  267. ~UTSR0_TFS;
  268. } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
  269. spin_unlock(&sport->port.lock);
  270. return IRQ_HANDLED;
  271. }
  272. /*
  273. * Return TIOCSER_TEMT when transmitter is not busy.
  274. */
  275. static unsigned int sa1100_tx_empty(struct uart_port *port)
  276. {
  277. struct sa1100_port *sport = (struct sa1100_port *)port;
  278. return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
  279. }
  280. static unsigned int sa1100_get_mctrl(struct uart_port *port)
  281. {
  282. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  283. }
  284. static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
  285. {
  286. }
  287. /*
  288. * Interrupts always disabled.
  289. */
  290. static void sa1100_break_ctl(struct uart_port *port, int break_state)
  291. {
  292. struct sa1100_port *sport = (struct sa1100_port *)port;
  293. unsigned long flags;
  294. unsigned int utcr3;
  295. spin_lock_irqsave(&sport->port.lock, flags);
  296. utcr3 = UART_GET_UTCR3(sport);
  297. if (break_state == -1)
  298. utcr3 |= UTCR3_BRK;
  299. else
  300. utcr3 &= ~UTCR3_BRK;
  301. UART_PUT_UTCR3(sport, utcr3);
  302. spin_unlock_irqrestore(&sport->port.lock, flags);
  303. }
  304. static int sa1100_startup(struct uart_port *port)
  305. {
  306. struct sa1100_port *sport = (struct sa1100_port *)port;
  307. int retval;
  308. /*
  309. * Allocate the IRQ
  310. */
  311. retval = request_irq(sport->port.irq, sa1100_int, 0,
  312. "sa11x0-uart", sport);
  313. if (retval)
  314. return retval;
  315. /*
  316. * Finally, clear and enable interrupts
  317. */
  318. UART_PUT_UTSR0(sport, -1);
  319. UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
  320. /*
  321. * Enable modem status interrupts
  322. */
  323. spin_lock_irq(&sport->port.lock);
  324. sa1100_enable_ms(&sport->port);
  325. spin_unlock_irq(&sport->port.lock);
  326. return 0;
  327. }
  328. static void sa1100_shutdown(struct uart_port *port)
  329. {
  330. struct sa1100_port *sport = (struct sa1100_port *)port;
  331. /*
  332. * Stop our timer.
  333. */
  334. del_timer_sync(&sport->timer);
  335. /*
  336. * Free the interrupt
  337. */
  338. free_irq(sport->port.irq, sport);
  339. /*
  340. * Disable all interrupts, port and break condition.
  341. */
  342. UART_PUT_UTCR3(sport, 0);
  343. }
  344. static void
  345. sa1100_set_termios(struct uart_port *port, struct termios *termios,
  346. struct termios *old)
  347. {
  348. struct sa1100_port *sport = (struct sa1100_port *)port;
  349. unsigned long flags;
  350. unsigned int utcr0, old_utcr3, baud, quot;
  351. unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
  352. /*
  353. * We only support CS7 and CS8.
  354. */
  355. while ((termios->c_cflag & CSIZE) != CS7 &&
  356. (termios->c_cflag & CSIZE) != CS8) {
  357. termios->c_cflag &= ~CSIZE;
  358. termios->c_cflag |= old_csize;
  359. old_csize = CS8;
  360. }
  361. if ((termios->c_cflag & CSIZE) == CS8)
  362. utcr0 = UTCR0_DSS;
  363. else
  364. utcr0 = 0;
  365. if (termios->c_cflag & CSTOPB)
  366. utcr0 |= UTCR0_SBS;
  367. if (termios->c_cflag & PARENB) {
  368. utcr0 |= UTCR0_PE;
  369. if (!(termios->c_cflag & PARODD))
  370. utcr0 |= UTCR0_OES;
  371. }
  372. /*
  373. * Ask the core to calculate the divisor for us.
  374. */
  375. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  376. quot = uart_get_divisor(port, baud);
  377. spin_lock_irqsave(&sport->port.lock, flags);
  378. sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
  379. sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
  380. if (termios->c_iflag & INPCK)
  381. sport->port.read_status_mask |=
  382. UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
  383. if (termios->c_iflag & (BRKINT | PARMRK))
  384. sport->port.read_status_mask |=
  385. UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
  386. /*
  387. * Characters to ignore
  388. */
  389. sport->port.ignore_status_mask = 0;
  390. if (termios->c_iflag & IGNPAR)
  391. sport->port.ignore_status_mask |=
  392. UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
  393. if (termios->c_iflag & IGNBRK) {
  394. sport->port.ignore_status_mask |=
  395. UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
  396. /*
  397. * If we're ignoring parity and break indicators,
  398. * ignore overruns too (for real raw support).
  399. */
  400. if (termios->c_iflag & IGNPAR)
  401. sport->port.ignore_status_mask |=
  402. UTSR1_TO_SM(UTSR1_ROR);
  403. }
  404. del_timer_sync(&sport->timer);
  405. /*
  406. * Update the per-port timeout.
  407. */
  408. uart_update_timeout(port, termios->c_cflag, baud);
  409. /*
  410. * disable interrupts and drain transmitter
  411. */
  412. old_utcr3 = UART_GET_UTCR3(sport);
  413. UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
  414. while (UART_GET_UTSR1(sport) & UTSR1_TBY)
  415. barrier();
  416. /* then, disable everything */
  417. UART_PUT_UTCR3(sport, 0);
  418. /* set the parity, stop bits and data size */
  419. UART_PUT_UTCR0(sport, utcr0);
  420. /* set the baud rate */
  421. quot -= 1;
  422. UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
  423. UART_PUT_UTCR2(sport, (quot & 0xff));
  424. UART_PUT_UTSR0(sport, -1);
  425. UART_PUT_UTCR3(sport, old_utcr3);
  426. if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
  427. sa1100_enable_ms(&sport->port);
  428. spin_unlock_irqrestore(&sport->port.lock, flags);
  429. }
  430. static const char *sa1100_type(struct uart_port *port)
  431. {
  432. struct sa1100_port *sport = (struct sa1100_port *)port;
  433. return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
  434. }
  435. /*
  436. * Release the memory region(s) being used by 'port'.
  437. */
  438. static void sa1100_release_port(struct uart_port *port)
  439. {
  440. struct sa1100_port *sport = (struct sa1100_port *)port;
  441. release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
  442. }
  443. /*
  444. * Request the memory region(s) being used by 'port'.
  445. */
  446. static int sa1100_request_port(struct uart_port *port)
  447. {
  448. struct sa1100_port *sport = (struct sa1100_port *)port;
  449. return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
  450. "sa11x0-uart") != NULL ? 0 : -EBUSY;
  451. }
  452. /*
  453. * Configure/autoconfigure the port.
  454. */
  455. static void sa1100_config_port(struct uart_port *port, int flags)
  456. {
  457. struct sa1100_port *sport = (struct sa1100_port *)port;
  458. if (flags & UART_CONFIG_TYPE &&
  459. sa1100_request_port(&sport->port) == 0)
  460. sport->port.type = PORT_SA1100;
  461. }
  462. /*
  463. * Verify the new serial_struct (for TIOCSSERIAL).
  464. * The only change we allow are to the flags and type, and
  465. * even then only between PORT_SA1100 and PORT_UNKNOWN
  466. */
  467. static int
  468. sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
  469. {
  470. struct sa1100_port *sport = (struct sa1100_port *)port;
  471. int ret = 0;
  472. if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
  473. ret = -EINVAL;
  474. if (sport->port.irq != ser->irq)
  475. ret = -EINVAL;
  476. if (ser->io_type != SERIAL_IO_MEM)
  477. ret = -EINVAL;
  478. if (sport->port.uartclk / 16 != ser->baud_base)
  479. ret = -EINVAL;
  480. if ((void *)sport->port.mapbase != ser->iomem_base)
  481. ret = -EINVAL;
  482. if (sport->port.iobase != ser->port)
  483. ret = -EINVAL;
  484. if (ser->hub6 != 0)
  485. ret = -EINVAL;
  486. return ret;
  487. }
  488. static struct uart_ops sa1100_pops = {
  489. .tx_empty = sa1100_tx_empty,
  490. .set_mctrl = sa1100_set_mctrl,
  491. .get_mctrl = sa1100_get_mctrl,
  492. .stop_tx = sa1100_stop_tx,
  493. .start_tx = sa1100_start_tx,
  494. .stop_rx = sa1100_stop_rx,
  495. .enable_ms = sa1100_enable_ms,
  496. .break_ctl = sa1100_break_ctl,
  497. .startup = sa1100_startup,
  498. .shutdown = sa1100_shutdown,
  499. .set_termios = sa1100_set_termios,
  500. .type = sa1100_type,
  501. .release_port = sa1100_release_port,
  502. .request_port = sa1100_request_port,
  503. .config_port = sa1100_config_port,
  504. .verify_port = sa1100_verify_port,
  505. };
  506. static struct sa1100_port sa1100_ports[NR_PORTS];
  507. /*
  508. * Setup the SA1100 serial ports. Note that we don't include the IrDA
  509. * port here since we have our own SIR/FIR driver (see drivers/net/irda)
  510. *
  511. * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
  512. * Which serial port this ends up being depends on the machine you're
  513. * running this kernel on. I'm not convinced that this is a good idea,
  514. * but that's the way it traditionally works.
  515. *
  516. * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
  517. * used here.
  518. */
  519. static void __init sa1100_init_ports(void)
  520. {
  521. static int first = 1;
  522. int i;
  523. if (!first)
  524. return;
  525. first = 0;
  526. for (i = 0; i < NR_PORTS; i++) {
  527. sa1100_ports[i].port.uartclk = 3686400;
  528. sa1100_ports[i].port.ops = &sa1100_pops;
  529. sa1100_ports[i].port.fifosize = 8;
  530. sa1100_ports[i].port.line = i;
  531. sa1100_ports[i].port.iotype = SERIAL_IO_MEM;
  532. init_timer(&sa1100_ports[i].timer);
  533. sa1100_ports[i].timer.function = sa1100_timeout;
  534. sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
  535. }
  536. /*
  537. * make transmit lines outputs, so that when the port
  538. * is closed, the output is in the MARK state.
  539. */
  540. PPDR |= PPC_TXD1 | PPC_TXD3;
  541. PPSR |= PPC_TXD1 | PPC_TXD3;
  542. }
  543. void __init sa1100_register_uart_fns(struct sa1100_port_fns *fns)
  544. {
  545. if (fns->get_mctrl)
  546. sa1100_pops.get_mctrl = fns->get_mctrl;
  547. if (fns->set_mctrl)
  548. sa1100_pops.set_mctrl = fns->set_mctrl;
  549. sa1100_pops.pm = fns->pm;
  550. sa1100_pops.set_wake = fns->set_wake;
  551. }
  552. void __init sa1100_register_uart(int idx, int port)
  553. {
  554. if (idx >= NR_PORTS) {
  555. printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx);
  556. return;
  557. }
  558. switch (port) {
  559. case 1:
  560. sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
  561. sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
  562. sa1100_ports[idx].port.irq = IRQ_Ser1UART;
  563. sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
  564. break;
  565. case 2:
  566. sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
  567. sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
  568. sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
  569. sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
  570. break;
  571. case 3:
  572. sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
  573. sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
  574. sa1100_ports[idx].port.irq = IRQ_Ser3UART;
  575. sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
  576. break;
  577. default:
  578. printk(KERN_ERR "%s: bad port number %d\n", __FUNCTION__, port);
  579. }
  580. }
  581. #ifdef CONFIG_SERIAL_SA1100_CONSOLE
  582. /*
  583. * Interrupts are disabled on entering
  584. */
  585. static void
  586. sa1100_console_write(struct console *co, const char *s, unsigned int count)
  587. {
  588. struct sa1100_port *sport = &sa1100_ports[co->index];
  589. unsigned int old_utcr3, status, i;
  590. /*
  591. * First, save UTCR3 and then disable interrupts
  592. */
  593. old_utcr3 = UART_GET_UTCR3(sport);
  594. UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
  595. UTCR3_TXE);
  596. /*
  597. * Now, do each character
  598. */
  599. for (i = 0; i < count; i++) {
  600. do {
  601. status = UART_GET_UTSR1(sport);
  602. } while (!(status & UTSR1_TNF));
  603. UART_PUT_CHAR(sport, s[i]);
  604. if (s[i] == '\n') {
  605. do {
  606. status = UART_GET_UTSR1(sport);
  607. } while (!(status & UTSR1_TNF));
  608. UART_PUT_CHAR(sport, '\r');
  609. }
  610. }
  611. /*
  612. * Finally, wait for transmitter to become empty
  613. * and restore UTCR3
  614. */
  615. do {
  616. status = UART_GET_UTSR1(sport);
  617. } while (status & UTSR1_TBY);
  618. UART_PUT_UTCR3(sport, old_utcr3);
  619. }
  620. /*
  621. * If the port was already initialised (eg, by a boot loader),
  622. * try to determine the current setup.
  623. */
  624. static void __init
  625. sa1100_console_get_options(struct sa1100_port *sport, int *baud,
  626. int *parity, int *bits)
  627. {
  628. unsigned int utcr3;
  629. utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
  630. if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
  631. /* ok, the port was enabled */
  632. unsigned int utcr0, quot;
  633. utcr0 = UART_GET_UTCR0(sport);
  634. *parity = 'n';
  635. if (utcr0 & UTCR0_PE) {
  636. if (utcr0 & UTCR0_OES)
  637. *parity = 'e';
  638. else
  639. *parity = 'o';
  640. }
  641. if (utcr0 & UTCR0_DSS)
  642. *bits = 8;
  643. else
  644. *bits = 7;
  645. quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
  646. quot &= 0xfff;
  647. *baud = sport->port.uartclk / (16 * (quot + 1));
  648. }
  649. }
  650. static int __init
  651. sa1100_console_setup(struct console *co, char *options)
  652. {
  653. struct sa1100_port *sport;
  654. int baud = 9600;
  655. int bits = 8;
  656. int parity = 'n';
  657. int flow = 'n';
  658. /*
  659. * Check whether an invalid uart number has been specified, and
  660. * if so, search for the first available port that does have
  661. * console support.
  662. */
  663. if (co->index == -1 || co->index >= NR_PORTS)
  664. co->index = 0;
  665. sport = &sa1100_ports[co->index];
  666. if (options)
  667. uart_parse_options(options, &baud, &parity, &bits, &flow);
  668. else
  669. sa1100_console_get_options(sport, &baud, &parity, &bits);
  670. return uart_set_options(&sport->port, co, baud, parity, bits, flow);
  671. }
  672. static struct uart_driver sa1100_reg;
  673. static struct console sa1100_console = {
  674. .name = "ttySA",
  675. .write = sa1100_console_write,
  676. .device = uart_console_device,
  677. .setup = sa1100_console_setup,
  678. .flags = CON_PRINTBUFFER,
  679. .index = -1,
  680. .data = &sa1100_reg,
  681. };
  682. static int __init sa1100_rs_console_init(void)
  683. {
  684. sa1100_init_ports();
  685. register_console(&sa1100_console);
  686. return 0;
  687. }
  688. console_initcall(sa1100_rs_console_init);
  689. #define SA1100_CONSOLE &sa1100_console
  690. #else
  691. #define SA1100_CONSOLE NULL
  692. #endif
  693. static struct uart_driver sa1100_reg = {
  694. .owner = THIS_MODULE,
  695. .driver_name = "ttySA",
  696. .dev_name = "ttySA",
  697. .devfs_name = "ttySA",
  698. .major = SERIAL_SA1100_MAJOR,
  699. .minor = MINOR_START,
  700. .nr = NR_PORTS,
  701. .cons = SA1100_CONSOLE,
  702. };
  703. static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
  704. {
  705. struct sa1100_port *sport = platform_get_drvdata(dev);
  706. if (sport)
  707. uart_suspend_port(&sa1100_reg, &sport->port);
  708. return 0;
  709. }
  710. static int sa1100_serial_resume(struct platform_device *dev)
  711. {
  712. struct sa1100_port *sport = platform_get_drvdata(dev);
  713. if (sport)
  714. uart_resume_port(&sa1100_reg, &sport->port);
  715. return 0;
  716. }
  717. static int sa1100_serial_probe(struct platform_device *dev)
  718. {
  719. struct resource *res = dev->resource;
  720. int i;
  721. for (i = 0; i < dev->num_resources; i++, res++)
  722. if (res->flags & IORESOURCE_MEM)
  723. break;
  724. if (i < dev->num_resources) {
  725. for (i = 0; i < NR_PORTS; i++) {
  726. if (sa1100_ports[i].port.mapbase != res->start)
  727. continue;
  728. sa1100_ports[i].port.dev = &dev->dev;
  729. uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
  730. platform_set_drvdata(dev, &sa1100_ports[i]);
  731. break;
  732. }
  733. }
  734. return 0;
  735. }
  736. static int sa1100_serial_remove(struct platform_device *pdev)
  737. {
  738. struct sa1100_port *sport = platform_get_drvdata(pdev);
  739. platform_set_drvdata(pdev, NULL);
  740. if (sport)
  741. uart_remove_one_port(&sa1100_reg, &sport->port);
  742. return 0;
  743. }
  744. static struct platform_driver sa11x0_serial_driver = {
  745. .probe = sa1100_serial_probe,
  746. .remove = sa1100_serial_remove,
  747. .suspend = sa1100_serial_suspend,
  748. .resume = sa1100_serial_resume,
  749. .driver = {
  750. .name = "sa11x0-uart",
  751. },
  752. };
  753. static int __init sa1100_serial_init(void)
  754. {
  755. int ret;
  756. printk(KERN_INFO "Serial: SA11x0 driver $Revision: 1.50 $\n");
  757. sa1100_init_ports();
  758. ret = uart_register_driver(&sa1100_reg);
  759. if (ret == 0) {
  760. ret = platform_driver_register(&sa11x0_serial_driver);
  761. if (ret)
  762. uart_unregister_driver(&sa1100_reg);
  763. }
  764. return ret;
  765. }
  766. static void __exit sa1100_serial_exit(void)
  767. {
  768. platform_driver_unregister(&sa11x0_serial_driver);
  769. uart_unregister_driver(&sa1100_reg);
  770. }
  771. module_init(sa1100_serial_init);
  772. module_exit(sa1100_serial_exit);
  773. MODULE_AUTHOR("Deep Blue Solutions Ltd");
  774. MODULE_DESCRIPTION("SA1100 generic serial port driver $Revision: 1.50 $");
  775. MODULE_LICENSE("GPL");
  776. MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);