malta-time.c 4.4 KB

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  1. /*
  2. * Carsten Langgaard, carstenl@mips.com
  3. * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
  4. *
  5. * This program is free software; you can distribute it and/or modify it
  6. * under the terms of the GNU General Public License (Version 2) as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along
  15. * with this program; if not, write to the Free Software Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17. *
  18. * Setting up the clock on the MIPS boards.
  19. */
  20. #include <linux/types.h>
  21. #include <linux/i8253.h>
  22. #include <linux/init.h>
  23. #include <linux/kernel_stat.h>
  24. #include <linux/sched.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/timex.h>
  28. #include <linux/mc146818rtc.h>
  29. #include <asm/mipsregs.h>
  30. #include <asm/mipsmtregs.h>
  31. #include <asm/hardirq.h>
  32. #include <asm/irq.h>
  33. #include <asm/div64.h>
  34. #include <asm/setup.h>
  35. #include <asm/time.h>
  36. #include <asm/mc146818-time.h>
  37. #include <asm/msc01_ic.h>
  38. #include <asm/gic.h>
  39. #include <asm/mips-boards/generic.h>
  40. #include <asm/mips-boards/maltaint.h>
  41. unsigned long cpu_khz;
  42. int gic_frequency;
  43. static int mips_cpu_timer_irq;
  44. static int mips_cpu_perf_irq;
  45. extern int cp0_perfcount_irq;
  46. static void mips_timer_dispatch(void)
  47. {
  48. do_IRQ(mips_cpu_timer_irq);
  49. }
  50. static void mips_perf_dispatch(void)
  51. {
  52. do_IRQ(mips_cpu_perf_irq);
  53. }
  54. static unsigned int freqround(unsigned int freq, unsigned int amount)
  55. {
  56. freq += amount;
  57. freq -= freq % (amount*2);
  58. return freq;
  59. }
  60. /*
  61. * Estimate CPU and GIC frequencies.
  62. */
  63. static void __init estimate_frequencies(void)
  64. {
  65. unsigned long flags;
  66. unsigned int count, start;
  67. unsigned int giccount = 0, gicstart = 0;
  68. local_irq_save(flags);
  69. /* Start counter exactly on falling edge of update flag. */
  70. while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  71. while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  72. /* Initialize counters. */
  73. start = read_c0_count();
  74. if (gic_present)
  75. GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
  76. /* Read counter exactly on falling edge of update flag. */
  77. while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  78. while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  79. count = read_c0_count();
  80. if (gic_present)
  81. GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
  82. local_irq_restore(flags);
  83. count -= start;
  84. if (gic_present)
  85. giccount -= gicstart;
  86. mips_hpt_frequency = count;
  87. if (gic_present)
  88. gic_frequency = giccount;
  89. }
  90. void read_persistent_clock(struct timespec *ts)
  91. {
  92. ts->tv_sec = mc146818_get_cmos_time();
  93. ts->tv_nsec = 0;
  94. }
  95. static void __init plat_perf_setup(void)
  96. {
  97. #ifdef MSC01E_INT_BASE
  98. if (cpu_has_veic) {
  99. set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
  100. mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
  101. } else
  102. #endif
  103. if (cp0_perfcount_irq >= 0) {
  104. if (cpu_has_vint)
  105. set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
  106. mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
  107. #ifdef CONFIG_SMP
  108. irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
  109. #endif
  110. }
  111. }
  112. unsigned int __cpuinit get_c0_compare_int(void)
  113. {
  114. #ifdef MSC01E_INT_BASE
  115. if (cpu_has_veic) {
  116. set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
  117. mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
  118. } else
  119. #endif
  120. {
  121. if (cpu_has_vint)
  122. set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
  123. mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
  124. }
  125. return mips_cpu_timer_irq;
  126. }
  127. void __init plat_time_init(void)
  128. {
  129. unsigned int prid = read_c0_prid() & 0xffff00;
  130. unsigned int freq;
  131. estimate_frequencies();
  132. freq = mips_hpt_frequency;
  133. if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
  134. (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
  135. freq *= 2;
  136. freq = freqround(freq, 5000);
  137. pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
  138. (freq%1000000)*100/1000000);
  139. cpu_khz = freq / 1000;
  140. if (gic_present) {
  141. freq = freqround(gic_frequency, 5000);
  142. pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
  143. (freq%1000000)*100/1000000);
  144. gic_clocksource_init(gic_frequency);
  145. } else
  146. init_r4k_clocksource();
  147. #ifdef CONFIG_I8253
  148. /* Only Malta has a PIT. */
  149. setup_pit_timer();
  150. #endif
  151. mips_scroll_message();
  152. plat_perf_setup();
  153. }