soc-cache.c 36 KB

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  1. /*
  2. * soc-cache.c -- ASoC register cache helpers
  3. *
  4. * Copyright 2009 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/i2c.h>
  14. #include <linux/spi/spi.h>
  15. #include <sound/soc.h>
  16. #include <linux/lzo.h>
  17. #include <linux/bitmap.h>
  18. #include <linux/rbtree.h>
  19. #include <trace/events/asoc.h>
  20. static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
  21. unsigned int value, const void *data, int len)
  22. {
  23. int ret;
  24. if (!snd_soc_codec_volatile_register(codec, reg) &&
  25. reg < codec->driver->reg_cache_size &&
  26. !codec->cache_bypass) {
  27. ret = snd_soc_cache_write(codec, reg, value);
  28. if (ret < 0)
  29. return -1;
  30. }
  31. if (codec->cache_only) {
  32. codec->cache_sync = 1;
  33. return 0;
  34. }
  35. ret = codec->hw_write(codec->control_data, data, len);
  36. if (ret == len)
  37. return 0;
  38. if (ret < 0)
  39. return ret;
  40. else
  41. return -EIO;
  42. }
  43. static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
  44. unsigned int reg)
  45. {
  46. int ret;
  47. unsigned int val;
  48. if (reg >= codec->driver->reg_cache_size ||
  49. snd_soc_codec_volatile_register(codec, reg) ||
  50. codec->cache_bypass) {
  51. if (codec->cache_only)
  52. return -1;
  53. BUG_ON(!codec->hw_read);
  54. return codec->hw_read(codec, reg);
  55. }
  56. ret = snd_soc_cache_read(codec, reg, &val);
  57. if (ret < 0)
  58. return -1;
  59. return val;
  60. }
  61. static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
  62. unsigned int value)
  63. {
  64. u8 data[2];
  65. data[0] = (reg << 4) | ((value >> 8) & 0x000f);
  66. data[1] = value & 0x00ff;
  67. return do_hw_write(codec, reg, value, data, 2);
  68. }
  69. #if defined(CONFIG_SPI_MASTER)
  70. static int snd_soc_4_12_spi_write(void *control_data, const char *data,
  71. int len)
  72. {
  73. struct spi_device *spi = control_data;
  74. struct spi_transfer t;
  75. struct spi_message m;
  76. u8 msg[2];
  77. if (len <= 0)
  78. return 0;
  79. msg[0] = data[1];
  80. msg[1] = data[0];
  81. spi_message_init(&m);
  82. memset(&t, 0, sizeof t);
  83. t.tx_buf = &msg[0];
  84. t.len = len;
  85. spi_message_add_tail(&t, &m);
  86. spi_sync(spi, &m);
  87. return len;
  88. }
  89. #else
  90. #define snd_soc_4_12_spi_write NULL
  91. #endif
  92. static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
  93. unsigned int reg)
  94. {
  95. int ret;
  96. unsigned int val;
  97. if (reg >= codec->driver->reg_cache_size ||
  98. snd_soc_codec_volatile_register(codec, reg) ||
  99. codec->cache_bypass) {
  100. if (codec->cache_only)
  101. return -1;
  102. BUG_ON(!codec->hw_read);
  103. return codec->hw_read(codec, reg);
  104. }
  105. ret = snd_soc_cache_read(codec, reg, &val);
  106. if (ret < 0)
  107. return -1;
  108. return val;
  109. }
  110. static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
  111. unsigned int value)
  112. {
  113. u8 data[2];
  114. data[0] = (reg << 1) | ((value >> 8) & 0x0001);
  115. data[1] = value & 0x00ff;
  116. return do_hw_write(codec, reg, value, data, 2);
  117. }
  118. #if defined(CONFIG_SPI_MASTER)
  119. static int snd_soc_7_9_spi_write(void *control_data, const char *data,
  120. int len)
  121. {
  122. struct spi_device *spi = control_data;
  123. struct spi_transfer t;
  124. struct spi_message m;
  125. u8 msg[2];
  126. if (len <= 0)
  127. return 0;
  128. msg[0] = data[0];
  129. msg[1] = data[1];
  130. spi_message_init(&m);
  131. memset(&t, 0, sizeof t);
  132. t.tx_buf = &msg[0];
  133. t.len = len;
  134. spi_message_add_tail(&t, &m);
  135. spi_sync(spi, &m);
  136. return len;
  137. }
  138. #else
  139. #define snd_soc_7_9_spi_write NULL
  140. #endif
  141. static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
  142. unsigned int value)
  143. {
  144. u8 data[2];
  145. reg &= 0xff;
  146. data[0] = reg;
  147. data[1] = value & 0xff;
  148. return do_hw_write(codec, reg, value, data, 2);
  149. }
  150. static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
  151. unsigned int reg)
  152. {
  153. int ret;
  154. unsigned int val;
  155. reg &= 0xff;
  156. if (reg >= codec->driver->reg_cache_size ||
  157. snd_soc_codec_volatile_register(codec, reg) ||
  158. codec->cache_bypass) {
  159. if (codec->cache_only)
  160. return -1;
  161. BUG_ON(!codec->hw_read);
  162. return codec->hw_read(codec, reg);
  163. }
  164. ret = snd_soc_cache_read(codec, reg, &val);
  165. if (ret < 0)
  166. return -1;
  167. return val;
  168. }
  169. #if defined(CONFIG_SPI_MASTER)
  170. static int snd_soc_8_8_spi_write(void *control_data, const char *data,
  171. int len)
  172. {
  173. struct spi_device *spi = control_data;
  174. struct spi_transfer t;
  175. struct spi_message m;
  176. u8 msg[2];
  177. if (len <= 0)
  178. return 0;
  179. msg[0] = data[0];
  180. msg[1] = data[1];
  181. spi_message_init(&m);
  182. memset(&t, 0, sizeof t);
  183. t.tx_buf = &msg[0];
  184. t.len = len;
  185. spi_message_add_tail(&t, &m);
  186. spi_sync(spi, &m);
  187. return len;
  188. }
  189. #else
  190. #define snd_soc_8_8_spi_write NULL
  191. #endif
  192. static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
  193. unsigned int value)
  194. {
  195. u8 data[3];
  196. data[0] = reg;
  197. data[1] = (value >> 8) & 0xff;
  198. data[2] = value & 0xff;
  199. return do_hw_write(codec, reg, value, data, 3);
  200. }
  201. static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
  202. unsigned int reg)
  203. {
  204. int ret;
  205. unsigned int val;
  206. if (reg >= codec->driver->reg_cache_size ||
  207. snd_soc_codec_volatile_register(codec, reg) ||
  208. codec->cache_bypass) {
  209. if (codec->cache_only)
  210. return -1;
  211. BUG_ON(!codec->hw_read);
  212. return codec->hw_read(codec, reg);
  213. }
  214. ret = snd_soc_cache_read(codec, reg, &val);
  215. if (ret < 0)
  216. return -1;
  217. return val;
  218. }
  219. #if defined(CONFIG_SPI_MASTER)
  220. static int snd_soc_8_16_spi_write(void *control_data, const char *data,
  221. int len)
  222. {
  223. struct spi_device *spi = control_data;
  224. struct spi_transfer t;
  225. struct spi_message m;
  226. u8 msg[3];
  227. if (len <= 0)
  228. return 0;
  229. msg[0] = data[0];
  230. msg[1] = data[1];
  231. msg[2] = data[2];
  232. spi_message_init(&m);
  233. memset(&t, 0, sizeof t);
  234. t.tx_buf = &msg[0];
  235. t.len = len;
  236. spi_message_add_tail(&t, &m);
  237. spi_sync(spi, &m);
  238. return len;
  239. }
  240. #else
  241. #define snd_soc_8_16_spi_write NULL
  242. #endif
  243. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  244. static unsigned int do_i2c_read(struct snd_soc_codec *codec,
  245. void *reg, int reglen,
  246. void *data, int datalen)
  247. {
  248. struct i2c_msg xfer[2];
  249. int ret;
  250. struct i2c_client *client = codec->control_data;
  251. /* Write register */
  252. xfer[0].addr = client->addr;
  253. xfer[0].flags = 0;
  254. xfer[0].len = reglen;
  255. xfer[0].buf = reg;
  256. /* Read data */
  257. xfer[1].addr = client->addr;
  258. xfer[1].flags = I2C_M_RD;
  259. xfer[1].len = datalen;
  260. xfer[1].buf = data;
  261. ret = i2c_transfer(client->adapter, xfer, 2);
  262. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  263. if (ret == 2)
  264. return 0;
  265. else if (ret < 0)
  266. return ret;
  267. else
  268. return -EIO;
  269. }
  270. #endif
  271. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  272. static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
  273. unsigned int r)
  274. {
  275. u8 reg = r;
  276. u8 data;
  277. int ret;
  278. ret = do_i2c_read(codec, &reg, 1, &data, 1);
  279. if (ret < 0)
  280. return 0;
  281. return data;
  282. }
  283. #else
  284. #define snd_soc_8_8_read_i2c NULL
  285. #endif
  286. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  287. static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
  288. unsigned int r)
  289. {
  290. u8 reg = r;
  291. u16 data;
  292. int ret;
  293. ret = do_i2c_read(codec, &reg, 1, &data, 2);
  294. if (ret < 0)
  295. return 0;
  296. return (data >> 8) | ((data & 0xff) << 8);
  297. }
  298. #else
  299. #define snd_soc_8_16_read_i2c NULL
  300. #endif
  301. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  302. static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
  303. unsigned int r)
  304. {
  305. u16 reg = r;
  306. u8 data;
  307. int ret;
  308. ret = do_i2c_read(codec, &reg, 2, &data, 1);
  309. if (ret < 0)
  310. return 0;
  311. return data;
  312. }
  313. #else
  314. #define snd_soc_16_8_read_i2c NULL
  315. #endif
  316. static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
  317. unsigned int reg)
  318. {
  319. int ret;
  320. unsigned int val;
  321. reg &= 0xff;
  322. if (reg >= codec->driver->reg_cache_size ||
  323. snd_soc_codec_volatile_register(codec, reg) ||
  324. codec->cache_bypass) {
  325. if (codec->cache_only)
  326. return -1;
  327. BUG_ON(!codec->hw_read);
  328. return codec->hw_read(codec, reg);
  329. }
  330. ret = snd_soc_cache_read(codec, reg, &val);
  331. if (ret < 0)
  332. return -1;
  333. return val;
  334. }
  335. static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
  336. unsigned int value)
  337. {
  338. u8 data[3];
  339. data[0] = (reg >> 8) & 0xff;
  340. data[1] = reg & 0xff;
  341. data[2] = value;
  342. reg &= 0xff;
  343. return do_hw_write(codec, reg, value, data, 3);
  344. }
  345. #if defined(CONFIG_SPI_MASTER)
  346. static int snd_soc_16_8_spi_write(void *control_data, const char *data,
  347. int len)
  348. {
  349. struct spi_device *spi = control_data;
  350. struct spi_transfer t;
  351. struct spi_message m;
  352. u8 msg[3];
  353. if (len <= 0)
  354. return 0;
  355. msg[0] = data[0];
  356. msg[1] = data[1];
  357. msg[2] = data[2];
  358. spi_message_init(&m);
  359. memset(&t, 0, sizeof t);
  360. t.tx_buf = &msg[0];
  361. t.len = len;
  362. spi_message_add_tail(&t, &m);
  363. spi_sync(spi, &m);
  364. return len;
  365. }
  366. #else
  367. #define snd_soc_16_8_spi_write NULL
  368. #endif
  369. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  370. static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
  371. unsigned int r)
  372. {
  373. u16 reg = cpu_to_be16(r);
  374. u16 data;
  375. int ret;
  376. ret = do_i2c_read(codec, &reg, 2, &data, 2);
  377. if (ret < 0)
  378. return 0;
  379. return be16_to_cpu(data);
  380. }
  381. #else
  382. #define snd_soc_16_16_read_i2c NULL
  383. #endif
  384. static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
  385. unsigned int reg)
  386. {
  387. int ret;
  388. unsigned int val;
  389. if (reg >= codec->driver->reg_cache_size ||
  390. snd_soc_codec_volatile_register(codec, reg) ||
  391. codec->cache_bypass) {
  392. if (codec->cache_only)
  393. return -1;
  394. BUG_ON(!codec->hw_read);
  395. return codec->hw_read(codec, reg);
  396. }
  397. ret = snd_soc_cache_read(codec, reg, &val);
  398. if (ret < 0)
  399. return -1;
  400. return val;
  401. }
  402. static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
  403. unsigned int value)
  404. {
  405. u8 data[4];
  406. data[0] = (reg >> 8) & 0xff;
  407. data[1] = reg & 0xff;
  408. data[2] = (value >> 8) & 0xff;
  409. data[3] = value & 0xff;
  410. return do_hw_write(codec, reg, value, data, 4);
  411. }
  412. #if defined(CONFIG_SPI_MASTER)
  413. static int snd_soc_16_16_spi_write(void *control_data, const char *data,
  414. int len)
  415. {
  416. struct spi_device *spi = control_data;
  417. struct spi_transfer t;
  418. struct spi_message m;
  419. u8 msg[4];
  420. if (len <= 0)
  421. return 0;
  422. msg[0] = data[0];
  423. msg[1] = data[1];
  424. msg[2] = data[2];
  425. msg[3] = data[3];
  426. spi_message_init(&m);
  427. memset(&t, 0, sizeof t);
  428. t.tx_buf = &msg[0];
  429. t.len = len;
  430. spi_message_add_tail(&t, &m);
  431. spi_sync(spi, &m);
  432. return len;
  433. }
  434. #else
  435. #define snd_soc_16_16_spi_write NULL
  436. #endif
  437. /* Primitive bulk write support for soc-cache. The data pointed to by `data' needs
  438. * to already be in the form the hardware expects including any leading register specific
  439. * data. Any data written through this function will not go through the cache as it
  440. * only handles writing to volatile or out of bounds registers.
  441. */
  442. static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
  443. const void *data, size_t len)
  444. {
  445. int ret;
  446. /* Ensure that the base register is volatile. Subsequently
  447. * any other register that is touched by this routine should be
  448. * volatile as well to ensure that we don't get out of sync with
  449. * the cache.
  450. */
  451. if (!snd_soc_codec_volatile_register(codec, reg)
  452. && reg < codec->driver->reg_cache_size)
  453. return -EINVAL;
  454. switch (codec->control_type) {
  455. case SND_SOC_I2C:
  456. ret = i2c_master_send(codec->control_data, data, len);
  457. break;
  458. case SND_SOC_SPI:
  459. ret = do_spi_write(codec->control_data, data, len);
  460. break;
  461. default:
  462. BUG();
  463. }
  464. if (ret == len)
  465. return 0;
  466. if (ret < 0)
  467. return ret;
  468. else
  469. return -EIO;
  470. }
  471. static struct {
  472. int addr_bits;
  473. int data_bits;
  474. int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
  475. int (*spi_write)(void *, const char *, int);
  476. unsigned int (*read)(struct snd_soc_codec *, unsigned int);
  477. unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
  478. } io_types[] = {
  479. {
  480. .addr_bits = 4, .data_bits = 12,
  481. .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
  482. .spi_write = snd_soc_4_12_spi_write,
  483. },
  484. {
  485. .addr_bits = 7, .data_bits = 9,
  486. .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
  487. .spi_write = snd_soc_7_9_spi_write,
  488. },
  489. {
  490. .addr_bits = 8, .data_bits = 8,
  491. .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
  492. .i2c_read = snd_soc_8_8_read_i2c,
  493. .spi_write = snd_soc_8_8_spi_write,
  494. },
  495. {
  496. .addr_bits = 8, .data_bits = 16,
  497. .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
  498. .i2c_read = snd_soc_8_16_read_i2c,
  499. .spi_write = snd_soc_8_16_spi_write,
  500. },
  501. {
  502. .addr_bits = 16, .data_bits = 8,
  503. .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
  504. .i2c_read = snd_soc_16_8_read_i2c,
  505. .spi_write = snd_soc_16_8_spi_write,
  506. },
  507. {
  508. .addr_bits = 16, .data_bits = 16,
  509. .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
  510. .i2c_read = snd_soc_16_16_read_i2c,
  511. .spi_write = snd_soc_16_16_spi_write,
  512. },
  513. };
  514. /**
  515. * snd_soc_codec_set_cache_io: Set up standard I/O functions.
  516. *
  517. * @codec: CODEC to configure.
  518. * @type: Type of cache.
  519. * @addr_bits: Number of bits of register address data.
  520. * @data_bits: Number of bits of data per register.
  521. * @control: Control bus used.
  522. *
  523. * Register formats are frequently shared between many I2C and SPI
  524. * devices. In order to promote code reuse the ASoC core provides
  525. * some standard implementations of CODEC read and write operations
  526. * which can be set up using this function.
  527. *
  528. * The caller is responsible for allocating and initialising the
  529. * actual cache.
  530. *
  531. * Note that at present this code cannot be used by CODECs with
  532. * volatile registers.
  533. */
  534. int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
  535. int addr_bits, int data_bits,
  536. enum snd_soc_control_type control)
  537. {
  538. int i;
  539. for (i = 0; i < ARRAY_SIZE(io_types); i++)
  540. if (io_types[i].addr_bits == addr_bits &&
  541. io_types[i].data_bits == data_bits)
  542. break;
  543. if (i == ARRAY_SIZE(io_types)) {
  544. printk(KERN_ERR
  545. "No I/O functions for %d bit address %d bit data\n",
  546. addr_bits, data_bits);
  547. return -EINVAL;
  548. }
  549. codec->write = io_types[i].write;
  550. codec->read = io_types[i].read;
  551. codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
  552. switch (control) {
  553. case SND_SOC_CUSTOM:
  554. break;
  555. case SND_SOC_I2C:
  556. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  557. codec->hw_write = (hw_write_t)i2c_master_send;
  558. #endif
  559. if (io_types[i].i2c_read)
  560. codec->hw_read = io_types[i].i2c_read;
  561. codec->control_data = container_of(codec->dev,
  562. struct i2c_client,
  563. dev);
  564. break;
  565. case SND_SOC_SPI:
  566. if (io_types[i].spi_write)
  567. codec->hw_write = io_types[i].spi_write;
  568. codec->control_data = container_of(codec->dev,
  569. struct spi_device,
  570. dev);
  571. break;
  572. }
  573. return 0;
  574. }
  575. EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
  576. static bool snd_soc_set_cache_val(void *base, unsigned int idx,
  577. unsigned int val, unsigned int word_size)
  578. {
  579. switch (word_size) {
  580. case 1: {
  581. u8 *cache = base;
  582. if (cache[idx] == val)
  583. return true;
  584. cache[idx] = val;
  585. break;
  586. }
  587. case 2: {
  588. u16 *cache = base;
  589. if (cache[idx] == val)
  590. return true;
  591. cache[idx] = val;
  592. break;
  593. }
  594. default:
  595. BUG();
  596. }
  597. return false;
  598. }
  599. static unsigned int snd_soc_get_cache_val(const void *base, unsigned int idx,
  600. unsigned int word_size)
  601. {
  602. switch (word_size) {
  603. case 1: {
  604. const u8 *cache = base;
  605. return cache[idx];
  606. }
  607. case 2: {
  608. const u16 *cache = base;
  609. return cache[idx];
  610. }
  611. default:
  612. BUG();
  613. }
  614. /* unreachable */
  615. return -1;
  616. }
  617. struct snd_soc_rbtree_node {
  618. struct rb_node node;
  619. unsigned int reg;
  620. unsigned int value;
  621. unsigned int defval;
  622. } __attribute__ ((packed));
  623. struct snd_soc_rbtree_ctx {
  624. struct rb_root root;
  625. };
  626. static struct snd_soc_rbtree_node *snd_soc_rbtree_lookup(
  627. struct rb_root *root, unsigned int reg)
  628. {
  629. struct rb_node *node;
  630. struct snd_soc_rbtree_node *rbnode;
  631. node = root->rb_node;
  632. while (node) {
  633. rbnode = container_of(node, struct snd_soc_rbtree_node, node);
  634. if (rbnode->reg < reg)
  635. node = node->rb_left;
  636. else if (rbnode->reg > reg)
  637. node = node->rb_right;
  638. else
  639. return rbnode;
  640. }
  641. return NULL;
  642. }
  643. static int snd_soc_rbtree_insert(struct rb_root *root,
  644. struct snd_soc_rbtree_node *rbnode)
  645. {
  646. struct rb_node **new, *parent;
  647. struct snd_soc_rbtree_node *rbnode_tmp;
  648. parent = NULL;
  649. new = &root->rb_node;
  650. while (*new) {
  651. rbnode_tmp = container_of(*new, struct snd_soc_rbtree_node,
  652. node);
  653. parent = *new;
  654. if (rbnode_tmp->reg < rbnode->reg)
  655. new = &((*new)->rb_left);
  656. else if (rbnode_tmp->reg > rbnode->reg)
  657. new = &((*new)->rb_right);
  658. else
  659. return 0;
  660. }
  661. /* insert the node into the rbtree */
  662. rb_link_node(&rbnode->node, parent, new);
  663. rb_insert_color(&rbnode->node, root);
  664. return 1;
  665. }
  666. static int snd_soc_rbtree_cache_sync(struct snd_soc_codec *codec)
  667. {
  668. struct snd_soc_rbtree_ctx *rbtree_ctx;
  669. struct rb_node *node;
  670. struct snd_soc_rbtree_node *rbnode;
  671. unsigned int val;
  672. int ret;
  673. rbtree_ctx = codec->reg_cache;
  674. for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
  675. rbnode = rb_entry(node, struct snd_soc_rbtree_node, node);
  676. if (rbnode->value == rbnode->defval)
  677. continue;
  678. ret = snd_soc_cache_read(codec, rbnode->reg, &val);
  679. if (ret)
  680. return ret;
  681. codec->cache_bypass = 1;
  682. ret = snd_soc_write(codec, rbnode->reg, val);
  683. codec->cache_bypass = 0;
  684. if (ret)
  685. return ret;
  686. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  687. rbnode->reg, val);
  688. }
  689. return 0;
  690. }
  691. static int snd_soc_rbtree_cache_write(struct snd_soc_codec *codec,
  692. unsigned int reg, unsigned int value)
  693. {
  694. struct snd_soc_rbtree_ctx *rbtree_ctx;
  695. struct snd_soc_rbtree_node *rbnode;
  696. rbtree_ctx = codec->reg_cache;
  697. rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
  698. if (rbnode) {
  699. if (rbnode->value == value)
  700. return 0;
  701. rbnode->value = value;
  702. } else {
  703. /* bail out early, no need to create the rbnode yet */
  704. if (!value)
  705. return 0;
  706. /*
  707. * for uninitialized registers whose value is changed
  708. * from the default zero, create an rbnode and insert
  709. * it into the tree.
  710. */
  711. rbnode = kzalloc(sizeof *rbnode, GFP_KERNEL);
  712. if (!rbnode)
  713. return -ENOMEM;
  714. rbnode->reg = reg;
  715. rbnode->value = value;
  716. snd_soc_rbtree_insert(&rbtree_ctx->root, rbnode);
  717. }
  718. return 0;
  719. }
  720. static int snd_soc_rbtree_cache_read(struct snd_soc_codec *codec,
  721. unsigned int reg, unsigned int *value)
  722. {
  723. struct snd_soc_rbtree_ctx *rbtree_ctx;
  724. struct snd_soc_rbtree_node *rbnode;
  725. rbtree_ctx = codec->reg_cache;
  726. rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
  727. if (rbnode) {
  728. *value = rbnode->value;
  729. } else {
  730. /* uninitialized registers default to 0 */
  731. *value = 0;
  732. }
  733. return 0;
  734. }
  735. static int snd_soc_rbtree_cache_exit(struct snd_soc_codec *codec)
  736. {
  737. struct rb_node *next;
  738. struct snd_soc_rbtree_ctx *rbtree_ctx;
  739. struct snd_soc_rbtree_node *rbtree_node;
  740. /* if we've already been called then just return */
  741. rbtree_ctx = codec->reg_cache;
  742. if (!rbtree_ctx)
  743. return 0;
  744. /* free up the rbtree */
  745. next = rb_first(&rbtree_ctx->root);
  746. while (next) {
  747. rbtree_node = rb_entry(next, struct snd_soc_rbtree_node, node);
  748. next = rb_next(&rbtree_node->node);
  749. rb_erase(&rbtree_node->node, &rbtree_ctx->root);
  750. kfree(rbtree_node);
  751. }
  752. /* release the resources */
  753. kfree(codec->reg_cache);
  754. codec->reg_cache = NULL;
  755. return 0;
  756. }
  757. static int snd_soc_rbtree_cache_init(struct snd_soc_codec *codec)
  758. {
  759. struct snd_soc_rbtree_node *rbtree_node;
  760. struct snd_soc_rbtree_ctx *rbtree_ctx;
  761. unsigned int val;
  762. unsigned int word_size;
  763. int i;
  764. int ret;
  765. codec->reg_cache = kmalloc(sizeof *rbtree_ctx, GFP_KERNEL);
  766. if (!codec->reg_cache)
  767. return -ENOMEM;
  768. rbtree_ctx = codec->reg_cache;
  769. rbtree_ctx->root = RB_ROOT;
  770. if (!codec->reg_def_copy)
  771. return 0;
  772. /*
  773. * populate the rbtree with the initialized registers. All other
  774. * registers will be inserted when they are first modified.
  775. */
  776. word_size = codec->driver->reg_word_size;
  777. for (i = 0; i < codec->driver->reg_cache_size; ++i) {
  778. val = snd_soc_get_cache_val(codec->reg_def_copy, i, word_size);
  779. if (!val)
  780. continue;
  781. rbtree_node = kzalloc(sizeof *rbtree_node, GFP_KERNEL);
  782. if (!rbtree_node) {
  783. ret = -ENOMEM;
  784. snd_soc_cache_exit(codec);
  785. break;
  786. }
  787. rbtree_node->reg = i;
  788. rbtree_node->value = val;
  789. rbtree_node->defval = val;
  790. snd_soc_rbtree_insert(&rbtree_ctx->root, rbtree_node);
  791. }
  792. return 0;
  793. }
  794. #ifdef CONFIG_SND_SOC_CACHE_LZO
  795. struct snd_soc_lzo_ctx {
  796. void *wmem;
  797. void *dst;
  798. const void *src;
  799. size_t src_len;
  800. size_t dst_len;
  801. size_t decompressed_size;
  802. unsigned long *sync_bmp;
  803. int sync_bmp_nbits;
  804. };
  805. #define LZO_BLOCK_NUM 8
  806. static int snd_soc_lzo_block_count(void)
  807. {
  808. return LZO_BLOCK_NUM;
  809. }
  810. static int snd_soc_lzo_prepare(struct snd_soc_lzo_ctx *lzo_ctx)
  811. {
  812. lzo_ctx->wmem = kmalloc(LZO1X_MEM_COMPRESS, GFP_KERNEL);
  813. if (!lzo_ctx->wmem)
  814. return -ENOMEM;
  815. return 0;
  816. }
  817. static int snd_soc_lzo_compress(struct snd_soc_lzo_ctx *lzo_ctx)
  818. {
  819. size_t compress_size;
  820. int ret;
  821. ret = lzo1x_1_compress(lzo_ctx->src, lzo_ctx->src_len,
  822. lzo_ctx->dst, &compress_size, lzo_ctx->wmem);
  823. if (ret != LZO_E_OK || compress_size > lzo_ctx->dst_len)
  824. return -EINVAL;
  825. lzo_ctx->dst_len = compress_size;
  826. return 0;
  827. }
  828. static int snd_soc_lzo_decompress(struct snd_soc_lzo_ctx *lzo_ctx)
  829. {
  830. size_t dst_len;
  831. int ret;
  832. dst_len = lzo_ctx->dst_len;
  833. ret = lzo1x_decompress_safe(lzo_ctx->src, lzo_ctx->src_len,
  834. lzo_ctx->dst, &dst_len);
  835. if (ret != LZO_E_OK || dst_len != lzo_ctx->dst_len)
  836. return -EINVAL;
  837. return 0;
  838. }
  839. static int snd_soc_lzo_compress_cache_block(struct snd_soc_codec *codec,
  840. struct snd_soc_lzo_ctx *lzo_ctx)
  841. {
  842. int ret;
  843. lzo_ctx->dst_len = lzo1x_worst_compress(PAGE_SIZE);
  844. lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
  845. if (!lzo_ctx->dst) {
  846. lzo_ctx->dst_len = 0;
  847. return -ENOMEM;
  848. }
  849. ret = snd_soc_lzo_compress(lzo_ctx);
  850. if (ret < 0)
  851. return ret;
  852. return 0;
  853. }
  854. static int snd_soc_lzo_decompress_cache_block(struct snd_soc_codec *codec,
  855. struct snd_soc_lzo_ctx *lzo_ctx)
  856. {
  857. int ret;
  858. lzo_ctx->dst_len = lzo_ctx->decompressed_size;
  859. lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
  860. if (!lzo_ctx->dst) {
  861. lzo_ctx->dst_len = 0;
  862. return -ENOMEM;
  863. }
  864. ret = snd_soc_lzo_decompress(lzo_ctx);
  865. if (ret < 0)
  866. return ret;
  867. return 0;
  868. }
  869. static inline int snd_soc_lzo_get_blkindex(struct snd_soc_codec *codec,
  870. unsigned int reg)
  871. {
  872. const struct snd_soc_codec_driver *codec_drv;
  873. codec_drv = codec->driver;
  874. return (reg * codec_drv->reg_word_size) /
  875. DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count());
  876. }
  877. static inline int snd_soc_lzo_get_blkpos(struct snd_soc_codec *codec,
  878. unsigned int reg)
  879. {
  880. const struct snd_soc_codec_driver *codec_drv;
  881. codec_drv = codec->driver;
  882. return reg % (DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count()) /
  883. codec_drv->reg_word_size);
  884. }
  885. static inline int snd_soc_lzo_get_blksize(struct snd_soc_codec *codec)
  886. {
  887. const struct snd_soc_codec_driver *codec_drv;
  888. codec_drv = codec->driver;
  889. return DIV_ROUND_UP(codec->reg_size, snd_soc_lzo_block_count());
  890. }
  891. static int snd_soc_lzo_cache_sync(struct snd_soc_codec *codec)
  892. {
  893. struct snd_soc_lzo_ctx **lzo_blocks;
  894. unsigned int val;
  895. int i;
  896. int ret;
  897. lzo_blocks = codec->reg_cache;
  898. for_each_set_bit(i, lzo_blocks[0]->sync_bmp, lzo_blocks[0]->sync_bmp_nbits) {
  899. ret = snd_soc_cache_read(codec, i, &val);
  900. if (ret)
  901. return ret;
  902. codec->cache_bypass = 1;
  903. ret = snd_soc_write(codec, i, val);
  904. codec->cache_bypass = 0;
  905. if (ret)
  906. return ret;
  907. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  908. i, val);
  909. }
  910. return 0;
  911. }
  912. static int snd_soc_lzo_cache_write(struct snd_soc_codec *codec,
  913. unsigned int reg, unsigned int value)
  914. {
  915. struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
  916. int ret, blkindex, blkpos;
  917. size_t blksize, tmp_dst_len;
  918. void *tmp_dst;
  919. /* index of the compressed lzo block */
  920. blkindex = snd_soc_lzo_get_blkindex(codec, reg);
  921. /* register index within the decompressed block */
  922. blkpos = snd_soc_lzo_get_blkpos(codec, reg);
  923. /* size of the compressed block */
  924. blksize = snd_soc_lzo_get_blksize(codec);
  925. lzo_blocks = codec->reg_cache;
  926. lzo_block = lzo_blocks[blkindex];
  927. /* save the pointer and length of the compressed block */
  928. tmp_dst = lzo_block->dst;
  929. tmp_dst_len = lzo_block->dst_len;
  930. /* prepare the source to be the compressed block */
  931. lzo_block->src = lzo_block->dst;
  932. lzo_block->src_len = lzo_block->dst_len;
  933. /* decompress the block */
  934. ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
  935. if (ret < 0) {
  936. kfree(lzo_block->dst);
  937. goto out;
  938. }
  939. /* write the new value to the cache */
  940. if (snd_soc_set_cache_val(lzo_block->dst, blkpos, value,
  941. codec->driver->reg_word_size)) {
  942. kfree(lzo_block->dst);
  943. goto out;
  944. }
  945. /* prepare the source to be the decompressed block */
  946. lzo_block->src = lzo_block->dst;
  947. lzo_block->src_len = lzo_block->dst_len;
  948. /* compress the block */
  949. ret = snd_soc_lzo_compress_cache_block(codec, lzo_block);
  950. if (ret < 0) {
  951. kfree(lzo_block->dst);
  952. kfree(lzo_block->src);
  953. goto out;
  954. }
  955. /* set the bit so we know we have to sync this register */
  956. set_bit(reg, lzo_block->sync_bmp);
  957. kfree(tmp_dst);
  958. kfree(lzo_block->src);
  959. return 0;
  960. out:
  961. lzo_block->dst = tmp_dst;
  962. lzo_block->dst_len = tmp_dst_len;
  963. return ret;
  964. }
  965. static int snd_soc_lzo_cache_read(struct snd_soc_codec *codec,
  966. unsigned int reg, unsigned int *value)
  967. {
  968. struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
  969. int ret, blkindex, blkpos;
  970. size_t blksize, tmp_dst_len;
  971. void *tmp_dst;
  972. *value = 0;
  973. /* index of the compressed lzo block */
  974. blkindex = snd_soc_lzo_get_blkindex(codec, reg);
  975. /* register index within the decompressed block */
  976. blkpos = snd_soc_lzo_get_blkpos(codec, reg);
  977. /* size of the compressed block */
  978. blksize = snd_soc_lzo_get_blksize(codec);
  979. lzo_blocks = codec->reg_cache;
  980. lzo_block = lzo_blocks[blkindex];
  981. /* save the pointer and length of the compressed block */
  982. tmp_dst = lzo_block->dst;
  983. tmp_dst_len = lzo_block->dst_len;
  984. /* prepare the source to be the compressed block */
  985. lzo_block->src = lzo_block->dst;
  986. lzo_block->src_len = lzo_block->dst_len;
  987. /* decompress the block */
  988. ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
  989. if (ret >= 0)
  990. /* fetch the value from the cache */
  991. *value = snd_soc_get_cache_val(lzo_block->dst, blkpos,
  992. codec->driver->reg_word_size);
  993. kfree(lzo_block->dst);
  994. /* restore the pointer and length of the compressed block */
  995. lzo_block->dst = tmp_dst;
  996. lzo_block->dst_len = tmp_dst_len;
  997. return 0;
  998. }
  999. static int snd_soc_lzo_cache_exit(struct snd_soc_codec *codec)
  1000. {
  1001. struct snd_soc_lzo_ctx **lzo_blocks;
  1002. int i, blkcount;
  1003. lzo_blocks = codec->reg_cache;
  1004. if (!lzo_blocks)
  1005. return 0;
  1006. blkcount = snd_soc_lzo_block_count();
  1007. /*
  1008. * the pointer to the bitmap used for syncing the cache
  1009. * is shared amongst all lzo_blocks. Ensure it is freed
  1010. * only once.
  1011. */
  1012. if (lzo_blocks[0])
  1013. kfree(lzo_blocks[0]->sync_bmp);
  1014. for (i = 0; i < blkcount; ++i) {
  1015. if (lzo_blocks[i]) {
  1016. kfree(lzo_blocks[i]->wmem);
  1017. kfree(lzo_blocks[i]->dst);
  1018. }
  1019. /* each lzo_block is a pointer returned by kmalloc or NULL */
  1020. kfree(lzo_blocks[i]);
  1021. }
  1022. kfree(lzo_blocks);
  1023. codec->reg_cache = NULL;
  1024. return 0;
  1025. }
  1026. static int snd_soc_lzo_cache_init(struct snd_soc_codec *codec)
  1027. {
  1028. struct snd_soc_lzo_ctx **lzo_blocks;
  1029. size_t bmp_size;
  1030. const struct snd_soc_codec_driver *codec_drv;
  1031. int ret, tofree, i, blksize, blkcount;
  1032. const char *p, *end;
  1033. unsigned long *sync_bmp;
  1034. ret = 0;
  1035. codec_drv = codec->driver;
  1036. /*
  1037. * If we have not been given a default register cache
  1038. * then allocate a dummy zero-ed out region, compress it
  1039. * and remember to free it afterwards.
  1040. */
  1041. tofree = 0;
  1042. if (!codec->reg_def_copy)
  1043. tofree = 1;
  1044. if (!codec->reg_def_copy) {
  1045. codec->reg_def_copy = kzalloc(codec->reg_size, GFP_KERNEL);
  1046. if (!codec->reg_def_copy)
  1047. return -ENOMEM;
  1048. }
  1049. blkcount = snd_soc_lzo_block_count();
  1050. codec->reg_cache = kzalloc(blkcount * sizeof *lzo_blocks,
  1051. GFP_KERNEL);
  1052. if (!codec->reg_cache) {
  1053. ret = -ENOMEM;
  1054. goto err_tofree;
  1055. }
  1056. lzo_blocks = codec->reg_cache;
  1057. /*
  1058. * allocate a bitmap to be used when syncing the cache with
  1059. * the hardware. Each time a register is modified, the corresponding
  1060. * bit is set in the bitmap, so we know that we have to sync
  1061. * that register.
  1062. */
  1063. bmp_size = codec_drv->reg_cache_size;
  1064. sync_bmp = kmalloc(BITS_TO_LONGS(bmp_size) * sizeof(long),
  1065. GFP_KERNEL);
  1066. if (!sync_bmp) {
  1067. ret = -ENOMEM;
  1068. goto err;
  1069. }
  1070. bitmap_zero(sync_bmp, bmp_size);
  1071. /* allocate the lzo blocks and initialize them */
  1072. for (i = 0; i < blkcount; ++i) {
  1073. lzo_blocks[i] = kzalloc(sizeof **lzo_blocks,
  1074. GFP_KERNEL);
  1075. if (!lzo_blocks[i]) {
  1076. kfree(sync_bmp);
  1077. ret = -ENOMEM;
  1078. goto err;
  1079. }
  1080. lzo_blocks[i]->sync_bmp = sync_bmp;
  1081. lzo_blocks[i]->sync_bmp_nbits = bmp_size;
  1082. /* alloc the working space for the compressed block */
  1083. ret = snd_soc_lzo_prepare(lzo_blocks[i]);
  1084. if (ret < 0)
  1085. goto err;
  1086. }
  1087. blksize = snd_soc_lzo_get_blksize(codec);
  1088. p = codec->reg_def_copy;
  1089. end = codec->reg_def_copy + codec->reg_size;
  1090. /* compress the register map and fill the lzo blocks */
  1091. for (i = 0; i < blkcount; ++i, p += blksize) {
  1092. lzo_blocks[i]->src = p;
  1093. if (p + blksize > end)
  1094. lzo_blocks[i]->src_len = end - p;
  1095. else
  1096. lzo_blocks[i]->src_len = blksize;
  1097. ret = snd_soc_lzo_compress_cache_block(codec,
  1098. lzo_blocks[i]);
  1099. if (ret < 0)
  1100. goto err;
  1101. lzo_blocks[i]->decompressed_size =
  1102. lzo_blocks[i]->src_len;
  1103. }
  1104. if (tofree) {
  1105. kfree(codec->reg_def_copy);
  1106. codec->reg_def_copy = NULL;
  1107. }
  1108. return 0;
  1109. err:
  1110. snd_soc_cache_exit(codec);
  1111. err_tofree:
  1112. if (tofree) {
  1113. kfree(codec->reg_def_copy);
  1114. codec->reg_def_copy = NULL;
  1115. }
  1116. return ret;
  1117. }
  1118. #endif
  1119. static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec)
  1120. {
  1121. int i;
  1122. int ret;
  1123. const struct snd_soc_codec_driver *codec_drv;
  1124. unsigned int val;
  1125. codec_drv = codec->driver;
  1126. for (i = 0; i < codec_drv->reg_cache_size; ++i) {
  1127. ret = snd_soc_cache_read(codec, i, &val);
  1128. if (ret)
  1129. return ret;
  1130. if (codec->reg_def_copy)
  1131. if (snd_soc_get_cache_val(codec->reg_def_copy,
  1132. i, codec_drv->reg_word_size) == val)
  1133. continue;
  1134. ret = snd_soc_write(codec, i, val);
  1135. if (ret)
  1136. return ret;
  1137. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  1138. i, val);
  1139. }
  1140. return 0;
  1141. }
  1142. static int snd_soc_flat_cache_write(struct snd_soc_codec *codec,
  1143. unsigned int reg, unsigned int value)
  1144. {
  1145. snd_soc_set_cache_val(codec->reg_cache, reg, value,
  1146. codec->driver->reg_word_size);
  1147. return 0;
  1148. }
  1149. static int snd_soc_flat_cache_read(struct snd_soc_codec *codec,
  1150. unsigned int reg, unsigned int *value)
  1151. {
  1152. *value = snd_soc_get_cache_val(codec->reg_cache, reg,
  1153. codec->driver->reg_word_size);
  1154. return 0;
  1155. }
  1156. static int snd_soc_flat_cache_exit(struct snd_soc_codec *codec)
  1157. {
  1158. if (!codec->reg_cache)
  1159. return 0;
  1160. kfree(codec->reg_cache);
  1161. codec->reg_cache = NULL;
  1162. return 0;
  1163. }
  1164. static int snd_soc_flat_cache_init(struct snd_soc_codec *codec)
  1165. {
  1166. const struct snd_soc_codec_driver *codec_drv;
  1167. codec_drv = codec->driver;
  1168. if (codec->reg_def_copy)
  1169. codec->reg_cache = kmemdup(codec->reg_def_copy,
  1170. codec->reg_size, GFP_KERNEL);
  1171. else
  1172. codec->reg_cache = kzalloc(codec->reg_size, GFP_KERNEL);
  1173. if (!codec->reg_cache)
  1174. return -ENOMEM;
  1175. return 0;
  1176. }
  1177. /* an array of all supported compression types */
  1178. static const struct snd_soc_cache_ops cache_types[] = {
  1179. /* Flat *must* be the first entry for fallback */
  1180. {
  1181. .id = SND_SOC_FLAT_COMPRESSION,
  1182. .name = "flat",
  1183. .init = snd_soc_flat_cache_init,
  1184. .exit = snd_soc_flat_cache_exit,
  1185. .read = snd_soc_flat_cache_read,
  1186. .write = snd_soc_flat_cache_write,
  1187. .sync = snd_soc_flat_cache_sync
  1188. },
  1189. #ifdef CONFIG_SND_SOC_CACHE_LZO
  1190. {
  1191. .id = SND_SOC_LZO_COMPRESSION,
  1192. .name = "LZO",
  1193. .init = snd_soc_lzo_cache_init,
  1194. .exit = snd_soc_lzo_cache_exit,
  1195. .read = snd_soc_lzo_cache_read,
  1196. .write = snd_soc_lzo_cache_write,
  1197. .sync = snd_soc_lzo_cache_sync
  1198. },
  1199. #endif
  1200. {
  1201. .id = SND_SOC_RBTREE_COMPRESSION,
  1202. .name = "rbtree",
  1203. .init = snd_soc_rbtree_cache_init,
  1204. .exit = snd_soc_rbtree_cache_exit,
  1205. .read = snd_soc_rbtree_cache_read,
  1206. .write = snd_soc_rbtree_cache_write,
  1207. .sync = snd_soc_rbtree_cache_sync
  1208. }
  1209. };
  1210. int snd_soc_cache_init(struct snd_soc_codec *codec)
  1211. {
  1212. int i;
  1213. for (i = 0; i < ARRAY_SIZE(cache_types); ++i)
  1214. if (cache_types[i].id == codec->compress_type)
  1215. break;
  1216. /* Fall back to flat compression */
  1217. if (i == ARRAY_SIZE(cache_types)) {
  1218. dev_warn(codec->dev, "Could not match compress type: %d\n",
  1219. codec->compress_type);
  1220. i = 0;
  1221. }
  1222. mutex_init(&codec->cache_rw_mutex);
  1223. codec->cache_ops = &cache_types[i];
  1224. if (codec->cache_ops->init) {
  1225. if (codec->cache_ops->name)
  1226. dev_dbg(codec->dev, "Initializing %s cache for %s codec\n",
  1227. codec->cache_ops->name, codec->name);
  1228. return codec->cache_ops->init(codec);
  1229. }
  1230. return -EINVAL;
  1231. }
  1232. /*
  1233. * NOTE: keep in mind that this function might be called
  1234. * multiple times.
  1235. */
  1236. int snd_soc_cache_exit(struct snd_soc_codec *codec)
  1237. {
  1238. if (codec->cache_ops && codec->cache_ops->exit) {
  1239. if (codec->cache_ops->name)
  1240. dev_dbg(codec->dev, "Destroying %s cache for %s codec\n",
  1241. codec->cache_ops->name, codec->name);
  1242. return codec->cache_ops->exit(codec);
  1243. }
  1244. return -EINVAL;
  1245. }
  1246. /**
  1247. * snd_soc_cache_read: Fetch the value of a given register from the cache.
  1248. *
  1249. * @codec: CODEC to configure.
  1250. * @reg: The register index.
  1251. * @value: The value to be returned.
  1252. */
  1253. int snd_soc_cache_read(struct snd_soc_codec *codec,
  1254. unsigned int reg, unsigned int *value)
  1255. {
  1256. int ret;
  1257. mutex_lock(&codec->cache_rw_mutex);
  1258. if (value && codec->cache_ops && codec->cache_ops->read) {
  1259. ret = codec->cache_ops->read(codec, reg, value);
  1260. mutex_unlock(&codec->cache_rw_mutex);
  1261. return ret;
  1262. }
  1263. mutex_unlock(&codec->cache_rw_mutex);
  1264. return -EINVAL;
  1265. }
  1266. EXPORT_SYMBOL_GPL(snd_soc_cache_read);
  1267. /**
  1268. * snd_soc_cache_write: Set the value of a given register in the cache.
  1269. *
  1270. * @codec: CODEC to configure.
  1271. * @reg: The register index.
  1272. * @value: The new register value.
  1273. */
  1274. int snd_soc_cache_write(struct snd_soc_codec *codec,
  1275. unsigned int reg, unsigned int value)
  1276. {
  1277. int ret;
  1278. mutex_lock(&codec->cache_rw_mutex);
  1279. if (codec->cache_ops && codec->cache_ops->write) {
  1280. ret = codec->cache_ops->write(codec, reg, value);
  1281. mutex_unlock(&codec->cache_rw_mutex);
  1282. return ret;
  1283. }
  1284. mutex_unlock(&codec->cache_rw_mutex);
  1285. return -EINVAL;
  1286. }
  1287. EXPORT_SYMBOL_GPL(snd_soc_cache_write);
  1288. /**
  1289. * snd_soc_cache_sync: Sync the register cache with the hardware.
  1290. *
  1291. * @codec: CODEC to configure.
  1292. *
  1293. * Any registers that should not be synced should be marked as
  1294. * volatile. In general drivers can choose not to use the provided
  1295. * syncing functionality if they so require.
  1296. */
  1297. int snd_soc_cache_sync(struct snd_soc_codec *codec)
  1298. {
  1299. int ret;
  1300. const char *name;
  1301. if (!codec->cache_sync) {
  1302. return 0;
  1303. }
  1304. if (!codec->cache_ops || !codec->cache_ops->sync)
  1305. return -EINVAL;
  1306. if (codec->cache_ops->name)
  1307. name = codec->cache_ops->name;
  1308. else
  1309. name = "unknown";
  1310. if (codec->cache_ops->name)
  1311. dev_dbg(codec->dev, "Syncing %s cache for %s codec\n",
  1312. codec->cache_ops->name, codec->name);
  1313. trace_snd_soc_cache_sync(codec, name, "start");
  1314. ret = codec->cache_ops->sync(codec);
  1315. if (!ret)
  1316. codec->cache_sync = 0;
  1317. trace_snd_soc_cache_sync(codec, name, "end");
  1318. return ret;
  1319. }
  1320. EXPORT_SYMBOL_GPL(snd_soc_cache_sync);
  1321. static int snd_soc_get_reg_access_index(struct snd_soc_codec *codec,
  1322. unsigned int reg)
  1323. {
  1324. const struct snd_soc_codec_driver *codec_drv;
  1325. unsigned int min, max, index;
  1326. codec_drv = codec->driver;
  1327. min = 0;
  1328. max = codec_drv->reg_access_size - 1;
  1329. do {
  1330. index = (min + max) / 2;
  1331. if (codec_drv->reg_access_default[index].reg == reg)
  1332. return index;
  1333. if (codec_drv->reg_access_default[index].reg < reg)
  1334. min = index + 1;
  1335. else
  1336. max = index;
  1337. } while (min <= max);
  1338. return -1;
  1339. }
  1340. int snd_soc_default_volatile_register(struct snd_soc_codec *codec,
  1341. unsigned int reg)
  1342. {
  1343. int index;
  1344. if (reg >= codec->driver->reg_cache_size)
  1345. return 1;
  1346. index = snd_soc_get_reg_access_index(codec, reg);
  1347. if (index < 0)
  1348. return 0;
  1349. return codec->driver->reg_access_default[index].vol;
  1350. }
  1351. EXPORT_SYMBOL_GPL(snd_soc_default_volatile_register);
  1352. int snd_soc_default_readable_register(struct snd_soc_codec *codec,
  1353. unsigned int reg)
  1354. {
  1355. int index;
  1356. if (reg >= codec->driver->reg_cache_size)
  1357. return 1;
  1358. index = snd_soc_get_reg_access_index(codec, reg);
  1359. if (index < 0)
  1360. return 0;
  1361. return codec->driver->reg_access_default[index].read;
  1362. }
  1363. EXPORT_SYMBOL_GPL(snd_soc_default_readable_register);