intel_crt.c 19 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "drm_crtc.h"
  32. #include "drm_crtc_helper.h"
  33. #include "drm_edid.h"
  34. #include "intel_drv.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  39. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  40. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  41. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  42. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  43. ADPA_CRT_HOTPLUG_ENABLE)
  44. struct intel_crt {
  45. struct intel_encoder base;
  46. bool force_hotplug_required;
  47. u32 adpa_reg;
  48. };
  49. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  50. {
  51. return container_of(intel_attached_encoder(connector),
  52. struct intel_crt, base);
  53. }
  54. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  55. {
  56. return container_of(encoder, struct intel_crt, base);
  57. }
  58. static void pch_crt_dpms(struct drm_encoder *encoder, int mode)
  59. {
  60. struct drm_device *dev = encoder->dev;
  61. struct drm_i915_private *dev_priv = dev->dev_private;
  62. u32 temp;
  63. temp = I915_READ(PCH_ADPA);
  64. temp &= ~ADPA_DAC_ENABLE;
  65. switch (mode) {
  66. case DRM_MODE_DPMS_ON:
  67. temp |= ADPA_DAC_ENABLE;
  68. break;
  69. case DRM_MODE_DPMS_STANDBY:
  70. case DRM_MODE_DPMS_SUSPEND:
  71. case DRM_MODE_DPMS_OFF:
  72. /* Just leave port enable cleared */
  73. break;
  74. }
  75. I915_WRITE(PCH_ADPA, temp);
  76. }
  77. static void gmch_crt_dpms(struct drm_encoder *encoder, int mode)
  78. {
  79. struct drm_device *dev = encoder->dev;
  80. struct drm_i915_private *dev_priv = dev->dev_private;
  81. u32 temp;
  82. temp = I915_READ(ADPA);
  83. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  84. temp &= ~ADPA_DAC_ENABLE;
  85. if (IS_VALLEYVIEW(dev) && mode != DRM_MODE_DPMS_ON)
  86. mode = DRM_MODE_DPMS_OFF;
  87. switch (mode) {
  88. case DRM_MODE_DPMS_ON:
  89. temp |= ADPA_DAC_ENABLE;
  90. break;
  91. case DRM_MODE_DPMS_STANDBY:
  92. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  93. break;
  94. case DRM_MODE_DPMS_SUSPEND:
  95. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  96. break;
  97. case DRM_MODE_DPMS_OFF:
  98. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  99. break;
  100. }
  101. I915_WRITE(ADPA, temp);
  102. }
  103. static int intel_crt_mode_valid(struct drm_connector *connector,
  104. struct drm_display_mode *mode)
  105. {
  106. struct drm_device *dev = connector->dev;
  107. int max_clock = 0;
  108. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  109. return MODE_NO_DBLESCAN;
  110. if (mode->clock < 25000)
  111. return MODE_CLOCK_LOW;
  112. if (IS_GEN2(dev))
  113. max_clock = 350000;
  114. else
  115. max_clock = 400000;
  116. if (mode->clock > max_clock)
  117. return MODE_CLOCK_HIGH;
  118. return MODE_OK;
  119. }
  120. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  121. const struct drm_display_mode *mode,
  122. struct drm_display_mode *adjusted_mode)
  123. {
  124. return true;
  125. }
  126. static void intel_crt_mode_set(struct drm_encoder *encoder,
  127. struct drm_display_mode *mode,
  128. struct drm_display_mode *adjusted_mode)
  129. {
  130. struct drm_device *dev = encoder->dev;
  131. struct drm_crtc *crtc = encoder->crtc;
  132. struct intel_crt *crt =
  133. intel_encoder_to_crt(to_intel_encoder(encoder));
  134. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  135. struct drm_i915_private *dev_priv = dev->dev_private;
  136. int dpll_md_reg;
  137. u32 adpa, dpll_md;
  138. dpll_md_reg = DPLL_MD(intel_crtc->pipe);
  139. /*
  140. * Disable separate mode multiplier used when cloning SDVO to CRT
  141. * XXX this needs to be adjusted when we really are cloning
  142. */
  143. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  144. dpll_md = I915_READ(dpll_md_reg);
  145. I915_WRITE(dpll_md_reg,
  146. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  147. }
  148. adpa = ADPA_HOTPLUG_BITS;
  149. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  150. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  151. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  152. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  153. /* For CPT allow 3 pipe config, for others just use A or B */
  154. if (HAS_PCH_CPT(dev))
  155. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  156. else if (intel_crtc->pipe == 0)
  157. adpa |= ADPA_PIPE_A_SELECT;
  158. else
  159. adpa |= ADPA_PIPE_B_SELECT;
  160. if (!HAS_PCH_SPLIT(dev))
  161. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  162. I915_WRITE(crt->adpa_reg, adpa);
  163. }
  164. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  165. {
  166. struct drm_device *dev = connector->dev;
  167. struct intel_crt *crt = intel_attached_crt(connector);
  168. struct drm_i915_private *dev_priv = dev->dev_private;
  169. u32 adpa;
  170. bool ret;
  171. /* The first time through, trigger an explicit detection cycle */
  172. if (crt->force_hotplug_required) {
  173. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  174. u32 save_adpa;
  175. crt->force_hotplug_required = 0;
  176. save_adpa = adpa = I915_READ(PCH_ADPA);
  177. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  178. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  179. if (turn_off_dac)
  180. adpa &= ~ADPA_DAC_ENABLE;
  181. I915_WRITE(PCH_ADPA, adpa);
  182. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  183. 1000))
  184. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  185. if (turn_off_dac) {
  186. I915_WRITE(PCH_ADPA, save_adpa);
  187. POSTING_READ(PCH_ADPA);
  188. }
  189. }
  190. /* Check the status to see if both blue and green are on now */
  191. adpa = I915_READ(PCH_ADPA);
  192. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  193. ret = true;
  194. else
  195. ret = false;
  196. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  197. return ret;
  198. }
  199. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  200. {
  201. struct drm_device *dev = connector->dev;
  202. struct drm_i915_private *dev_priv = dev->dev_private;
  203. u32 adpa;
  204. bool ret;
  205. u32 save_adpa;
  206. save_adpa = adpa = I915_READ(ADPA);
  207. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  208. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  209. I915_WRITE(ADPA, adpa);
  210. if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  211. 1000)) {
  212. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  213. I915_WRITE(ADPA, save_adpa);
  214. }
  215. /* Check the status to see if both blue and green are on now */
  216. adpa = I915_READ(ADPA);
  217. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  218. ret = true;
  219. else
  220. ret = false;
  221. DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  222. /* FIXME: debug force function and remove */
  223. ret = true;
  224. return ret;
  225. }
  226. /**
  227. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  228. *
  229. * Not for i915G/i915GM
  230. *
  231. * \return true if CRT is connected.
  232. * \return false if CRT is disconnected.
  233. */
  234. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  235. {
  236. struct drm_device *dev = connector->dev;
  237. struct drm_i915_private *dev_priv = dev->dev_private;
  238. u32 hotplug_en, orig, stat;
  239. bool ret = false;
  240. int i, tries = 0;
  241. if (HAS_PCH_SPLIT(dev))
  242. return intel_ironlake_crt_detect_hotplug(connector);
  243. if (IS_VALLEYVIEW(dev))
  244. return valleyview_crt_detect_hotplug(connector);
  245. /*
  246. * On 4 series desktop, CRT detect sequence need to be done twice
  247. * to get a reliable result.
  248. */
  249. if (IS_G4X(dev) && !IS_GM45(dev))
  250. tries = 2;
  251. else
  252. tries = 1;
  253. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  254. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  255. for (i = 0; i < tries ; i++) {
  256. /* turn on the FORCE_DETECT */
  257. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  258. /* wait for FORCE_DETECT to go off */
  259. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  260. CRT_HOTPLUG_FORCE_DETECT) == 0,
  261. 1000))
  262. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  263. }
  264. stat = I915_READ(PORT_HOTPLUG_STAT);
  265. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  266. ret = true;
  267. /* clear the interrupt we just generated, if any */
  268. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  269. /* and put the bits back */
  270. I915_WRITE(PORT_HOTPLUG_EN, orig);
  271. return ret;
  272. }
  273. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  274. {
  275. struct intel_crt *crt = intel_attached_crt(connector);
  276. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  277. struct edid *edid;
  278. struct i2c_adapter *i2c;
  279. BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  280. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  281. edid = drm_get_edid(connector, i2c);
  282. if (edid) {
  283. bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  284. /*
  285. * This may be a DVI-I connector with a shared DDC
  286. * link between analog and digital outputs, so we
  287. * have to check the EDID input spec of the attached device.
  288. */
  289. if (!is_digital) {
  290. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  291. return true;
  292. }
  293. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  294. } else {
  295. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  296. }
  297. kfree(edid);
  298. return false;
  299. }
  300. static enum drm_connector_status
  301. intel_crt_load_detect(struct intel_crt *crt)
  302. {
  303. struct drm_device *dev = crt->base.base.dev;
  304. struct drm_i915_private *dev_priv = dev->dev_private;
  305. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  306. uint32_t save_bclrpat;
  307. uint32_t save_vtotal;
  308. uint32_t vtotal, vactive;
  309. uint32_t vsample;
  310. uint32_t vblank, vblank_start, vblank_end;
  311. uint32_t dsl;
  312. uint32_t bclrpat_reg;
  313. uint32_t vtotal_reg;
  314. uint32_t vblank_reg;
  315. uint32_t vsync_reg;
  316. uint32_t pipeconf_reg;
  317. uint32_t pipe_dsl_reg;
  318. uint8_t st00;
  319. enum drm_connector_status status;
  320. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  321. bclrpat_reg = BCLRPAT(pipe);
  322. vtotal_reg = VTOTAL(pipe);
  323. vblank_reg = VBLANK(pipe);
  324. vsync_reg = VSYNC(pipe);
  325. pipeconf_reg = PIPECONF(pipe);
  326. pipe_dsl_reg = PIPEDSL(pipe);
  327. save_bclrpat = I915_READ(bclrpat_reg);
  328. save_vtotal = I915_READ(vtotal_reg);
  329. vblank = I915_READ(vblank_reg);
  330. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  331. vactive = (save_vtotal & 0x7ff) + 1;
  332. vblank_start = (vblank & 0xfff) + 1;
  333. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  334. /* Set the border color to purple. */
  335. I915_WRITE(bclrpat_reg, 0x500050);
  336. if (!IS_GEN2(dev)) {
  337. uint32_t pipeconf = I915_READ(pipeconf_reg);
  338. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  339. POSTING_READ(pipeconf_reg);
  340. /* Wait for next Vblank to substitue
  341. * border color for Color info */
  342. intel_wait_for_vblank(dev, pipe);
  343. st00 = I915_READ8(VGA_MSR_WRITE);
  344. status = ((st00 & (1 << 4)) != 0) ?
  345. connector_status_connected :
  346. connector_status_disconnected;
  347. I915_WRITE(pipeconf_reg, pipeconf);
  348. } else {
  349. bool restore_vblank = false;
  350. int count, detect;
  351. /*
  352. * If there isn't any border, add some.
  353. * Yes, this will flicker
  354. */
  355. if (vblank_start <= vactive && vblank_end >= vtotal) {
  356. uint32_t vsync = I915_READ(vsync_reg);
  357. uint32_t vsync_start = (vsync & 0xffff) + 1;
  358. vblank_start = vsync_start;
  359. I915_WRITE(vblank_reg,
  360. (vblank_start - 1) |
  361. ((vblank_end - 1) << 16));
  362. restore_vblank = true;
  363. }
  364. /* sample in the vertical border, selecting the larger one */
  365. if (vblank_start - vactive >= vtotal - vblank_end)
  366. vsample = (vblank_start + vactive) >> 1;
  367. else
  368. vsample = (vtotal + vblank_end) >> 1;
  369. /*
  370. * Wait for the border to be displayed
  371. */
  372. while (I915_READ(pipe_dsl_reg) >= vactive)
  373. ;
  374. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  375. ;
  376. /*
  377. * Watch ST00 for an entire scanline
  378. */
  379. detect = 0;
  380. count = 0;
  381. do {
  382. count++;
  383. /* Read the ST00 VGA status register */
  384. st00 = I915_READ8(VGA_MSR_WRITE);
  385. if (st00 & (1 << 4))
  386. detect++;
  387. } while ((I915_READ(pipe_dsl_reg) == dsl));
  388. /* restore vblank if necessary */
  389. if (restore_vblank)
  390. I915_WRITE(vblank_reg, vblank);
  391. /*
  392. * If more than 3/4 of the scanline detected a monitor,
  393. * then it is assumed to be present. This works even on i830,
  394. * where there isn't any way to force the border color across
  395. * the screen
  396. */
  397. status = detect * 4 > count * 3 ?
  398. connector_status_connected :
  399. connector_status_disconnected;
  400. }
  401. /* Restore previous settings */
  402. I915_WRITE(bclrpat_reg, save_bclrpat);
  403. return status;
  404. }
  405. static enum drm_connector_status
  406. intel_crt_detect(struct drm_connector *connector, bool force)
  407. {
  408. struct drm_device *dev = connector->dev;
  409. struct intel_crt *crt = intel_attached_crt(connector);
  410. enum drm_connector_status status;
  411. struct intel_load_detect_pipe tmp;
  412. if (I915_HAS_HOTPLUG(dev)) {
  413. /* We can not rely on the HPD pin always being correctly wired
  414. * up, for example many KVM do not pass it through, and so
  415. * only trust an assertion that the monitor is connected.
  416. */
  417. if (intel_crt_detect_hotplug(connector)) {
  418. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  419. return connector_status_connected;
  420. } else
  421. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  422. }
  423. if (intel_crt_detect_ddc(connector))
  424. return connector_status_connected;
  425. /* Load detection is broken on HPD capable machines. Whoever wants a
  426. * broken monitor (without edid) to work behind a broken kvm (that fails
  427. * to have the right resistors for HP detection) needs to fix this up.
  428. * For now just bail out. */
  429. if (I915_HAS_HOTPLUG(dev))
  430. return connector_status_disconnected;
  431. if (!force)
  432. return connector->status;
  433. /* for pre-945g platforms use load detect */
  434. if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
  435. &tmp)) {
  436. if (intel_crt_detect_ddc(connector))
  437. status = connector_status_connected;
  438. else
  439. status = intel_crt_load_detect(crt);
  440. intel_release_load_detect_pipe(&crt->base, connector,
  441. &tmp);
  442. } else
  443. status = connector_status_unknown;
  444. return status;
  445. }
  446. static void intel_crt_destroy(struct drm_connector *connector)
  447. {
  448. drm_sysfs_connector_remove(connector);
  449. drm_connector_cleanup(connector);
  450. kfree(connector);
  451. }
  452. static int intel_crt_get_modes(struct drm_connector *connector)
  453. {
  454. struct drm_device *dev = connector->dev;
  455. struct drm_i915_private *dev_priv = dev->dev_private;
  456. int ret;
  457. struct i2c_adapter *i2c;
  458. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  459. ret = intel_ddc_get_modes(connector, i2c);
  460. if (ret || !IS_G4X(dev))
  461. return ret;
  462. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  463. i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  464. return intel_ddc_get_modes(connector, i2c);
  465. }
  466. static int intel_crt_set_property(struct drm_connector *connector,
  467. struct drm_property *property,
  468. uint64_t value)
  469. {
  470. return 0;
  471. }
  472. static void intel_crt_reset(struct drm_connector *connector)
  473. {
  474. struct drm_device *dev = connector->dev;
  475. struct intel_crt *crt = intel_attached_crt(connector);
  476. if (HAS_PCH_SPLIT(dev))
  477. crt->force_hotplug_required = 1;
  478. }
  479. /*
  480. * Routines for controlling stuff on the analog port
  481. */
  482. static const struct drm_encoder_helper_funcs pch_encoder_funcs = {
  483. .mode_fixup = intel_crt_mode_fixup,
  484. .prepare = intel_encoder_prepare,
  485. .commit = intel_encoder_commit,
  486. .mode_set = intel_crt_mode_set,
  487. .dpms = pch_crt_dpms,
  488. };
  489. static const struct drm_encoder_helper_funcs gmch_encoder_funcs = {
  490. .mode_fixup = intel_crt_mode_fixup,
  491. .prepare = intel_encoder_prepare,
  492. .commit = intel_encoder_commit,
  493. .mode_set = intel_crt_mode_set,
  494. .dpms = gmch_crt_dpms,
  495. };
  496. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  497. .reset = intel_crt_reset,
  498. .dpms = drm_helper_connector_dpms,
  499. .detect = intel_crt_detect,
  500. .fill_modes = drm_helper_probe_single_connector_modes,
  501. .destroy = intel_crt_destroy,
  502. .set_property = intel_crt_set_property,
  503. };
  504. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  505. .mode_valid = intel_crt_mode_valid,
  506. .get_modes = intel_crt_get_modes,
  507. .best_encoder = intel_best_encoder,
  508. };
  509. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  510. .destroy = intel_encoder_destroy,
  511. };
  512. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  513. {
  514. DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  515. return 1;
  516. }
  517. static const struct dmi_system_id intel_no_crt[] = {
  518. {
  519. .callback = intel_no_crt_dmi_callback,
  520. .ident = "ACER ZGB",
  521. .matches = {
  522. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  523. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  524. },
  525. },
  526. { }
  527. };
  528. void intel_crt_init(struct drm_device *dev)
  529. {
  530. struct drm_connector *connector;
  531. struct intel_crt *crt;
  532. struct intel_connector *intel_connector;
  533. struct drm_i915_private *dev_priv = dev->dev_private;
  534. const struct drm_encoder_helper_funcs *encoder_helper_funcs;
  535. /* Skip machines without VGA that falsely report hotplug events */
  536. if (dmi_check_system(intel_no_crt))
  537. return;
  538. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  539. if (!crt)
  540. return;
  541. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  542. if (!intel_connector) {
  543. kfree(crt);
  544. return;
  545. }
  546. connector = &intel_connector->base;
  547. drm_connector_init(dev, &intel_connector->base,
  548. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  549. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  550. DRM_MODE_ENCODER_DAC);
  551. intel_connector_attach_encoder(intel_connector, &crt->base);
  552. crt->base.type = INTEL_OUTPUT_ANALOG;
  553. crt->base.cloneable = true;
  554. if (IS_HASWELL(dev))
  555. crt->base.crtc_mask = (1 << 0);
  556. else
  557. crt->base.crtc_mask = (1 << 0) | (1 << 1);
  558. if (IS_GEN2(dev))
  559. connector->interlace_allowed = 0;
  560. else
  561. connector->interlace_allowed = 1;
  562. connector->doublescan_allowed = 0;
  563. if (HAS_PCH_SPLIT(dev))
  564. encoder_helper_funcs = &pch_encoder_funcs;
  565. else
  566. encoder_helper_funcs = &gmch_encoder_funcs;
  567. if (HAS_PCH_SPLIT(dev))
  568. crt->adpa_reg = PCH_ADPA;
  569. else if (IS_VALLEYVIEW(dev))
  570. crt->adpa_reg = VLV_ADPA;
  571. else
  572. crt->adpa_reg = ADPA;
  573. drm_encoder_helper_add(&crt->base.base, encoder_helper_funcs);
  574. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  575. drm_sysfs_connector_add(connector);
  576. if (I915_HAS_HOTPLUG(dev))
  577. connector->polled = DRM_CONNECTOR_POLL_HPD;
  578. else
  579. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  580. /*
  581. * Configure the automatic hotplug detection stuff
  582. */
  583. crt->force_hotplug_required = 0;
  584. if (HAS_PCH_SPLIT(dev)) {
  585. u32 adpa;
  586. adpa = I915_READ(PCH_ADPA);
  587. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  588. adpa |= ADPA_HOTPLUG_BITS;
  589. I915_WRITE(PCH_ADPA, adpa);
  590. POSTING_READ(PCH_ADPA);
  591. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  592. crt->force_hotplug_required = 1;
  593. }
  594. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  595. }