iwl3945-base.c 217 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-fh.h"
  47. #include "iwl-3945-fh.h"
  48. #include "iwl-commands.h"
  49. #include "iwl-3945.h"
  50. #include "iwl-helpers.h"
  51. #include "iwl-core.h"
  52. #include "iwl-dev.h"
  53. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  54. struct iwl_tx_queue *txq);
  55. /*
  56. * module name, copyright, version, etc.
  57. */
  58. #define DRV_DESCRIPTION \
  59. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  60. #ifdef CONFIG_IWL3945_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define IWL39_VERSION "1.2.26k" VD VS
  71. #define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
  72. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  73. #define DRV_VERSION IWL39_VERSION
  74. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  75. MODULE_VERSION(DRV_VERSION);
  76. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  77. MODULE_LICENSE("GPL");
  78. /* module parameters */
  79. struct iwl_mod_params iwl3945_mod_params = {
  80. .num_of_queues = IWL39_MAX_NUM_QUEUES,
  81. .sw_crypto = 1,
  82. /* the rest are 0 by default */
  83. };
  84. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  85. * DMA services
  86. *
  87. * Theory of operation
  88. *
  89. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  90. * of buffer descriptors, each of which points to one or more data buffers for
  91. * the device to read from or fill. Driver and device exchange status of each
  92. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  93. * entries in each circular buffer, to protect against confusing empty and full
  94. * queue states.
  95. *
  96. * The device reads or writes the data in the queues via the device's several
  97. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  98. *
  99. * For Tx queue, there are low mark and high mark limits. If, after queuing
  100. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  101. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  102. * Tx queue resumed.
  103. *
  104. * The 3945 operates with six queues: One receive queue, one transmit queue
  105. * (#4) for sending commands to the device firmware, and four transmit queues
  106. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  107. ***************************************************/
  108. /**
  109. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  110. */
  111. static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  112. int count, int slots_num, u32 id)
  113. {
  114. q->n_bd = count;
  115. q->n_window = slots_num;
  116. q->id = id;
  117. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  118. * and iwl_queue_dec_wrap are broken. */
  119. BUG_ON(!is_power_of_2(count));
  120. /* slots_num must be power-of-two size, otherwise
  121. * get_cmd_index is broken. */
  122. BUG_ON(!is_power_of_2(slots_num));
  123. q->low_mark = q->n_window / 4;
  124. if (q->low_mark < 4)
  125. q->low_mark = 4;
  126. q->high_mark = q->n_window / 8;
  127. if (q->high_mark < 2)
  128. q->high_mark = 2;
  129. q->write_ptr = q->read_ptr = 0;
  130. return 0;
  131. }
  132. /**
  133. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  134. */
  135. static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
  136. struct iwl_tx_queue *txq, u32 id)
  137. {
  138. struct pci_dev *dev = priv->pci_dev;
  139. /* Driver private data, only for Tx (not command) queues,
  140. * not shared with device. */
  141. if (id != IWL_CMD_QUEUE_NUM) {
  142. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  143. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  144. if (!txq->txb) {
  145. IWL_ERR(priv, "kmalloc for auxiliary BD "
  146. "structures failed\n");
  147. goto error;
  148. }
  149. } else
  150. txq->txb = NULL;
  151. /* Circular buffer of transmit frame descriptors (TFDs),
  152. * shared with device */
  153. txq->tfds39 = pci_alloc_consistent(dev,
  154. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
  155. &txq->q.dma_addr);
  156. if (!txq->tfds39) {
  157. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
  158. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
  159. goto error;
  160. }
  161. txq->q.id = id;
  162. return 0;
  163. error:
  164. kfree(txq->txb);
  165. txq->txb = NULL;
  166. return -ENOMEM;
  167. }
  168. /**
  169. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  170. */
  171. int iwl3945_tx_queue_init(struct iwl_priv *priv,
  172. struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
  173. {
  174. int len, i;
  175. int rc = 0;
  176. /*
  177. * Alloc buffer array for commands (Tx or other types of commands).
  178. * For the command queue (#4), allocate command space + one big
  179. * command for scan, since scan command is very huge; the system will
  180. * not have two scans at the same time, so only one is needed.
  181. * For data Tx queues (all other queues), no super-size command
  182. * space is needed.
  183. */
  184. len = sizeof(struct iwl_cmd);
  185. for (i = 0; i <= slots_num; i++) {
  186. if (i == slots_num) {
  187. if (txq_id == IWL_CMD_QUEUE_NUM)
  188. len += IWL_MAX_SCAN_SIZE;
  189. else
  190. continue;
  191. }
  192. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  193. if (!txq->cmd[i])
  194. goto err;
  195. }
  196. /* Alloc driver data array and TFD circular buffer */
  197. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  198. if (rc)
  199. goto err;
  200. txq->need_update = 0;
  201. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  202. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  203. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  204. /* Initialize queue high/low-water, head/tail indexes */
  205. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  206. /* Tell device where to find queue, enable DMA channel. */
  207. iwl3945_hw_tx_queue_init(priv, txq);
  208. return 0;
  209. err:
  210. for (i = 0; i < slots_num; i++) {
  211. kfree(txq->cmd[i]);
  212. txq->cmd[i] = NULL;
  213. }
  214. if (txq_id == IWL_CMD_QUEUE_NUM) {
  215. kfree(txq->cmd[slots_num]);
  216. txq->cmd[slots_num] = NULL;
  217. }
  218. return -ENOMEM;
  219. }
  220. /**
  221. * iwl3945_tx_queue_free - Deallocate DMA queue.
  222. * @txq: Transmit queue to deallocate.
  223. *
  224. * Empty queue by removing and destroying all BD's.
  225. * Free all buffers.
  226. * 0-fill, but do not free "txq" descriptor structure.
  227. */
  228. void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  229. {
  230. struct iwl_queue *q = &txq->q;
  231. struct pci_dev *dev = priv->pci_dev;
  232. int len, i;
  233. if (q->n_bd == 0)
  234. return;
  235. /* first, empty all BD's */
  236. for (; q->write_ptr != q->read_ptr;
  237. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  238. iwl3945_hw_txq_free_tfd(priv, txq);
  239. len = sizeof(struct iwl_cmd) * q->n_window;
  240. if (q->id == IWL_CMD_QUEUE_NUM)
  241. len += IWL_MAX_SCAN_SIZE;
  242. /* De-alloc array of command/tx buffers */
  243. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  244. kfree(txq->cmd[i]);
  245. /* De-alloc circular buffer of TFDs */
  246. if (txq->q.n_bd)
  247. pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
  248. txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
  249. /* De-alloc array of per-TFD driver data */
  250. kfree(txq->txb);
  251. txq->txb = NULL;
  252. /* 0-fill queue descriptor structure */
  253. memset(txq, 0, sizeof(*txq));
  254. }
  255. /*************** STATION TABLE MANAGEMENT ****
  256. * mac80211 should be examined to determine if sta_info is duplicating
  257. * the functionality provided here
  258. */
  259. /**************************************************************/
  260. #if 0 /* temporary disable till we add real remove station */
  261. /**
  262. * iwl3945_remove_station - Remove driver's knowledge of station.
  263. *
  264. * NOTE: This does not remove station from device's station table.
  265. */
  266. static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  267. {
  268. int index = IWL_INVALID_STATION;
  269. int i;
  270. unsigned long flags;
  271. spin_lock_irqsave(&priv->sta_lock, flags);
  272. if (is_ap)
  273. index = IWL_AP_ID;
  274. else if (is_broadcast_ether_addr(addr))
  275. index = priv->hw_params.bcast_sta_id;
  276. else
  277. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
  278. if (priv->stations_39[i].used &&
  279. !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  280. addr)) {
  281. index = i;
  282. break;
  283. }
  284. if (unlikely(index == IWL_INVALID_STATION))
  285. goto out;
  286. if (priv->stations_39[index].used) {
  287. priv->stations_39[index].used = 0;
  288. priv->num_stations--;
  289. }
  290. BUG_ON(priv->num_stations < 0);
  291. out:
  292. spin_unlock_irqrestore(&priv->sta_lock, flags);
  293. return 0;
  294. }
  295. #endif
  296. /**
  297. * iwl3945_clear_stations_table - Clear the driver's station table
  298. *
  299. * NOTE: This does not clear or otherwise alter the device's station table.
  300. */
  301. static void iwl3945_clear_stations_table(struct iwl_priv *priv)
  302. {
  303. unsigned long flags;
  304. spin_lock_irqsave(&priv->sta_lock, flags);
  305. priv->num_stations = 0;
  306. memset(priv->stations_39, 0, sizeof(priv->stations_39));
  307. spin_unlock_irqrestore(&priv->sta_lock, flags);
  308. }
  309. /**
  310. * iwl3945_add_station - Add station to station tables in driver and device
  311. */
  312. u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
  313. {
  314. int i;
  315. int index = IWL_INVALID_STATION;
  316. struct iwl3945_station_entry *station;
  317. unsigned long flags_spin;
  318. u8 rate;
  319. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  320. if (is_ap)
  321. index = IWL_AP_ID;
  322. else if (is_broadcast_ether_addr(addr))
  323. index = priv->hw_params.bcast_sta_id;
  324. else
  325. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
  326. if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  327. addr)) {
  328. index = i;
  329. break;
  330. }
  331. if (!priv->stations_39[i].used &&
  332. index == IWL_INVALID_STATION)
  333. index = i;
  334. }
  335. /* These two conditions has the same outcome but keep them separate
  336. since they have different meaning */
  337. if (unlikely(index == IWL_INVALID_STATION)) {
  338. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  339. return index;
  340. }
  341. if (priv->stations_39[index].used &&
  342. !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
  343. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  344. return index;
  345. }
  346. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  347. station = &priv->stations_39[index];
  348. station->used = 1;
  349. priv->num_stations++;
  350. /* Set up the REPLY_ADD_STA command to send to device */
  351. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  352. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  353. station->sta.mode = 0;
  354. station->sta.sta.sta_id = index;
  355. station->sta.station_flags = 0;
  356. if (priv->band == IEEE80211_BAND_5GHZ)
  357. rate = IWL_RATE_6M_PLCP;
  358. else
  359. rate = IWL_RATE_1M_PLCP;
  360. /* Turn on both antennas for the station... */
  361. station->sta.rate_n_flags =
  362. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  363. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  364. /* Add station to device's station table */
  365. iwl3945_send_add_station(priv, &station->sta, flags);
  366. return index;
  367. }
  368. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  369. #define IWL_CMD(x) case x: return #x
  370. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  371. /**
  372. * iwl3945_enqueue_hcmd - enqueue a uCode command
  373. * @priv: device private data point
  374. * @cmd: a point to the ucode command structure
  375. *
  376. * The function returns < 0 values to indicate the operation is
  377. * failed. On success, it turns the index (> 0) of command in the
  378. * command queue.
  379. */
  380. static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  381. {
  382. struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  383. struct iwl_queue *q = &txq->q;
  384. struct iwl3945_tfd *tfd;
  385. struct iwl_cmd *out_cmd;
  386. u32 idx;
  387. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  388. dma_addr_t phys_addr;
  389. int pad;
  390. int ret, len;
  391. unsigned long flags;
  392. /* If any of the command structures end up being larger than
  393. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  394. * we will need to increase the size of the TFD entries */
  395. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  396. !(cmd->meta.flags & CMD_SIZE_HUGE));
  397. if (iwl_is_rfkill(priv)) {
  398. IWL_DEBUG_INFO("Not sending command - RF KILL");
  399. return -EIO;
  400. }
  401. if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  402. IWL_ERR(priv, "No space for Tx\n");
  403. return -ENOSPC;
  404. }
  405. spin_lock_irqsave(&priv->hcmd_lock, flags);
  406. tfd = &txq->tfds39[q->write_ptr];
  407. memset(tfd, 0, sizeof(*tfd));
  408. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  409. out_cmd = txq->cmd[idx];
  410. out_cmd->hdr.cmd = cmd->id;
  411. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  412. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  413. /* At this point, the out_cmd now has all of the incoming cmd
  414. * information */
  415. out_cmd->hdr.flags = 0;
  416. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  417. INDEX_TO_SEQ(q->write_ptr));
  418. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  419. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  420. len = (idx == TFD_CMD_SLOTS) ?
  421. IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
  422. phys_addr = pci_map_single(priv->pci_dev, out_cmd,
  423. len, PCI_DMA_TODEVICE);
  424. pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
  425. pci_unmap_len_set(&out_cmd->meta, len, len);
  426. phys_addr += offsetof(struct iwl_cmd, hdr);
  427. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  428. pad = U32_PAD(cmd->len);
  429. tfd->control_flags |= cpu_to_le32(TFD_CTL_PAD_SET(pad));
  430. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  431. "%d bytes at %d[%d]:%d\n",
  432. get_cmd_string(out_cmd->hdr.cmd),
  433. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  434. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  435. txq->need_update = 1;
  436. /* Increment and update queue's write index */
  437. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  438. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  439. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  440. return ret ? ret : idx;
  441. }
  442. static int iwl3945_send_cmd_async(struct iwl_priv *priv,
  443. struct iwl_host_cmd *cmd)
  444. {
  445. int ret;
  446. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  447. /* An asynchronous command can not expect an SKB to be set. */
  448. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  449. /* An asynchronous command MUST have a callback. */
  450. BUG_ON(!cmd->meta.u.callback);
  451. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  452. return -EBUSY;
  453. ret = iwl3945_enqueue_hcmd(priv, cmd);
  454. if (ret < 0) {
  455. IWL_ERR(priv,
  456. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  457. get_cmd_string(cmd->id), ret);
  458. return ret;
  459. }
  460. return 0;
  461. }
  462. static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
  463. struct iwl_host_cmd *cmd)
  464. {
  465. int cmd_idx;
  466. int ret;
  467. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  468. /* A synchronous command can not have a callback set. */
  469. BUG_ON(cmd->meta.u.callback != NULL);
  470. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  471. IWL_ERR(priv,
  472. "Error sending %s: Already sending a host command\n",
  473. get_cmd_string(cmd->id));
  474. ret = -EBUSY;
  475. goto out;
  476. }
  477. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  478. if (cmd->meta.flags & CMD_WANT_SKB)
  479. cmd->meta.source = &cmd->meta;
  480. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  481. if (cmd_idx < 0) {
  482. ret = cmd_idx;
  483. IWL_ERR(priv,
  484. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  485. get_cmd_string(cmd->id), ret);
  486. goto out;
  487. }
  488. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  489. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  490. HOST_COMPLETE_TIMEOUT);
  491. if (!ret) {
  492. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  493. IWL_ERR(priv, "Error sending %s: time out after %dms\n",
  494. get_cmd_string(cmd->id),
  495. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  496. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  497. ret = -ETIMEDOUT;
  498. goto cancel;
  499. }
  500. }
  501. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  502. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  503. get_cmd_string(cmd->id));
  504. ret = -ECANCELED;
  505. goto fail;
  506. }
  507. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  508. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  509. get_cmd_string(cmd->id));
  510. ret = -EIO;
  511. goto fail;
  512. }
  513. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  514. IWL_ERR(priv, "Error: Response NULL in '%s'\n",
  515. get_cmd_string(cmd->id));
  516. ret = -EIO;
  517. goto cancel;
  518. }
  519. ret = 0;
  520. goto out;
  521. cancel:
  522. if (cmd->meta.flags & CMD_WANT_SKB) {
  523. struct iwl_cmd *qcmd;
  524. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  525. * TX cmd queue. Otherwise in case the cmd comes
  526. * in later, it will possibly set an invalid
  527. * address (cmd->meta.source). */
  528. qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  529. qcmd->meta.flags &= ~CMD_WANT_SKB;
  530. }
  531. fail:
  532. if (cmd->meta.u.skb) {
  533. dev_kfree_skb_any(cmd->meta.u.skb);
  534. cmd->meta.u.skb = NULL;
  535. }
  536. out:
  537. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  538. return ret;
  539. }
  540. int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  541. {
  542. if (cmd->meta.flags & CMD_ASYNC)
  543. return iwl3945_send_cmd_async(priv, cmd);
  544. return iwl3945_send_cmd_sync(priv, cmd);
  545. }
  546. int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
  547. {
  548. struct iwl_host_cmd cmd = {
  549. .id = id,
  550. .len = len,
  551. .data = data,
  552. };
  553. return iwl3945_send_cmd_sync(priv, &cmd);
  554. }
  555. static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
  556. {
  557. struct iwl_host_cmd cmd = {
  558. .id = id,
  559. .len = sizeof(val),
  560. .data = &val,
  561. };
  562. return iwl3945_send_cmd_sync(priv, &cmd);
  563. }
  564. int iwl3945_send_statistics_request(struct iwl_priv *priv)
  565. {
  566. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  567. }
  568. /**
  569. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  570. * @band: 2.4 or 5 GHz band
  571. * @channel: Any channel valid for the requested band
  572. * In addition to setting the staging RXON, priv->band is also set.
  573. *
  574. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  575. * in the staging RXON flag structure based on the band
  576. */
  577. static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
  578. enum ieee80211_band band,
  579. u16 channel)
  580. {
  581. if (!iwl3945_get_channel_info(priv, band, channel)) {
  582. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  583. channel, band);
  584. return -EINVAL;
  585. }
  586. if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
  587. (priv->band == band))
  588. return 0;
  589. priv->staging39_rxon.channel = cpu_to_le16(channel);
  590. if (band == IEEE80211_BAND_5GHZ)
  591. priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  592. else
  593. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  594. priv->band = band;
  595. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  596. return 0;
  597. }
  598. /**
  599. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  600. *
  601. * NOTE: This is really only useful during development and can eventually
  602. * be #ifdef'd out once the driver is stable and folks aren't actively
  603. * making changes
  604. */
  605. static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
  606. {
  607. int error = 0;
  608. int counter = 1;
  609. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  610. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  611. error |= le32_to_cpu(rxon->flags &
  612. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  613. RXON_FLG_RADAR_DETECT_MSK));
  614. if (error)
  615. IWL_WARN(priv, "check 24G fields %d | %d\n",
  616. counter++, error);
  617. } else {
  618. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  619. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  620. if (error)
  621. IWL_WARN(priv, "check 52 fields %d | %d\n",
  622. counter++, error);
  623. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  624. if (error)
  625. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  626. counter++, error);
  627. }
  628. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  629. if (error)
  630. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  631. /* make sure basic rates 6Mbps and 1Mbps are supported */
  632. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  633. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  634. if (error)
  635. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  636. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  637. if (error)
  638. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  639. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  640. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  641. if (error)
  642. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  643. counter++, error);
  644. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  645. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  646. if (error)
  647. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  648. counter++, error);
  649. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  650. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  651. if (error)
  652. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  653. counter++, error);
  654. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  655. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  656. RXON_FLG_ANT_A_MSK)) == 0);
  657. if (error)
  658. IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
  659. if (error)
  660. IWL_WARN(priv, "Tuning to channel %d\n",
  661. le16_to_cpu(rxon->channel));
  662. if (error) {
  663. IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
  664. return -1;
  665. }
  666. return 0;
  667. }
  668. /**
  669. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  670. * @priv: staging_rxon is compared to active_rxon
  671. *
  672. * If the RXON structure is changing enough to require a new tune,
  673. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  674. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  675. */
  676. static int iwl3945_full_rxon_required(struct iwl_priv *priv)
  677. {
  678. /* These items are only settable from the full RXON command */
  679. if (!(iwl3945_is_associated(priv)) ||
  680. compare_ether_addr(priv->staging39_rxon.bssid_addr,
  681. priv->active39_rxon.bssid_addr) ||
  682. compare_ether_addr(priv->staging39_rxon.node_addr,
  683. priv->active39_rxon.node_addr) ||
  684. compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
  685. priv->active39_rxon.wlap_bssid_addr) ||
  686. (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
  687. (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
  688. (priv->staging39_rxon.air_propagation !=
  689. priv->active39_rxon.air_propagation) ||
  690. (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
  691. return 1;
  692. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  693. * be updated with the RXON_ASSOC command -- however only some
  694. * flag transitions are allowed using RXON_ASSOC */
  695. /* Check if we are not switching bands */
  696. if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  697. (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
  698. return 1;
  699. /* Check if we are switching association toggle */
  700. if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  701. (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  702. return 1;
  703. return 0;
  704. }
  705. static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
  706. {
  707. int rc = 0;
  708. struct iwl_rx_packet *res = NULL;
  709. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  710. struct iwl_host_cmd cmd = {
  711. .id = REPLY_RXON_ASSOC,
  712. .len = sizeof(rxon_assoc),
  713. .meta.flags = CMD_WANT_SKB,
  714. .data = &rxon_assoc,
  715. };
  716. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
  717. const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
  718. if ((rxon1->flags == rxon2->flags) &&
  719. (rxon1->filter_flags == rxon2->filter_flags) &&
  720. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  721. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  722. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  723. return 0;
  724. }
  725. rxon_assoc.flags = priv->staging39_rxon.flags;
  726. rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
  727. rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
  728. rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
  729. rxon_assoc.reserved = 0;
  730. rc = iwl3945_send_cmd_sync(priv, &cmd);
  731. if (rc)
  732. return rc;
  733. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  734. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  735. IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
  736. rc = -EIO;
  737. }
  738. priv->alloc_rxb_skb--;
  739. dev_kfree_skb_any(cmd.meta.u.skb);
  740. return rc;
  741. }
  742. /**
  743. * iwl3945_commit_rxon - commit staging_rxon to hardware
  744. *
  745. * The RXON command in staging_rxon is committed to the hardware and
  746. * the active_rxon structure is updated with the new data. This
  747. * function correctly transitions out of the RXON_ASSOC_MSK state if
  748. * a HW tune is required based on the RXON structure changes.
  749. */
  750. static int iwl3945_commit_rxon(struct iwl_priv *priv)
  751. {
  752. /* cast away the const for active_rxon in this function */
  753. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
  754. int rc = 0;
  755. if (!iwl_is_alive(priv))
  756. return -1;
  757. /* always get timestamp with Rx frame */
  758. priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  759. /* select antenna */
  760. priv->staging39_rxon.flags &=
  761. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  762. priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
  763. rc = iwl3945_check_rxon_cmd(priv);
  764. if (rc) {
  765. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  766. return -EINVAL;
  767. }
  768. /* If we don't need to send a full RXON, we can use
  769. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  770. * and other flags for the current radio configuration. */
  771. if (!iwl3945_full_rxon_required(priv)) {
  772. rc = iwl3945_send_rxon_assoc(priv);
  773. if (rc) {
  774. IWL_ERR(priv, "Error setting RXON_ASSOC "
  775. "configuration (%d).\n", rc);
  776. return rc;
  777. }
  778. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  779. return 0;
  780. }
  781. /* If we are currently associated and the new config requires
  782. * an RXON_ASSOC and the new config wants the associated mask enabled,
  783. * we must clear the associated from the active configuration
  784. * before we apply the new config */
  785. if (iwl3945_is_associated(priv) &&
  786. (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  787. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  788. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  789. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  790. sizeof(struct iwl3945_rxon_cmd),
  791. &priv->active39_rxon);
  792. /* If the mask clearing failed then we set
  793. * active_rxon back to what it was previously */
  794. if (rc) {
  795. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  796. IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
  797. "configuration (%d).\n", rc);
  798. return rc;
  799. }
  800. }
  801. IWL_DEBUG_INFO("Sending RXON\n"
  802. "* with%s RXON_FILTER_ASSOC_MSK\n"
  803. "* channel = %d\n"
  804. "* bssid = %pM\n",
  805. ((priv->staging39_rxon.filter_flags &
  806. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  807. le16_to_cpu(priv->staging39_rxon.channel),
  808. priv->staging_rxon.bssid_addr);
  809. /* Apply the new configuration */
  810. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  811. sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
  812. if (rc) {
  813. IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
  814. return rc;
  815. }
  816. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  817. iwl3945_clear_stations_table(priv);
  818. /* If we issue a new RXON command which required a tune then we must
  819. * send a new TXPOWER command or we won't be able to Tx any frames */
  820. rc = iwl3945_hw_reg_send_txpower(priv);
  821. if (rc) {
  822. IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
  823. return rc;
  824. }
  825. /* Add the broadcast address so we can send broadcast frames */
  826. if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
  827. IWL_INVALID_STATION) {
  828. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  829. return -EIO;
  830. }
  831. /* If we have set the ASSOC_MSK and we are in BSS mode then
  832. * add the IWL_AP_ID to the station rate table */
  833. if (iwl3945_is_associated(priv) &&
  834. (priv->iw_mode == NL80211_IFTYPE_STATION))
  835. if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
  836. == IWL_INVALID_STATION) {
  837. IWL_ERR(priv, "Error adding AP address for transmit\n");
  838. return -EIO;
  839. }
  840. /* Init the hardware's rate fallback order based on the band */
  841. rc = iwl3945_init_hw_rate_table(priv);
  842. if (rc) {
  843. IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
  844. return -EIO;
  845. }
  846. return 0;
  847. }
  848. static int iwl3945_send_bt_config(struct iwl_priv *priv)
  849. {
  850. struct iwl_bt_cmd bt_cmd = {
  851. .flags = 3,
  852. .lead_time = 0xAA,
  853. .max_kill = 1,
  854. .kill_ack_mask = 0,
  855. .kill_cts_mask = 0,
  856. };
  857. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  858. sizeof(bt_cmd), &bt_cmd);
  859. }
  860. static int iwl3945_send_scan_abort(struct iwl_priv *priv)
  861. {
  862. int rc = 0;
  863. struct iwl_rx_packet *res;
  864. struct iwl_host_cmd cmd = {
  865. .id = REPLY_SCAN_ABORT_CMD,
  866. .meta.flags = CMD_WANT_SKB,
  867. };
  868. /* If there isn't a scan actively going on in the hardware
  869. * then we are in between scan bands and not actually
  870. * actively scanning, so don't send the abort command */
  871. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  872. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  873. return 0;
  874. }
  875. rc = iwl3945_send_cmd_sync(priv, &cmd);
  876. if (rc) {
  877. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  878. return rc;
  879. }
  880. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  881. if (res->u.status != CAN_ABORT_STATUS) {
  882. /* The scan abort will return 1 for success or
  883. * 2 for "failure". A failure condition can be
  884. * due to simply not being in an active scan which
  885. * can occur if we send the scan abort before we
  886. * the microcode has notified us that a scan is
  887. * completed. */
  888. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  889. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  890. clear_bit(STATUS_SCAN_HW, &priv->status);
  891. }
  892. dev_kfree_skb_any(cmd.meta.u.skb);
  893. return rc;
  894. }
  895. static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
  896. struct iwl_cmd *cmd, struct sk_buff *skb)
  897. {
  898. struct iwl_rx_packet *res = NULL;
  899. if (!skb) {
  900. IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
  901. return 1;
  902. }
  903. res = (struct iwl_rx_packet *)skb->data;
  904. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  905. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  906. res->hdr.flags);
  907. return 1;
  908. }
  909. switch (res->u.add_sta.status) {
  910. case ADD_STA_SUCCESS_MSK:
  911. break;
  912. default:
  913. break;
  914. }
  915. /* We didn't cache the SKB; let the caller free it */
  916. return 1;
  917. }
  918. int iwl3945_send_add_station(struct iwl_priv *priv,
  919. struct iwl3945_addsta_cmd *sta, u8 flags)
  920. {
  921. struct iwl_rx_packet *res = NULL;
  922. int rc = 0;
  923. struct iwl_host_cmd cmd = {
  924. .id = REPLY_ADD_STA,
  925. .len = sizeof(struct iwl3945_addsta_cmd),
  926. .meta.flags = flags,
  927. .data = sta,
  928. };
  929. if (flags & CMD_ASYNC)
  930. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  931. else
  932. cmd.meta.flags |= CMD_WANT_SKB;
  933. rc = iwl3945_send_cmd(priv, &cmd);
  934. if (rc || (flags & CMD_ASYNC))
  935. return rc;
  936. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  937. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  938. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  939. res->hdr.flags);
  940. rc = -EIO;
  941. }
  942. if (rc == 0) {
  943. switch (res->u.add_sta.status) {
  944. case ADD_STA_SUCCESS_MSK:
  945. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  946. break;
  947. default:
  948. rc = -EIO;
  949. IWL_WARN(priv, "REPLY_ADD_STA failed\n");
  950. break;
  951. }
  952. }
  953. priv->alloc_rxb_skb--;
  954. dev_kfree_skb_any(cmd.meta.u.skb);
  955. return rc;
  956. }
  957. static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
  958. struct ieee80211_key_conf *keyconf,
  959. u8 sta_id)
  960. {
  961. unsigned long flags;
  962. __le16 key_flags = 0;
  963. switch (keyconf->alg) {
  964. case ALG_CCMP:
  965. key_flags |= STA_KEY_FLG_CCMP;
  966. key_flags |= cpu_to_le16(
  967. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  968. key_flags &= ~STA_KEY_FLG_INVALID;
  969. break;
  970. case ALG_TKIP:
  971. case ALG_WEP:
  972. default:
  973. return -EINVAL;
  974. }
  975. spin_lock_irqsave(&priv->sta_lock, flags);
  976. priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
  977. priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
  978. memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
  979. keyconf->keylen);
  980. memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
  981. keyconf->keylen);
  982. priv->stations_39[sta_id].sta.key.key_flags = key_flags;
  983. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  984. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  985. spin_unlock_irqrestore(&priv->sta_lock, flags);
  986. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  987. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  988. return 0;
  989. }
  990. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  991. {
  992. unsigned long flags;
  993. spin_lock_irqsave(&priv->sta_lock, flags);
  994. memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  995. memset(&priv->stations_39[sta_id].sta.key, 0,
  996. sizeof(struct iwl4965_keyinfo));
  997. priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  998. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  999. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1000. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1001. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1002. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1003. return 0;
  1004. }
  1005. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  1006. {
  1007. struct list_head *element;
  1008. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1009. priv->frames_count);
  1010. while (!list_empty(&priv->free_frames)) {
  1011. element = priv->free_frames.next;
  1012. list_del(element);
  1013. kfree(list_entry(element, struct iwl3945_frame, list));
  1014. priv->frames_count--;
  1015. }
  1016. if (priv->frames_count) {
  1017. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  1018. priv->frames_count);
  1019. priv->frames_count = 0;
  1020. }
  1021. }
  1022. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  1023. {
  1024. struct iwl3945_frame *frame;
  1025. struct list_head *element;
  1026. if (list_empty(&priv->free_frames)) {
  1027. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1028. if (!frame) {
  1029. IWL_ERR(priv, "Could not allocate frame!\n");
  1030. return NULL;
  1031. }
  1032. priv->frames_count++;
  1033. return frame;
  1034. }
  1035. element = priv->free_frames.next;
  1036. list_del(element);
  1037. return list_entry(element, struct iwl3945_frame, list);
  1038. }
  1039. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  1040. {
  1041. memset(frame, 0, sizeof(*frame));
  1042. list_add(&frame->list, &priv->free_frames);
  1043. }
  1044. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  1045. struct ieee80211_hdr *hdr,
  1046. int left)
  1047. {
  1048. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1049. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1050. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1051. return 0;
  1052. if (priv->ibss_beacon->len > left)
  1053. return 0;
  1054. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1055. return priv->ibss_beacon->len;
  1056. }
  1057. static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
  1058. {
  1059. u8 i;
  1060. int rate_mask;
  1061. /* Set rate mask*/
  1062. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1063. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1064. else
  1065. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1066. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1067. i = iwl3945_rates[i].next_ieee) {
  1068. if (rate_mask & (1 << i))
  1069. return iwl3945_rates[i].plcp;
  1070. }
  1071. /* No valid rate was found. Assign the lowest one */
  1072. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1073. return IWL_RATE_1M_PLCP;
  1074. else
  1075. return IWL_RATE_6M_PLCP;
  1076. }
  1077. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  1078. {
  1079. struct iwl3945_frame *frame;
  1080. unsigned int frame_size;
  1081. int rc;
  1082. u8 rate;
  1083. frame = iwl3945_get_free_frame(priv);
  1084. if (!frame) {
  1085. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  1086. "command.\n");
  1087. return -ENOMEM;
  1088. }
  1089. rate = iwl3945_rate_get_lowest_plcp(priv);
  1090. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1091. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1092. &frame->u.cmd[0]);
  1093. iwl3945_free_frame(priv, frame);
  1094. return rc;
  1095. }
  1096. /******************************************************************************
  1097. *
  1098. * EEPROM related functions
  1099. *
  1100. ******************************************************************************/
  1101. static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
  1102. {
  1103. memcpy(mac, priv->eeprom39.mac_address, 6);
  1104. }
  1105. /*
  1106. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1107. * embedded controller) as EEPROM reader; each read is a series of pulses
  1108. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1109. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1110. * simply claims ownership, which should be safe when this function is called
  1111. * (i.e. before loading uCode!).
  1112. */
  1113. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
  1114. {
  1115. _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1116. return 0;
  1117. }
  1118. /**
  1119. * iwl3945_eeprom_init - read EEPROM contents
  1120. *
  1121. * Load the EEPROM contents from adapter into priv->eeprom39
  1122. *
  1123. * NOTE: This routine uses the non-debug IO access functions.
  1124. */
  1125. int iwl3945_eeprom_init(struct iwl_priv *priv)
  1126. {
  1127. u16 *e = (u16 *)&priv->eeprom39;
  1128. u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
  1129. int sz = sizeof(priv->eeprom39);
  1130. int ret;
  1131. u16 addr;
  1132. /* The EEPROM structure has several padding buffers within it
  1133. * and when adding new EEPROM maps is subject to programmer errors
  1134. * which may be very difficult to identify without explicitly
  1135. * checking the resulting size of the eeprom map. */
  1136. BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
  1137. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1138. IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1139. return -ENOENT;
  1140. }
  1141. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1142. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1143. if (ret < 0) {
  1144. IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
  1145. return -ENOENT;
  1146. }
  1147. /* eeprom is an array of 16bit values */
  1148. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1149. u32 r;
  1150. _iwl_write32(priv, CSR_EEPROM_REG,
  1151. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1152. _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1153. ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
  1154. CSR_EEPROM_REG_READ_VALID_MSK,
  1155. IWL_EEPROM_ACCESS_TIMEOUT);
  1156. if (ret < 0) {
  1157. IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
  1158. return ret;
  1159. }
  1160. r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
  1161. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1162. }
  1163. return 0;
  1164. }
  1165. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  1166. {
  1167. if (priv->shared_virt)
  1168. pci_free_consistent(priv->pci_dev,
  1169. sizeof(struct iwl3945_shared),
  1170. priv->shared_virt,
  1171. priv->shared_phys);
  1172. }
  1173. /**
  1174. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1175. *
  1176. * return : set the bit for each supported rate insert in ie
  1177. */
  1178. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1179. u16 basic_rate, int *left)
  1180. {
  1181. u16 ret_rates = 0, bit;
  1182. int i;
  1183. u8 *cnt = ie;
  1184. u8 *rates = ie + 1;
  1185. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1186. if (bit & supported_rate) {
  1187. ret_rates |= bit;
  1188. rates[*cnt] = iwl3945_rates[i].ieee |
  1189. ((bit & basic_rate) ? 0x80 : 0x00);
  1190. (*cnt)++;
  1191. (*left)--;
  1192. if ((*left <= 0) ||
  1193. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1194. break;
  1195. }
  1196. }
  1197. return ret_rates;
  1198. }
  1199. /**
  1200. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1201. */
  1202. static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
  1203. struct ieee80211_mgmt *frame,
  1204. int left)
  1205. {
  1206. int len = 0;
  1207. u8 *pos = NULL;
  1208. u16 active_rates, ret_rates, cck_rates;
  1209. /* Make sure there is enough space for the probe request,
  1210. * two mandatory IEs and the data */
  1211. left -= 24;
  1212. if (left < 0)
  1213. return 0;
  1214. len += 24;
  1215. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1216. memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
  1217. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1218. memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
  1219. frame->seq_ctrl = 0;
  1220. /* fill in our indirect SSID IE */
  1221. /* ...next IE... */
  1222. left -= 2;
  1223. if (left < 0)
  1224. return 0;
  1225. len += 2;
  1226. pos = &(frame->u.probe_req.variable[0]);
  1227. *pos++ = WLAN_EID_SSID;
  1228. *pos++ = 0;
  1229. /* fill in supported rate */
  1230. /* ...next IE... */
  1231. left -= 2;
  1232. if (left < 0)
  1233. return 0;
  1234. /* ... fill it in... */
  1235. *pos++ = WLAN_EID_SUPP_RATES;
  1236. *pos = 0;
  1237. priv->active_rate = priv->rates_mask;
  1238. active_rates = priv->active_rate;
  1239. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1240. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1241. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1242. priv->active_rate_basic, &left);
  1243. active_rates &= ~ret_rates;
  1244. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1245. priv->active_rate_basic, &left);
  1246. active_rates &= ~ret_rates;
  1247. len += 2 + *pos;
  1248. pos += (*pos) + 1;
  1249. if (active_rates == 0)
  1250. goto fill_end;
  1251. /* fill in supported extended rate */
  1252. /* ...next IE... */
  1253. left -= 2;
  1254. if (left < 0)
  1255. return 0;
  1256. /* ... fill it in... */
  1257. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1258. *pos = 0;
  1259. iwl3945_supported_rate_to_ie(pos, active_rates,
  1260. priv->active_rate_basic, &left);
  1261. if (*pos > 0)
  1262. len += 2 + *pos;
  1263. fill_end:
  1264. return (u16)len;
  1265. }
  1266. /*
  1267. * QoS support
  1268. */
  1269. static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
  1270. struct iwl_qosparam_cmd *qos)
  1271. {
  1272. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1273. sizeof(struct iwl_qosparam_cmd), qos);
  1274. }
  1275. static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
  1276. {
  1277. unsigned long flags;
  1278. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1279. return;
  1280. spin_lock_irqsave(&priv->lock, flags);
  1281. priv->qos_data.def_qos_parm.qos_flags = 0;
  1282. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1283. !priv->qos_data.qos_cap.q_AP.txop_request)
  1284. priv->qos_data.def_qos_parm.qos_flags |=
  1285. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1286. if (priv->qos_data.qos_active)
  1287. priv->qos_data.def_qos_parm.qos_flags |=
  1288. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1289. spin_unlock_irqrestore(&priv->lock, flags);
  1290. if (force || iwl3945_is_associated(priv)) {
  1291. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1292. priv->qos_data.qos_active);
  1293. iwl3945_send_qos_params_command(priv,
  1294. &(priv->qos_data.def_qos_parm));
  1295. }
  1296. }
  1297. /*
  1298. * Power management (not Tx power!) functions
  1299. */
  1300. #define MSEC_TO_USEC 1024
  1301. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1302. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1303. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1304. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1305. __constant_cpu_to_le32(X1), \
  1306. __constant_cpu_to_le32(X2), \
  1307. __constant_cpu_to_le32(X3), \
  1308. __constant_cpu_to_le32(X4)}
  1309. /* default power management (not Tx power) table values */
  1310. /* for TIM 0-10 */
  1311. static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
  1312. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1313. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1314. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1315. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1316. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1317. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1318. };
  1319. /* for TIM > 10 */
  1320. static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
  1321. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1322. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1323. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1324. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1325. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1326. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1327. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1328. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1329. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1330. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1331. };
  1332. int iwl3945_power_init_handle(struct iwl_priv *priv)
  1333. {
  1334. int rc = 0, i;
  1335. struct iwl3945_power_mgr *pow_data;
  1336. int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
  1337. u16 pci_pm;
  1338. IWL_DEBUG_POWER("Initialize power \n");
  1339. pow_data = &(priv->power_data_39);
  1340. memset(pow_data, 0, sizeof(*pow_data));
  1341. pow_data->active_index = IWL_POWER_RANGE_0;
  1342. pow_data->dtim_val = 0xffff;
  1343. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1344. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1345. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1346. if (rc != 0)
  1347. return 0;
  1348. else {
  1349. struct iwl_powertable_cmd *cmd;
  1350. IWL_DEBUG_POWER("adjust power command flags\n");
  1351. for (i = 0; i < IWL39_POWER_AC; i++) {
  1352. cmd = &pow_data->pwr_range_0[i].cmd;
  1353. if (pci_pm & 0x1)
  1354. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1355. else
  1356. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1357. }
  1358. }
  1359. return rc;
  1360. }
  1361. static int iwl3945_update_power_cmd(struct iwl_priv *priv,
  1362. struct iwl_powertable_cmd *cmd, u32 mode)
  1363. {
  1364. int rc = 0, i;
  1365. u8 skip;
  1366. u32 max_sleep = 0;
  1367. struct iwl_power_vec_entry *range;
  1368. u8 period = 0;
  1369. struct iwl3945_power_mgr *pow_data;
  1370. if (mode > IWL_POWER_INDEX_5) {
  1371. IWL_DEBUG_POWER("Error invalid power mode \n");
  1372. return -1;
  1373. }
  1374. pow_data = &(priv->power_data_39);
  1375. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1376. range = &pow_data->pwr_range_0[0];
  1377. else
  1378. range = &pow_data->pwr_range_1[1];
  1379. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1380. #ifdef IWL_MAC80211_DISABLE
  1381. if (priv->assoc_network != NULL) {
  1382. unsigned long flags;
  1383. period = priv->assoc_network->tim.tim_period;
  1384. }
  1385. #endif /*IWL_MAC80211_DISABLE */
  1386. skip = range[mode].no_dtim;
  1387. if (period == 0) {
  1388. period = 1;
  1389. skip = 0;
  1390. }
  1391. if (skip == 0) {
  1392. max_sleep = period;
  1393. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1394. } else {
  1395. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1396. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1397. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1398. }
  1399. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1400. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1401. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1402. }
  1403. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1404. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1405. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1406. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1407. le32_to_cpu(cmd->sleep_interval[0]),
  1408. le32_to_cpu(cmd->sleep_interval[1]),
  1409. le32_to_cpu(cmd->sleep_interval[2]),
  1410. le32_to_cpu(cmd->sleep_interval[3]),
  1411. le32_to_cpu(cmd->sleep_interval[4]));
  1412. return rc;
  1413. }
  1414. static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
  1415. {
  1416. u32 uninitialized_var(final_mode);
  1417. int rc;
  1418. struct iwl_powertable_cmd cmd;
  1419. /* If on battery, set to 3,
  1420. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1421. * else user level */
  1422. switch (mode) {
  1423. case IWL39_POWER_BATTERY:
  1424. final_mode = IWL_POWER_INDEX_3;
  1425. break;
  1426. case IWL39_POWER_AC:
  1427. final_mode = IWL_POWER_MODE_CAM;
  1428. break;
  1429. default:
  1430. final_mode = mode;
  1431. break;
  1432. }
  1433. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1434. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1435. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1436. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1437. if (final_mode == IWL_POWER_MODE_CAM)
  1438. clear_bit(STATUS_POWER_PMI, &priv->status);
  1439. else
  1440. set_bit(STATUS_POWER_PMI, &priv->status);
  1441. return rc;
  1442. }
  1443. /**
  1444. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1445. *
  1446. * NOTE: priv->mutex is not required before calling this function
  1447. */
  1448. static int iwl3945_scan_cancel(struct iwl_priv *priv)
  1449. {
  1450. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1451. clear_bit(STATUS_SCANNING, &priv->status);
  1452. return 0;
  1453. }
  1454. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1455. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1456. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1457. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1458. queue_work(priv->workqueue, &priv->abort_scan);
  1459. } else
  1460. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1461. return test_bit(STATUS_SCANNING, &priv->status);
  1462. }
  1463. return 0;
  1464. }
  1465. /**
  1466. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1467. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1468. *
  1469. * NOTE: priv->mutex must be held before calling this function
  1470. */
  1471. static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
  1472. {
  1473. unsigned long now = jiffies;
  1474. int ret;
  1475. ret = iwl3945_scan_cancel(priv);
  1476. if (ret && ms) {
  1477. mutex_unlock(&priv->mutex);
  1478. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1479. test_bit(STATUS_SCANNING, &priv->status))
  1480. msleep(1);
  1481. mutex_lock(&priv->mutex);
  1482. return test_bit(STATUS_SCANNING, &priv->status);
  1483. }
  1484. return ret;
  1485. }
  1486. #define MAX_UCODE_BEACON_INTERVAL 1024
  1487. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1488. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1489. {
  1490. u16 new_val = 0;
  1491. u16 beacon_factor = 0;
  1492. beacon_factor =
  1493. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1494. / MAX_UCODE_BEACON_INTERVAL;
  1495. new_val = beacon_val / beacon_factor;
  1496. return cpu_to_le16(new_val);
  1497. }
  1498. static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
  1499. {
  1500. u64 interval_tm_unit;
  1501. u64 tsf, result;
  1502. unsigned long flags;
  1503. struct ieee80211_conf *conf = NULL;
  1504. u16 beacon_int = 0;
  1505. conf = ieee80211_get_hw_conf(priv->hw);
  1506. spin_lock_irqsave(&priv->lock, flags);
  1507. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1508. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1509. tsf = priv->timestamp;
  1510. beacon_int = priv->beacon_int;
  1511. spin_unlock_irqrestore(&priv->lock, flags);
  1512. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1513. if (beacon_int == 0) {
  1514. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1515. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1516. } else {
  1517. priv->rxon_timing.beacon_interval =
  1518. cpu_to_le16(beacon_int);
  1519. priv->rxon_timing.beacon_interval =
  1520. iwl3945_adjust_beacon_interval(
  1521. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1522. }
  1523. priv->rxon_timing.atim_window = 0;
  1524. } else {
  1525. priv->rxon_timing.beacon_interval =
  1526. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1527. /* TODO: we need to get atim_window from upper stack
  1528. * for now we set to 0 */
  1529. priv->rxon_timing.atim_window = 0;
  1530. }
  1531. interval_tm_unit =
  1532. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1533. result = do_div(tsf, interval_tm_unit);
  1534. priv->rxon_timing.beacon_init_val =
  1535. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1536. IWL_DEBUG_ASSOC
  1537. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1538. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1539. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1540. le16_to_cpu(priv->rxon_timing.atim_window));
  1541. }
  1542. static int iwl3945_scan_initiate(struct iwl_priv *priv)
  1543. {
  1544. if (!iwl_is_ready_rf(priv)) {
  1545. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1546. return -EIO;
  1547. }
  1548. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1549. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1550. return -EAGAIN;
  1551. }
  1552. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1553. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1554. "Queuing.\n");
  1555. return -EAGAIN;
  1556. }
  1557. IWL_DEBUG_INFO("Starting scan...\n");
  1558. if (priv->cfg->sku & IWL_SKU_G)
  1559. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1560. if (priv->cfg->sku & IWL_SKU_A)
  1561. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1562. set_bit(STATUS_SCANNING, &priv->status);
  1563. priv->scan_start = jiffies;
  1564. priv->scan_pass_start = priv->scan_start;
  1565. queue_work(priv->workqueue, &priv->request_scan);
  1566. return 0;
  1567. }
  1568. static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  1569. {
  1570. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  1571. if (hw_decrypt)
  1572. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1573. else
  1574. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1575. return 0;
  1576. }
  1577. static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
  1578. enum ieee80211_band band)
  1579. {
  1580. if (band == IEEE80211_BAND_5GHZ) {
  1581. priv->staging39_rxon.flags &=
  1582. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1583. | RXON_FLG_CCK_MSK);
  1584. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1585. } else {
  1586. /* Copied from iwl3945_bg_post_associate() */
  1587. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1588. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1589. else
  1590. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1591. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1592. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1593. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1594. priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1595. priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1596. }
  1597. }
  1598. /*
  1599. * initialize rxon structure with default values from eeprom
  1600. */
  1601. static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
  1602. int mode)
  1603. {
  1604. const struct iwl_channel_info *ch_info;
  1605. memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
  1606. switch (mode) {
  1607. case NL80211_IFTYPE_AP:
  1608. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
  1609. break;
  1610. case NL80211_IFTYPE_STATION:
  1611. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1612. priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1613. break;
  1614. case NL80211_IFTYPE_ADHOC:
  1615. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1616. priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1617. priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1618. RXON_FILTER_ACCEPT_GRP_MSK;
  1619. break;
  1620. case NL80211_IFTYPE_MONITOR:
  1621. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1622. priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1623. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1624. break;
  1625. default:
  1626. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1627. break;
  1628. }
  1629. #if 0
  1630. /* TODO: Figure out when short_preamble would be set and cache from
  1631. * that */
  1632. if (!hw_to_local(priv->hw)->short_preamble)
  1633. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1634. else
  1635. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1636. #endif
  1637. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1638. le16_to_cpu(priv->active39_rxon.channel));
  1639. if (!ch_info)
  1640. ch_info = &priv->channel_info[0];
  1641. /*
  1642. * in some case A channels are all non IBSS
  1643. * in this case force B/G channel
  1644. */
  1645. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1646. ch_info = &priv->channel_info[0];
  1647. priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
  1648. if (is_channel_a_band(ch_info))
  1649. priv->band = IEEE80211_BAND_5GHZ;
  1650. else
  1651. priv->band = IEEE80211_BAND_2GHZ;
  1652. iwl3945_set_flags_for_phymode(priv, priv->band);
  1653. priv->staging39_rxon.ofdm_basic_rates =
  1654. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1655. priv->staging39_rxon.cck_basic_rates =
  1656. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1657. }
  1658. static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
  1659. {
  1660. if (mode == NL80211_IFTYPE_ADHOC) {
  1661. const struct iwl_channel_info *ch_info;
  1662. ch_info = iwl3945_get_channel_info(priv,
  1663. priv->band,
  1664. le16_to_cpu(priv->staging39_rxon.channel));
  1665. if (!ch_info || !is_channel_ibss(ch_info)) {
  1666. IWL_ERR(priv, "channel %d not IBSS channel\n",
  1667. le16_to_cpu(priv->staging39_rxon.channel));
  1668. return -EINVAL;
  1669. }
  1670. }
  1671. iwl3945_connection_init_rx_config(priv, mode);
  1672. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1673. iwl3945_clear_stations_table(priv);
  1674. /* don't commit rxon if rf-kill is on*/
  1675. if (!iwl_is_ready_rf(priv))
  1676. return -EAGAIN;
  1677. cancel_delayed_work(&priv->scan_check);
  1678. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1679. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1680. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1681. return -EAGAIN;
  1682. }
  1683. iwl3945_commit_rxon(priv);
  1684. return 0;
  1685. }
  1686. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  1687. struct ieee80211_tx_info *info,
  1688. struct iwl_cmd *cmd,
  1689. struct sk_buff *skb_frag,
  1690. int last_frag)
  1691. {
  1692. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1693. struct iwl3945_hw_key *keyinfo =
  1694. &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
  1695. switch (keyinfo->alg) {
  1696. case ALG_CCMP:
  1697. tx->sec_ctl = TX_CMD_SEC_CCM;
  1698. memcpy(tx->key, keyinfo->key, keyinfo->keylen);
  1699. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1700. break;
  1701. case ALG_TKIP:
  1702. #if 0
  1703. tx->sec_ctl = TX_CMD_SEC_TKIP;
  1704. if (last_frag)
  1705. memcpy(tx->tkip_mic.byte, skb_frag->tail - 8,
  1706. 8);
  1707. else
  1708. memset(tx->tkip_mic.byte, 0, 8);
  1709. #endif
  1710. break;
  1711. case ALG_WEP:
  1712. tx->sec_ctl = TX_CMD_SEC_WEP |
  1713. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1714. if (keyinfo->keylen == 13)
  1715. tx->sec_ctl |= TX_CMD_SEC_KEY128;
  1716. memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
  1717. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1718. "with key %d\n", info->control.hw_key->hw_key_idx);
  1719. break;
  1720. default:
  1721. IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
  1722. break;
  1723. }
  1724. }
  1725. /*
  1726. * handle build REPLY_TX command notification.
  1727. */
  1728. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  1729. struct iwl_cmd *cmd,
  1730. struct ieee80211_tx_info *info,
  1731. struct ieee80211_hdr *hdr, u8 std_id)
  1732. {
  1733. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1734. __le32 tx_flags = tx->tx_flags;
  1735. __le16 fc = hdr->frame_control;
  1736. u8 rc_flags = info->control.rates[0].flags;
  1737. tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1738. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1739. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1740. if (ieee80211_is_mgmt(fc))
  1741. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1742. if (ieee80211_is_probe_resp(fc) &&
  1743. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1744. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1745. } else {
  1746. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1747. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1748. }
  1749. tx->sta_id = std_id;
  1750. if (ieee80211_has_morefrags(fc))
  1751. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1752. if (ieee80211_is_data_qos(fc)) {
  1753. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1754. tx->tid_tspec = qc[0] & 0xf;
  1755. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1756. } else {
  1757. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1758. }
  1759. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1760. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1761. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1762. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1763. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1764. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1765. }
  1766. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1767. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1768. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1769. if (ieee80211_is_mgmt(fc)) {
  1770. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1771. tx->timeout.pm_frame_timeout = cpu_to_le16(3);
  1772. else
  1773. tx->timeout.pm_frame_timeout = cpu_to_le16(2);
  1774. } else {
  1775. tx->timeout.pm_frame_timeout = 0;
  1776. #ifdef CONFIG_IWL3945_LEDS
  1777. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1778. #endif
  1779. }
  1780. tx->driver_txop = 0;
  1781. tx->tx_flags = tx_flags;
  1782. tx->next_frame_len = 0;
  1783. }
  1784. /**
  1785. * iwl3945_get_sta_id - Find station's index within station table
  1786. */
  1787. static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
  1788. {
  1789. int sta_id;
  1790. u16 fc = le16_to_cpu(hdr->frame_control);
  1791. /* If this frame is broadcast or management, use broadcast station id */
  1792. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1793. is_multicast_ether_addr(hdr->addr1))
  1794. return priv->hw_params.bcast_sta_id;
  1795. switch (priv->iw_mode) {
  1796. /* If we are a client station in a BSS network, use the special
  1797. * AP station entry (that's the only station we communicate with) */
  1798. case NL80211_IFTYPE_STATION:
  1799. return IWL_AP_ID;
  1800. /* If we are an AP, then find the station, or use BCAST */
  1801. case NL80211_IFTYPE_AP:
  1802. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1803. if (sta_id != IWL_INVALID_STATION)
  1804. return sta_id;
  1805. return priv->hw_params.bcast_sta_id;
  1806. /* If this frame is going out to an IBSS network, find the station,
  1807. * or create a new station table entry */
  1808. case NL80211_IFTYPE_ADHOC: {
  1809. /* Create new station table entry */
  1810. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1811. if (sta_id != IWL_INVALID_STATION)
  1812. return sta_id;
  1813. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1814. if (sta_id != IWL_INVALID_STATION)
  1815. return sta_id;
  1816. IWL_DEBUG_DROP("Station %pM not in station map. "
  1817. "Defaulting to broadcast...\n",
  1818. hdr->addr1);
  1819. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1820. return priv->hw_params.bcast_sta_id;
  1821. }
  1822. /* If we are in monitor mode, use BCAST. This is required for
  1823. * packet injection. */
  1824. case NL80211_IFTYPE_MONITOR:
  1825. return priv->hw_params.bcast_sta_id;
  1826. default:
  1827. IWL_WARN(priv, "Unknown mode of operation: %d\n",
  1828. priv->iw_mode);
  1829. return priv->hw_params.bcast_sta_id;
  1830. }
  1831. }
  1832. /*
  1833. * start REPLY_TX command process
  1834. */
  1835. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  1836. {
  1837. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1838. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1839. struct iwl3945_tfd *tfd;
  1840. struct iwl3945_tx_cmd *tx;
  1841. struct iwl_tx_queue *txq = NULL;
  1842. struct iwl_queue *q = NULL;
  1843. struct iwl_cmd *out_cmd = NULL;
  1844. dma_addr_t phys_addr;
  1845. dma_addr_t txcmd_phys;
  1846. int txq_id = skb_get_queue_mapping(skb);
  1847. u16 len, idx, len_org, hdr_len;
  1848. u8 id;
  1849. u8 unicast;
  1850. u8 sta_id;
  1851. u8 tid = 0;
  1852. u16 seq_number = 0;
  1853. __le16 fc;
  1854. u8 wait_write_ptr = 0;
  1855. u8 *qc = NULL;
  1856. unsigned long flags;
  1857. int rc;
  1858. spin_lock_irqsave(&priv->lock, flags);
  1859. if (iwl_is_rfkill(priv)) {
  1860. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  1861. goto drop_unlock;
  1862. }
  1863. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  1864. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  1865. goto drop_unlock;
  1866. }
  1867. unicast = !is_multicast_ether_addr(hdr->addr1);
  1868. id = 0;
  1869. fc = hdr->frame_control;
  1870. #ifdef CONFIG_IWL3945_DEBUG
  1871. if (ieee80211_is_auth(fc))
  1872. IWL_DEBUG_TX("Sending AUTH frame\n");
  1873. else if (ieee80211_is_assoc_req(fc))
  1874. IWL_DEBUG_TX("Sending ASSOC frame\n");
  1875. else if (ieee80211_is_reassoc_req(fc))
  1876. IWL_DEBUG_TX("Sending REASSOC frame\n");
  1877. #endif
  1878. /* drop all data frame if we are not associated */
  1879. if (ieee80211_is_data(fc) &&
  1880. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  1881. (!iwl3945_is_associated(priv) ||
  1882. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  1883. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  1884. goto drop_unlock;
  1885. }
  1886. spin_unlock_irqrestore(&priv->lock, flags);
  1887. hdr_len = ieee80211_hdrlen(fc);
  1888. /* Find (or create) index into station table for destination station */
  1889. sta_id = iwl3945_get_sta_id(priv, hdr);
  1890. if (sta_id == IWL_INVALID_STATION) {
  1891. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  1892. hdr->addr1);
  1893. goto drop;
  1894. }
  1895. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  1896. if (ieee80211_is_data_qos(fc)) {
  1897. qc = ieee80211_get_qos_ctl(hdr);
  1898. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  1899. seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
  1900. IEEE80211_SCTL_SEQ;
  1901. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  1902. (hdr->seq_ctrl &
  1903. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  1904. seq_number += 0x10;
  1905. }
  1906. /* Descriptor for chosen Tx queue */
  1907. txq = &priv->txq[txq_id];
  1908. q = &txq->q;
  1909. spin_lock_irqsave(&priv->lock, flags);
  1910. /* Set up first empty TFD within this queue's circular TFD buffer */
  1911. tfd = &txq->tfds39[q->write_ptr];
  1912. memset(tfd, 0, sizeof(*tfd));
  1913. idx = get_cmd_index(q, q->write_ptr, 0);
  1914. /* Set up driver data for this TFD */
  1915. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  1916. txq->txb[q->write_ptr].skb[0] = skb;
  1917. /* Init first empty entry in queue's array of Tx/cmd buffers */
  1918. out_cmd = txq->cmd[idx];
  1919. tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  1920. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  1921. memset(tx, 0, sizeof(*tx));
  1922. /*
  1923. * Set up the Tx-command (not MAC!) header.
  1924. * Store the chosen Tx queue and TFD index within the sequence field;
  1925. * after Tx, uCode's Tx response will return this value so driver can
  1926. * locate the frame within the tx queue and do post-tx processing.
  1927. */
  1928. out_cmd->hdr.cmd = REPLY_TX;
  1929. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  1930. INDEX_TO_SEQ(q->write_ptr)));
  1931. /* Copy MAC header from skb into command buffer */
  1932. memcpy(tx->hdr, hdr, hdr_len);
  1933. /*
  1934. * Use the first empty entry in this queue's command buffer array
  1935. * to contain the Tx command and MAC header concatenated together
  1936. * (payload data will be in another buffer).
  1937. * Size of this varies, due to varying MAC header length.
  1938. * If end is not dword aligned, we'll have 2 extra bytes at the end
  1939. * of the MAC header (device reads on dword boundaries).
  1940. * We'll tell device about this padding later.
  1941. */
  1942. len = sizeof(struct iwl3945_tx_cmd) +
  1943. sizeof(struct iwl_cmd_header) + hdr_len;
  1944. len_org = len;
  1945. len = (len + 3) & ~3;
  1946. if (len_org != len)
  1947. len_org = 1;
  1948. else
  1949. len_org = 0;
  1950. /* Physical address of this Tx command's header (not MAC header!),
  1951. * within command buffer array. */
  1952. txcmd_phys = pci_map_single(priv->pci_dev,
  1953. out_cmd, sizeof(struct iwl_cmd),
  1954. PCI_DMA_TODEVICE);
  1955. pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
  1956. pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
  1957. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1958. * first entry */
  1959. txcmd_phys += offsetof(struct iwl_cmd, hdr);
  1960. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1961. * first entry */
  1962. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  1963. if (info->control.hw_key)
  1964. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  1965. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  1966. * if any (802.11 null frames have no payload). */
  1967. len = skb->len - hdr_len;
  1968. if (len) {
  1969. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  1970. len, PCI_DMA_TODEVICE);
  1971. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  1972. }
  1973. if (!len)
  1974. /* If there is no payload, then we use only one Tx buffer */
  1975. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(1));
  1976. else
  1977. /* Else use 2 buffers.
  1978. * Tell 3945 about any padding after MAC header */
  1979. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(2) |
  1980. TFD_CTL_PAD_SET(U32_PAD(len)));
  1981. /* Total # bytes to be transmitted */
  1982. len = (u16)skb->len;
  1983. tx->len = cpu_to_le16(len);
  1984. /* TODO need this for burst mode later on */
  1985. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  1986. /* set is_hcca to 0; it probably will never be implemented */
  1987. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  1988. tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  1989. tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  1990. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  1991. txq->need_update = 1;
  1992. if (qc)
  1993. priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
  1994. } else {
  1995. wait_write_ptr = 1;
  1996. txq->need_update = 0;
  1997. }
  1998. iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
  1999. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
  2000. ieee80211_hdrlen(fc));
  2001. /* Tell device the write index *just past* this latest filled TFD */
  2002. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2003. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2004. spin_unlock_irqrestore(&priv->lock, flags);
  2005. if (rc)
  2006. return rc;
  2007. if ((iwl_queue_space(q) < q->high_mark)
  2008. && priv->mac80211_registered) {
  2009. if (wait_write_ptr) {
  2010. spin_lock_irqsave(&priv->lock, flags);
  2011. txq->need_update = 1;
  2012. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2013. spin_unlock_irqrestore(&priv->lock, flags);
  2014. }
  2015. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2016. }
  2017. return 0;
  2018. drop_unlock:
  2019. spin_unlock_irqrestore(&priv->lock, flags);
  2020. drop:
  2021. return -1;
  2022. }
  2023. static void iwl3945_set_rate(struct iwl_priv *priv)
  2024. {
  2025. const struct ieee80211_supported_band *sband = NULL;
  2026. struct ieee80211_rate *rate;
  2027. int i;
  2028. sband = iwl_get_hw_mode(priv, priv->band);
  2029. if (!sband) {
  2030. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  2031. return;
  2032. }
  2033. priv->active_rate = 0;
  2034. priv->active_rate_basic = 0;
  2035. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2036. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2037. for (i = 0; i < sband->n_bitrates; i++) {
  2038. rate = &sband->bitrates[i];
  2039. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2040. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2041. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2042. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2043. priv->active_rate |= (1 << rate->hw_value);
  2044. }
  2045. }
  2046. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2047. priv->active_rate, priv->active_rate_basic);
  2048. /*
  2049. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2050. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2051. * OFDM
  2052. */
  2053. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2054. priv->staging39_rxon.cck_basic_rates =
  2055. ((priv->active_rate_basic &
  2056. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2057. else
  2058. priv->staging39_rxon.cck_basic_rates =
  2059. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2060. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2061. priv->staging39_rxon.ofdm_basic_rates =
  2062. ((priv->active_rate_basic &
  2063. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2064. IWL_FIRST_OFDM_RATE) & 0xFF;
  2065. else
  2066. priv->staging39_rxon.ofdm_basic_rates =
  2067. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2068. }
  2069. static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
  2070. {
  2071. unsigned long flags;
  2072. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2073. return;
  2074. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2075. disable_radio ? "OFF" : "ON");
  2076. if (disable_radio) {
  2077. iwl3945_scan_cancel(priv);
  2078. /* FIXME: This is a workaround for AP */
  2079. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2080. spin_lock_irqsave(&priv->lock, flags);
  2081. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2082. CSR_UCODE_SW_BIT_RFKILL);
  2083. spin_unlock_irqrestore(&priv->lock, flags);
  2084. iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2085. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2086. }
  2087. return;
  2088. }
  2089. spin_lock_irqsave(&priv->lock, flags);
  2090. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2091. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2092. spin_unlock_irqrestore(&priv->lock, flags);
  2093. /* wake up ucode */
  2094. msleep(10);
  2095. spin_lock_irqsave(&priv->lock, flags);
  2096. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2097. if (!iwl_grab_nic_access(priv))
  2098. iwl_release_nic_access(priv);
  2099. spin_unlock_irqrestore(&priv->lock, flags);
  2100. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2101. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2102. "disabled by HW switch\n");
  2103. return;
  2104. }
  2105. if (priv->is_open)
  2106. queue_work(priv->workqueue, &priv->restart);
  2107. return;
  2108. }
  2109. void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
  2110. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2111. {
  2112. u16 fc =
  2113. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2114. if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2115. return;
  2116. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2117. return;
  2118. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2119. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2120. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2121. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2122. RX_RES_STATUS_BAD_ICV_MIC)
  2123. stats->flag |= RX_FLAG_MMIC_ERROR;
  2124. case RX_RES_STATUS_SEC_TYPE_WEP:
  2125. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2126. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2127. RX_RES_STATUS_DECRYPT_OK) {
  2128. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2129. stats->flag |= RX_FLAG_DECRYPTED;
  2130. }
  2131. break;
  2132. default:
  2133. break;
  2134. }
  2135. }
  2136. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2137. #include "iwl-spectrum.h"
  2138. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2139. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2140. #define TIME_UNIT 1024
  2141. /*
  2142. * extended beacon time format
  2143. * time in usec will be changed into a 32-bit value in 8:24 format
  2144. * the high 1 byte is the beacon counts
  2145. * the lower 3 bytes is the time in usec within one beacon interval
  2146. */
  2147. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2148. {
  2149. u32 quot;
  2150. u32 rem;
  2151. u32 interval = beacon_interval * 1024;
  2152. if (!interval || !usec)
  2153. return 0;
  2154. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2155. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2156. return (quot << 24) + rem;
  2157. }
  2158. /* base is usually what we get from ucode with each received frame,
  2159. * the same as HW timer counter counting down
  2160. */
  2161. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2162. {
  2163. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2164. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2165. u32 interval = beacon_interval * TIME_UNIT;
  2166. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2167. (addon & BEACON_TIME_MASK_HIGH);
  2168. if (base_low > addon_low)
  2169. res += base_low - addon_low;
  2170. else if (base_low < addon_low) {
  2171. res += interval + base_low - addon_low;
  2172. res += (1 << 24);
  2173. } else
  2174. res += (1 << 24);
  2175. return cpu_to_le32(res);
  2176. }
  2177. static int iwl3945_get_measurement(struct iwl_priv *priv,
  2178. struct ieee80211_measurement_params *params,
  2179. u8 type)
  2180. {
  2181. struct iwl_spectrum_cmd spectrum;
  2182. struct iwl_rx_packet *res;
  2183. struct iwl_host_cmd cmd = {
  2184. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2185. .data = (void *)&spectrum,
  2186. .meta.flags = CMD_WANT_SKB,
  2187. };
  2188. u32 add_time = le64_to_cpu(params->start_time);
  2189. int rc;
  2190. int spectrum_resp_status;
  2191. int duration = le16_to_cpu(params->duration);
  2192. if (iwl3945_is_associated(priv))
  2193. add_time =
  2194. iwl3945_usecs_to_beacons(
  2195. le64_to_cpu(params->start_time) - priv->last_tsf,
  2196. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2197. memset(&spectrum, 0, sizeof(spectrum));
  2198. spectrum.channel_count = cpu_to_le16(1);
  2199. spectrum.flags =
  2200. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2201. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2202. cmd.len = sizeof(spectrum);
  2203. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2204. if (iwl3945_is_associated(priv))
  2205. spectrum.start_time =
  2206. iwl3945_add_beacon_time(priv->last_beacon_time,
  2207. add_time,
  2208. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2209. else
  2210. spectrum.start_time = 0;
  2211. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2212. spectrum.channels[0].channel = params->channel;
  2213. spectrum.channels[0].type = type;
  2214. if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2215. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2216. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2217. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2218. if (rc)
  2219. return rc;
  2220. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2221. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2222. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  2223. rc = -EIO;
  2224. }
  2225. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2226. switch (spectrum_resp_status) {
  2227. case 0: /* Command will be handled */
  2228. if (res->u.spectrum.id != 0xff) {
  2229. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2230. res->u.spectrum.id);
  2231. priv->measurement_status &= ~MEASUREMENT_READY;
  2232. }
  2233. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2234. rc = 0;
  2235. break;
  2236. case 1: /* Command will not be handled */
  2237. rc = -EAGAIN;
  2238. break;
  2239. }
  2240. dev_kfree_skb_any(cmd.meta.u.skb);
  2241. return rc;
  2242. }
  2243. #endif
  2244. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  2245. struct iwl_rx_mem_buffer *rxb)
  2246. {
  2247. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2248. struct iwl_alive_resp *palive;
  2249. struct delayed_work *pwork;
  2250. palive = &pkt->u.alive_frame;
  2251. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2252. "0x%01X 0x%01X\n",
  2253. palive->is_valid, palive->ver_type,
  2254. palive->ver_subtype);
  2255. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2256. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2257. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2258. sizeof(struct iwl_alive_resp));
  2259. pwork = &priv->init_alive_start;
  2260. } else {
  2261. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2262. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2263. sizeof(struct iwl_alive_resp));
  2264. pwork = &priv->alive_start;
  2265. iwl3945_disable_events(priv);
  2266. }
  2267. /* We delay the ALIVE response by 5ms to
  2268. * give the HW RF Kill time to activate... */
  2269. if (palive->is_valid == UCODE_VALID_OK)
  2270. queue_delayed_work(priv->workqueue, pwork,
  2271. msecs_to_jiffies(5));
  2272. else
  2273. IWL_WARN(priv, "uCode did not respond OK.\n");
  2274. }
  2275. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  2276. struct iwl_rx_mem_buffer *rxb)
  2277. {
  2278. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2279. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2280. return;
  2281. }
  2282. static void iwl3945_rx_reply_error(struct iwl_priv *priv,
  2283. struct iwl_rx_mem_buffer *rxb)
  2284. {
  2285. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2286. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  2287. "seq 0x%04X ser 0x%08X\n",
  2288. le32_to_cpu(pkt->u.err_resp.error_type),
  2289. get_cmd_string(pkt->u.err_resp.cmd_id),
  2290. pkt->u.err_resp.cmd_id,
  2291. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2292. le32_to_cpu(pkt->u.err_resp.error_info));
  2293. }
  2294. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2295. static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2296. {
  2297. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2298. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
  2299. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2300. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2301. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2302. rxon->channel = csa->channel;
  2303. priv->staging39_rxon.channel = csa->channel;
  2304. }
  2305. static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
  2306. struct iwl_rx_mem_buffer *rxb)
  2307. {
  2308. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2309. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2310. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2311. if (!report->state) {
  2312. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2313. "Spectrum Measure Notification: Start\n");
  2314. return;
  2315. }
  2316. memcpy(&priv->measure_report, report, sizeof(*report));
  2317. priv->measurement_status |= MEASUREMENT_READY;
  2318. #endif
  2319. }
  2320. static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
  2321. struct iwl_rx_mem_buffer *rxb)
  2322. {
  2323. #ifdef CONFIG_IWL3945_DEBUG
  2324. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2325. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2326. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2327. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2328. #endif
  2329. }
  2330. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  2331. struct iwl_rx_mem_buffer *rxb)
  2332. {
  2333. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2334. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2335. "notification for %s:\n",
  2336. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2337. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2338. le32_to_cpu(pkt->len));
  2339. }
  2340. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2341. {
  2342. struct iwl_priv *priv =
  2343. container_of(work, struct iwl_priv, beacon_update);
  2344. struct sk_buff *beacon;
  2345. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2346. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2347. if (!beacon) {
  2348. IWL_ERR(priv, "update beacon failed\n");
  2349. return;
  2350. }
  2351. mutex_lock(&priv->mutex);
  2352. /* new beacon skb is allocated every time; dispose previous.*/
  2353. if (priv->ibss_beacon)
  2354. dev_kfree_skb(priv->ibss_beacon);
  2355. priv->ibss_beacon = beacon;
  2356. mutex_unlock(&priv->mutex);
  2357. iwl3945_send_beacon_cmd(priv);
  2358. }
  2359. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  2360. struct iwl_rx_mem_buffer *rxb)
  2361. {
  2362. #ifdef CONFIG_IWL3945_DEBUG
  2363. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2364. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2365. u8 rate = beacon->beacon_notify_hdr.rate;
  2366. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2367. "tsf %d %d rate %d\n",
  2368. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2369. beacon->beacon_notify_hdr.failure_frame,
  2370. le32_to_cpu(beacon->ibss_mgr_status),
  2371. le32_to_cpu(beacon->high_tsf),
  2372. le32_to_cpu(beacon->low_tsf), rate);
  2373. #endif
  2374. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2375. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2376. queue_work(priv->workqueue, &priv->beacon_update);
  2377. }
  2378. /* Service response to REPLY_SCAN_CMD (0x80) */
  2379. static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
  2380. struct iwl_rx_mem_buffer *rxb)
  2381. {
  2382. #ifdef CONFIG_IWL3945_DEBUG
  2383. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2384. struct iwl_scanreq_notification *notif =
  2385. (struct iwl_scanreq_notification *)pkt->u.raw;
  2386. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2387. #endif
  2388. }
  2389. /* Service SCAN_START_NOTIFICATION (0x82) */
  2390. static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
  2391. struct iwl_rx_mem_buffer *rxb)
  2392. {
  2393. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2394. struct iwl_scanstart_notification *notif =
  2395. (struct iwl_scanstart_notification *)pkt->u.raw;
  2396. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2397. IWL_DEBUG_SCAN("Scan start: "
  2398. "%d [802.11%s] "
  2399. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2400. notif->channel,
  2401. notif->band ? "bg" : "a",
  2402. notif->tsf_high,
  2403. notif->tsf_low, notif->status, notif->beacon_timer);
  2404. }
  2405. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2406. static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
  2407. struct iwl_rx_mem_buffer *rxb)
  2408. {
  2409. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2410. struct iwl_scanresults_notification *notif =
  2411. (struct iwl_scanresults_notification *)pkt->u.raw;
  2412. IWL_DEBUG_SCAN("Scan ch.res: "
  2413. "%d [802.11%s] "
  2414. "(TSF: 0x%08X:%08X) - %d "
  2415. "elapsed=%lu usec (%dms since last)\n",
  2416. notif->channel,
  2417. notif->band ? "bg" : "a",
  2418. le32_to_cpu(notif->tsf_high),
  2419. le32_to_cpu(notif->tsf_low),
  2420. le32_to_cpu(notif->statistics[0]),
  2421. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2422. jiffies_to_msecs(elapsed_jiffies
  2423. (priv->last_scan_jiffies, jiffies)));
  2424. priv->last_scan_jiffies = jiffies;
  2425. priv->next_scan_jiffies = 0;
  2426. }
  2427. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2428. static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
  2429. struct iwl_rx_mem_buffer *rxb)
  2430. {
  2431. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2432. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2433. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2434. scan_notif->scanned_channels,
  2435. scan_notif->tsf_low,
  2436. scan_notif->tsf_high, scan_notif->status);
  2437. /* The HW is no longer scanning */
  2438. clear_bit(STATUS_SCAN_HW, &priv->status);
  2439. /* The scan completion notification came in, so kill that timer... */
  2440. cancel_delayed_work(&priv->scan_check);
  2441. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2442. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2443. "2.4" : "5.2",
  2444. jiffies_to_msecs(elapsed_jiffies
  2445. (priv->scan_pass_start, jiffies)));
  2446. /* Remove this scanned band from the list of pending
  2447. * bands to scan, band G precedes A in order of scanning
  2448. * as seen in iwl3945_bg_request_scan */
  2449. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2450. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2451. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2452. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2453. /* If a request to abort was given, or the scan did not succeed
  2454. * then we reset the scan state machine and terminate,
  2455. * re-queuing another scan if one has been requested */
  2456. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2457. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2458. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2459. } else {
  2460. /* If there are more bands on this scan pass reschedule */
  2461. if (priv->scan_bands > 0)
  2462. goto reschedule;
  2463. }
  2464. priv->last_scan_jiffies = jiffies;
  2465. priv->next_scan_jiffies = 0;
  2466. IWL_DEBUG_INFO("Setting scan to off\n");
  2467. clear_bit(STATUS_SCANNING, &priv->status);
  2468. IWL_DEBUG_INFO("Scan took %dms\n",
  2469. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2470. queue_work(priv->workqueue, &priv->scan_completed);
  2471. return;
  2472. reschedule:
  2473. priv->scan_pass_start = jiffies;
  2474. queue_work(priv->workqueue, &priv->request_scan);
  2475. }
  2476. /* Handle notification from uCode that card's power state is changing
  2477. * due to software, hardware, or critical temperature RFKILL */
  2478. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  2479. struct iwl_rx_mem_buffer *rxb)
  2480. {
  2481. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2482. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2483. unsigned long status = priv->status;
  2484. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2485. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2486. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2487. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2488. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2489. if (flags & HW_CARD_DISABLED)
  2490. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2491. else
  2492. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2493. if (flags & SW_CARD_DISABLED)
  2494. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2495. else
  2496. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2497. iwl3945_scan_cancel(priv);
  2498. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2499. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2500. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2501. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2502. queue_work(priv->workqueue, &priv->rf_kill);
  2503. else
  2504. wake_up_interruptible(&priv->wait_command_queue);
  2505. }
  2506. /**
  2507. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2508. *
  2509. * Setup the RX handlers for each of the reply types sent from the uCode
  2510. * to the host.
  2511. *
  2512. * This function chains into the hardware specific files for them to setup
  2513. * any hardware specific handlers as well.
  2514. */
  2515. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  2516. {
  2517. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2518. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2519. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2520. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2521. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2522. iwl3945_rx_spectrum_measure_notif;
  2523. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2524. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2525. iwl3945_rx_pm_debug_statistics_notif;
  2526. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2527. /*
  2528. * The same handler is used for both the REPLY to a discrete
  2529. * statistics request from the host as well as for the periodic
  2530. * statistics notifications (after received beacons) from the uCode.
  2531. */
  2532. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2533. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2534. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2535. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2536. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2537. iwl3945_rx_scan_results_notif;
  2538. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2539. iwl3945_rx_scan_complete_notif;
  2540. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2541. /* Set up hardware specific Rx handlers */
  2542. iwl3945_hw_rx_handler_setup(priv);
  2543. }
  2544. /**
  2545. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2546. * When FW advances 'R' index, all entries between old and new 'R' index
  2547. * need to be reclaimed.
  2548. */
  2549. static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
  2550. int txq_id, int index)
  2551. {
  2552. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  2553. struct iwl_queue *q = &txq->q;
  2554. int nfreed = 0;
  2555. if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
  2556. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  2557. "is out of range [0-%d] %d %d.\n", txq_id,
  2558. index, q->n_bd, q->write_ptr, q->read_ptr);
  2559. return;
  2560. }
  2561. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2562. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2563. if (nfreed > 1) {
  2564. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
  2565. q->write_ptr, q->read_ptr);
  2566. queue_work(priv->workqueue, &priv->restart);
  2567. break;
  2568. }
  2569. nfreed++;
  2570. }
  2571. }
  2572. /**
  2573. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2574. * @rxb: Rx buffer to reclaim
  2575. *
  2576. * If an Rx buffer has an async callback associated with it the callback
  2577. * will be executed. The attached skb (if present) will only be freed
  2578. * if the callback returns 1
  2579. */
  2580. static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
  2581. struct iwl_rx_mem_buffer *rxb)
  2582. {
  2583. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2584. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2585. int txq_id = SEQ_TO_QUEUE(sequence);
  2586. int index = SEQ_TO_INDEX(sequence);
  2587. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2588. int cmd_index;
  2589. struct iwl_cmd *cmd;
  2590. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2591. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2592. cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2593. /* Input error checking is done when commands are added to queue. */
  2594. if (cmd->meta.flags & CMD_WANT_SKB) {
  2595. cmd->meta.source->u.skb = rxb->skb;
  2596. rxb->skb = NULL;
  2597. } else if (cmd->meta.u.callback &&
  2598. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2599. rxb->skb = NULL;
  2600. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2601. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2602. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2603. wake_up_interruptible(&priv->wait_command_queue);
  2604. }
  2605. }
  2606. /************************** RX-FUNCTIONS ****************************/
  2607. /*
  2608. * Rx theory of operation
  2609. *
  2610. * The host allocates 32 DMA target addresses and passes the host address
  2611. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2612. * 0 to 31
  2613. *
  2614. * Rx Queue Indexes
  2615. * The host/firmware share two index registers for managing the Rx buffers.
  2616. *
  2617. * The READ index maps to the first position that the firmware may be writing
  2618. * to -- the driver can read up to (but not including) this position and get
  2619. * good data.
  2620. * The READ index is managed by the firmware once the card is enabled.
  2621. *
  2622. * The WRITE index maps to the last position the driver has read from -- the
  2623. * position preceding WRITE is the last slot the firmware can place a packet.
  2624. *
  2625. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2626. * WRITE = READ.
  2627. *
  2628. * During initialization, the host sets up the READ queue position to the first
  2629. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2630. *
  2631. * When the firmware places a packet in a buffer, it will advance the READ index
  2632. * and fire the RX interrupt. The driver can then query the READ index and
  2633. * process as many packets as possible, moving the WRITE index forward as it
  2634. * resets the Rx queue buffers with new memory.
  2635. *
  2636. * The management in the driver is as follows:
  2637. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2638. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2639. * to replenish the iwl->rxq->rx_free.
  2640. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2641. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2642. * 'processed' and 'read' driver indexes as well)
  2643. * + A received packet is processed and handed to the kernel network stack,
  2644. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2645. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2646. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2647. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2648. * were enough free buffers and RX_STALLED is set it is cleared.
  2649. *
  2650. *
  2651. * Driver sequence:
  2652. *
  2653. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2654. * iwl3945_rx_queue_restock
  2655. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2656. * queue, updates firmware pointers, and updates
  2657. * the WRITE index. If insufficient rx_free buffers
  2658. * are available, schedules iwl3945_rx_replenish
  2659. *
  2660. * -- enable interrupts --
  2661. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  2662. * READ INDEX, detaching the SKB from the pool.
  2663. * Moves the packet buffer from queue to rx_used.
  2664. * Calls iwl3945_rx_queue_restock to refill any empty
  2665. * slots.
  2666. * ...
  2667. *
  2668. */
  2669. /**
  2670. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2671. */
  2672. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  2673. dma_addr_t dma_addr)
  2674. {
  2675. return cpu_to_le32((u32)dma_addr);
  2676. }
  2677. /**
  2678. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2679. *
  2680. * If there are slots in the RX queue that need to be restocked,
  2681. * and we have free pre-allocated buffers, fill the ranks as much
  2682. * as we can, pulling from rx_free.
  2683. *
  2684. * This moves the 'write' index forward to catch up with 'processed', and
  2685. * also updates the memory address in the firmware to reference the new
  2686. * target buffer.
  2687. */
  2688. static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
  2689. {
  2690. struct iwl_rx_queue *rxq = &priv->rxq;
  2691. struct list_head *element;
  2692. struct iwl_rx_mem_buffer *rxb;
  2693. unsigned long flags;
  2694. int write, rc;
  2695. spin_lock_irqsave(&rxq->lock, flags);
  2696. write = rxq->write & ~0x7;
  2697. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2698. /* Get next free Rx buffer, remove from free list */
  2699. element = rxq->rx_free.next;
  2700. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2701. list_del(element);
  2702. /* Point to Rx buffer via next RBD in circular buffer */
  2703. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
  2704. rxq->queue[rxq->write] = rxb;
  2705. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2706. rxq->free_count--;
  2707. }
  2708. spin_unlock_irqrestore(&rxq->lock, flags);
  2709. /* If the pre-allocated buffer pool is dropping low, schedule to
  2710. * refill it */
  2711. if (rxq->free_count <= RX_LOW_WATERMARK)
  2712. queue_work(priv->workqueue, &priv->rx_replenish);
  2713. /* If we've added more space for the firmware to place data, tell it.
  2714. * Increment device's write pointer in multiples of 8. */
  2715. if ((write != (rxq->write & ~0x7))
  2716. || (abs(rxq->write - rxq->read) > 7)) {
  2717. spin_lock_irqsave(&rxq->lock, flags);
  2718. rxq->need_update = 1;
  2719. spin_unlock_irqrestore(&rxq->lock, flags);
  2720. rc = iwl_rx_queue_update_write_ptr(priv, rxq);
  2721. if (rc)
  2722. return rc;
  2723. }
  2724. return 0;
  2725. }
  2726. /**
  2727. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2728. *
  2729. * When moving to rx_free an SKB is allocated for the slot.
  2730. *
  2731. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2732. * This is called as a scheduled work item (except for during initialization)
  2733. */
  2734. static void iwl3945_rx_allocate(struct iwl_priv *priv)
  2735. {
  2736. struct iwl_rx_queue *rxq = &priv->rxq;
  2737. struct list_head *element;
  2738. struct iwl_rx_mem_buffer *rxb;
  2739. unsigned long flags;
  2740. spin_lock_irqsave(&rxq->lock, flags);
  2741. while (!list_empty(&rxq->rx_used)) {
  2742. element = rxq->rx_used.next;
  2743. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2744. /* Alloc a new receive buffer */
  2745. rxb->skb =
  2746. alloc_skb(priv->hw_params.rx_buf_size,
  2747. __GFP_NOWARN | GFP_ATOMIC);
  2748. if (!rxb->skb) {
  2749. if (net_ratelimit())
  2750. IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
  2751. /* We don't reschedule replenish work here -- we will
  2752. * call the restock method and if it still needs
  2753. * more buffers it will schedule replenish */
  2754. break;
  2755. }
  2756. /* If radiotap head is required, reserve some headroom here.
  2757. * The physical head count is a variable rx_stats->phy_count.
  2758. * We reserve 4 bytes here. Plus these extra bytes, the
  2759. * headroom of the physical head should be enough for the
  2760. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2761. */
  2762. skb_reserve(rxb->skb, 4);
  2763. priv->alloc_rxb_skb++;
  2764. list_del(element);
  2765. /* Get physical address of RB/SKB */
  2766. rxb->real_dma_addr = pci_map_single(priv->pci_dev,
  2767. rxb->skb->data,
  2768. priv->hw_params.rx_buf_size,
  2769. PCI_DMA_FROMDEVICE);
  2770. list_add_tail(&rxb->list, &rxq->rx_free);
  2771. rxq->free_count++;
  2772. }
  2773. spin_unlock_irqrestore(&rxq->lock, flags);
  2774. }
  2775. /*
  2776. * this should be called while priv->lock is locked
  2777. */
  2778. static void __iwl3945_rx_replenish(void *data)
  2779. {
  2780. struct iwl_priv *priv = data;
  2781. iwl3945_rx_allocate(priv);
  2782. iwl3945_rx_queue_restock(priv);
  2783. }
  2784. void iwl3945_rx_replenish(void *data)
  2785. {
  2786. struct iwl_priv *priv = data;
  2787. unsigned long flags;
  2788. iwl3945_rx_allocate(priv);
  2789. spin_lock_irqsave(&priv->lock, flags);
  2790. iwl3945_rx_queue_restock(priv);
  2791. spin_unlock_irqrestore(&priv->lock, flags);
  2792. }
  2793. /* Convert linear signal-to-noise ratio into dB */
  2794. static u8 ratio2dB[100] = {
  2795. /* 0 1 2 3 4 5 6 7 8 9 */
  2796. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  2797. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  2798. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  2799. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  2800. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  2801. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  2802. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  2803. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  2804. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  2805. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  2806. };
  2807. /* Calculates a relative dB value from a ratio of linear
  2808. * (i.e. not dB) signal levels.
  2809. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  2810. int iwl3945_calc_db_from_ratio(int sig_ratio)
  2811. {
  2812. /* 1000:1 or higher just report as 60 dB */
  2813. if (sig_ratio >= 1000)
  2814. return 60;
  2815. /* 100:1 or higher, divide by 10 and use table,
  2816. * add 20 dB to make up for divide by 10 */
  2817. if (sig_ratio >= 100)
  2818. return 20 + (int)ratio2dB[sig_ratio/10];
  2819. /* We shouldn't see this */
  2820. if (sig_ratio < 1)
  2821. return 0;
  2822. /* Use table for ratios 1:1 - 99:1 */
  2823. return (int)ratio2dB[sig_ratio];
  2824. }
  2825. #define PERFECT_RSSI (-20) /* dBm */
  2826. #define WORST_RSSI (-95) /* dBm */
  2827. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  2828. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  2829. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  2830. * about formulas used below. */
  2831. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  2832. {
  2833. int sig_qual;
  2834. int degradation = PERFECT_RSSI - rssi_dbm;
  2835. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  2836. * as indicator; formula is (signal dbm - noise dbm).
  2837. * SNR at or above 40 is a great signal (100%).
  2838. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  2839. * Weakest usable signal is usually 10 - 15 dB SNR. */
  2840. if (noise_dbm) {
  2841. if (rssi_dbm - noise_dbm >= 40)
  2842. return 100;
  2843. else if (rssi_dbm < noise_dbm)
  2844. return 0;
  2845. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  2846. /* Else use just the signal level.
  2847. * This formula is a least squares fit of data points collected and
  2848. * compared with a reference system that had a percentage (%) display
  2849. * for signal quality. */
  2850. } else
  2851. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  2852. (15 * RSSI_RANGE + 62 * degradation)) /
  2853. (RSSI_RANGE * RSSI_RANGE);
  2854. if (sig_qual > 100)
  2855. sig_qual = 100;
  2856. else if (sig_qual < 1)
  2857. sig_qual = 0;
  2858. return sig_qual;
  2859. }
  2860. /**
  2861. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  2862. *
  2863. * Uses the priv->rx_handlers callback function array to invoke
  2864. * the appropriate handlers, including command responses,
  2865. * frame-received notifications, and other notifications.
  2866. */
  2867. static void iwl3945_rx_handle(struct iwl_priv *priv)
  2868. {
  2869. struct iwl_rx_mem_buffer *rxb;
  2870. struct iwl_rx_packet *pkt;
  2871. struct iwl_rx_queue *rxq = &priv->rxq;
  2872. u32 r, i;
  2873. int reclaim;
  2874. unsigned long flags;
  2875. u8 fill_rx = 0;
  2876. u32 count = 8;
  2877. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  2878. * buffer that the driver may process (last buffer filled by ucode). */
  2879. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  2880. i = rxq->read;
  2881. if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  2882. fill_rx = 1;
  2883. /* Rx interrupt, but nothing sent from uCode */
  2884. if (i == r)
  2885. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  2886. while (i != r) {
  2887. rxb = rxq->queue[i];
  2888. /* If an RXB doesn't have a Rx queue slot associated with it,
  2889. * then a bug has been introduced in the queue refilling
  2890. * routines -- catch it here */
  2891. BUG_ON(rxb == NULL);
  2892. rxq->queue[i] = NULL;
  2893. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
  2894. priv->hw_params.rx_buf_size,
  2895. PCI_DMA_FROMDEVICE);
  2896. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2897. /* Reclaim a command buffer only if this packet is a response
  2898. * to a (driver-originated) command.
  2899. * If the packet (e.g. Rx frame) originated from uCode,
  2900. * there is no command buffer to reclaim.
  2901. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  2902. * but apparently a few don't get set; catch them here. */
  2903. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  2904. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  2905. (pkt->hdr.cmd != REPLY_TX);
  2906. /* Based on type of command response or notification,
  2907. * handle those that need handling via function in
  2908. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  2909. if (priv->rx_handlers[pkt->hdr.cmd]) {
  2910. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  2911. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  2912. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  2913. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  2914. } else {
  2915. /* No handling needed */
  2916. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  2917. "r %d i %d No handler needed for %s, 0x%02x\n",
  2918. r, i, get_cmd_string(pkt->hdr.cmd),
  2919. pkt->hdr.cmd);
  2920. }
  2921. if (reclaim) {
  2922. /* Invoke any callbacks, transfer the skb to caller, and
  2923. * fire off the (possibly) blocking iwl3945_send_cmd()
  2924. * as we reclaim the driver command queue */
  2925. if (rxb && rxb->skb)
  2926. iwl3945_tx_cmd_complete(priv, rxb);
  2927. else
  2928. IWL_WARN(priv, "Claim null rxb?\n");
  2929. }
  2930. /* For now we just don't re-use anything. We can tweak this
  2931. * later to try and re-use notification packets and SKBs that
  2932. * fail to Rx correctly */
  2933. if (rxb->skb != NULL) {
  2934. priv->alloc_rxb_skb--;
  2935. dev_kfree_skb_any(rxb->skb);
  2936. rxb->skb = NULL;
  2937. }
  2938. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  2939. priv->hw_params.rx_buf_size,
  2940. PCI_DMA_FROMDEVICE);
  2941. spin_lock_irqsave(&rxq->lock, flags);
  2942. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  2943. spin_unlock_irqrestore(&rxq->lock, flags);
  2944. i = (i + 1) & RX_QUEUE_MASK;
  2945. /* If there are a lot of unused frames,
  2946. * restock the Rx queue so ucode won't assert. */
  2947. if (fill_rx) {
  2948. count++;
  2949. if (count >= 8) {
  2950. priv->rxq.read = i;
  2951. __iwl3945_rx_replenish(priv);
  2952. count = 0;
  2953. }
  2954. }
  2955. }
  2956. /* Backtrack one entry */
  2957. priv->rxq.read = i;
  2958. iwl3945_rx_queue_restock(priv);
  2959. }
  2960. /**
  2961. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  2962. */
  2963. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  2964. struct iwl_tx_queue *txq)
  2965. {
  2966. u32 reg = 0;
  2967. int rc = 0;
  2968. int txq_id = txq->q.id;
  2969. if (txq->need_update == 0)
  2970. return rc;
  2971. /* if we're trying to save power */
  2972. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2973. /* wake up nic if it's powered down ...
  2974. * uCode will wake up, and interrupt us again, so next
  2975. * time we'll skip this part. */
  2976. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2977. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2978. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  2979. iwl_set_bit(priv, CSR_GP_CNTRL,
  2980. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2981. return rc;
  2982. }
  2983. /* restore this queue's parameters in nic hardware. */
  2984. rc = iwl_grab_nic_access(priv);
  2985. if (rc)
  2986. return rc;
  2987. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  2988. txq->q.write_ptr | (txq_id << 8));
  2989. iwl_release_nic_access(priv);
  2990. /* else not in power-save mode, uCode will never sleep when we're
  2991. * trying to tx (during RFKILL, we're not trying to tx). */
  2992. } else
  2993. iwl_write32(priv, HBUS_TARG_WRPTR,
  2994. txq->q.write_ptr | (txq_id << 8));
  2995. txq->need_update = 0;
  2996. return rc;
  2997. }
  2998. #ifdef CONFIG_IWL3945_DEBUG
  2999. static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
  3000. struct iwl3945_rxon_cmd *rxon)
  3001. {
  3002. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3003. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3004. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3005. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3006. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3007. le32_to_cpu(rxon->filter_flags));
  3008. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3009. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3010. rxon->ofdm_basic_rates);
  3011. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3012. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3013. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3014. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3015. }
  3016. #endif
  3017. static void iwl3945_enable_interrupts(struct iwl_priv *priv)
  3018. {
  3019. IWL_DEBUG_ISR("Enabling interrupts\n");
  3020. set_bit(STATUS_INT_ENABLED, &priv->status);
  3021. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3022. }
  3023. /* call this function to flush any scheduled tasklet */
  3024. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  3025. {
  3026. /* wait to make sure we flush pending tasklet*/
  3027. synchronize_irq(priv->pci_dev->irq);
  3028. tasklet_kill(&priv->irq_tasklet);
  3029. }
  3030. static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
  3031. {
  3032. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3033. /* disable interrupts from uCode/NIC to host */
  3034. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3035. /* acknowledge/clear/reset any interrupts still pending
  3036. * from uCode or flow handler (Rx/Tx DMA) */
  3037. iwl_write32(priv, CSR_INT, 0xffffffff);
  3038. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3039. IWL_DEBUG_ISR("Disabled interrupts\n");
  3040. }
  3041. static const char *desc_lookup(int i)
  3042. {
  3043. switch (i) {
  3044. case 1:
  3045. return "FAIL";
  3046. case 2:
  3047. return "BAD_PARAM";
  3048. case 3:
  3049. return "BAD_CHECKSUM";
  3050. case 4:
  3051. return "NMI_INTERRUPT";
  3052. case 5:
  3053. return "SYSASSERT";
  3054. case 6:
  3055. return "FATAL_ERROR";
  3056. }
  3057. return "UNKNOWN";
  3058. }
  3059. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3060. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3061. static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  3062. {
  3063. u32 i;
  3064. u32 desc, time, count, base, data1;
  3065. u32 blink1, blink2, ilink1, ilink2;
  3066. int rc;
  3067. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3068. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3069. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  3070. return;
  3071. }
  3072. rc = iwl_grab_nic_access(priv);
  3073. if (rc) {
  3074. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3075. return;
  3076. }
  3077. count = iwl_read_targ_mem(priv, base);
  3078. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3079. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  3080. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  3081. priv->status, count);
  3082. }
  3083. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  3084. "ilink1 nmiPC Line\n");
  3085. for (i = ERROR_START_OFFSET;
  3086. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3087. i += ERROR_ELEM_SIZE) {
  3088. desc = iwl_read_targ_mem(priv, base + i);
  3089. time =
  3090. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3091. blink1 =
  3092. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3093. blink2 =
  3094. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3095. ilink1 =
  3096. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3097. ilink2 =
  3098. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3099. data1 =
  3100. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3101. IWL_ERR(priv,
  3102. "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3103. desc_lookup(desc), desc, time, blink1, blink2,
  3104. ilink1, ilink2, data1);
  3105. }
  3106. iwl_release_nic_access(priv);
  3107. }
  3108. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3109. /**
  3110. * iwl3945_print_event_log - Dump error event log to syslog
  3111. *
  3112. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  3113. */
  3114. static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  3115. u32 num_events, u32 mode)
  3116. {
  3117. u32 i;
  3118. u32 base; /* SRAM byte address of event log header */
  3119. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3120. u32 ptr; /* SRAM byte address of log data */
  3121. u32 ev, time, data; /* event log data */
  3122. if (num_events == 0)
  3123. return;
  3124. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3125. if (mode == 0)
  3126. event_size = 2 * sizeof(u32);
  3127. else
  3128. event_size = 3 * sizeof(u32);
  3129. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3130. /* "time" is actually "data" for mode 0 (no timestamp).
  3131. * place event id # at far right for easier visual parsing. */
  3132. for (i = 0; i < num_events; i++) {
  3133. ev = iwl_read_targ_mem(priv, ptr);
  3134. ptr += sizeof(u32);
  3135. time = iwl_read_targ_mem(priv, ptr);
  3136. ptr += sizeof(u32);
  3137. if (mode == 0) {
  3138. /* data, ev */
  3139. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  3140. } else {
  3141. data = iwl_read_targ_mem(priv, ptr);
  3142. ptr += sizeof(u32);
  3143. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
  3144. }
  3145. }
  3146. }
  3147. static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
  3148. {
  3149. int rc;
  3150. u32 base; /* SRAM byte address of event log header */
  3151. u32 capacity; /* event log capacity in # entries */
  3152. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3153. u32 num_wraps; /* # times uCode wrapped to top of log */
  3154. u32 next_entry; /* index of next entry to be written by uCode */
  3155. u32 size; /* # entries that we'll print */
  3156. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3157. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3158. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  3159. return;
  3160. }
  3161. rc = iwl_grab_nic_access(priv);
  3162. if (rc) {
  3163. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3164. return;
  3165. }
  3166. /* event log header */
  3167. capacity = iwl_read_targ_mem(priv, base);
  3168. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3169. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3170. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3171. size = num_wraps ? capacity : next_entry;
  3172. /* bail out if nothing in log */
  3173. if (size == 0) {
  3174. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  3175. iwl_release_nic_access(priv);
  3176. return;
  3177. }
  3178. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  3179. size, num_wraps);
  3180. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3181. * i.e the next one that uCode would fill. */
  3182. if (num_wraps)
  3183. iwl3945_print_event_log(priv, next_entry,
  3184. capacity - next_entry, mode);
  3185. /* (then/else) start at top of log */
  3186. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3187. iwl_release_nic_access(priv);
  3188. }
  3189. /**
  3190. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3191. */
  3192. static void iwl3945_irq_handle_error(struct iwl_priv *priv)
  3193. {
  3194. /* Set the FW error flag -- cleared on iwl3945_down */
  3195. set_bit(STATUS_FW_ERROR, &priv->status);
  3196. /* Cancel currently queued command. */
  3197. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3198. #ifdef CONFIG_IWL3945_DEBUG
  3199. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3200. iwl3945_dump_nic_error_log(priv);
  3201. iwl3945_dump_nic_event_log(priv);
  3202. iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
  3203. }
  3204. #endif
  3205. wake_up_interruptible(&priv->wait_command_queue);
  3206. /* Keep the restart process from trying to send host
  3207. * commands by clearing the INIT status bit */
  3208. clear_bit(STATUS_READY, &priv->status);
  3209. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3210. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3211. "Restarting adapter due to uCode error.\n");
  3212. if (iwl3945_is_associated(priv)) {
  3213. memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
  3214. sizeof(priv->recovery39_rxon));
  3215. priv->error_recovering = 1;
  3216. }
  3217. queue_work(priv->workqueue, &priv->restart);
  3218. }
  3219. }
  3220. static void iwl3945_error_recovery(struct iwl_priv *priv)
  3221. {
  3222. unsigned long flags;
  3223. memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
  3224. sizeof(priv->staging39_rxon));
  3225. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3226. iwl3945_commit_rxon(priv);
  3227. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3228. spin_lock_irqsave(&priv->lock, flags);
  3229. priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
  3230. priv->error_recovering = 0;
  3231. spin_unlock_irqrestore(&priv->lock, flags);
  3232. }
  3233. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  3234. {
  3235. u32 inta, handled = 0;
  3236. u32 inta_fh;
  3237. unsigned long flags;
  3238. #ifdef CONFIG_IWL3945_DEBUG
  3239. u32 inta_mask;
  3240. #endif
  3241. spin_lock_irqsave(&priv->lock, flags);
  3242. /* Ack/clear/reset pending uCode interrupts.
  3243. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3244. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3245. inta = iwl_read32(priv, CSR_INT);
  3246. iwl_write32(priv, CSR_INT, inta);
  3247. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3248. * Any new interrupts that happen after this, either while we're
  3249. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3250. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3251. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3252. #ifdef CONFIG_IWL3945_DEBUG
  3253. if (priv->debug_level & IWL_DL_ISR) {
  3254. /* just for debug */
  3255. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3256. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3257. inta, inta_mask, inta_fh);
  3258. }
  3259. #endif
  3260. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3261. * atomic, make sure that inta covers all the interrupts that
  3262. * we've discovered, even if FH interrupt came in just after
  3263. * reading CSR_INT. */
  3264. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3265. inta |= CSR_INT_BIT_FH_RX;
  3266. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3267. inta |= CSR_INT_BIT_FH_TX;
  3268. /* Now service all interrupt bits discovered above. */
  3269. if (inta & CSR_INT_BIT_HW_ERR) {
  3270. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  3271. /* Tell the device to stop sending interrupts */
  3272. iwl3945_disable_interrupts(priv);
  3273. iwl3945_irq_handle_error(priv);
  3274. handled |= CSR_INT_BIT_HW_ERR;
  3275. spin_unlock_irqrestore(&priv->lock, flags);
  3276. return;
  3277. }
  3278. #ifdef CONFIG_IWL3945_DEBUG
  3279. if (priv->debug_level & (IWL_DL_ISR)) {
  3280. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3281. if (inta & CSR_INT_BIT_SCD)
  3282. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3283. "the frame/frames.\n");
  3284. /* Alive notification via Rx interrupt will do the real work */
  3285. if (inta & CSR_INT_BIT_ALIVE)
  3286. IWL_DEBUG_ISR("Alive interrupt\n");
  3287. }
  3288. #endif
  3289. /* Safely ignore these bits for debug checks below */
  3290. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3291. /* Error detected by uCode */
  3292. if (inta & CSR_INT_BIT_SW_ERR) {
  3293. IWL_ERR(priv, "Microcode SW error detected. "
  3294. "Restarting 0x%X.\n", inta);
  3295. iwl3945_irq_handle_error(priv);
  3296. handled |= CSR_INT_BIT_SW_ERR;
  3297. }
  3298. /* uCode wakes up after power-down sleep */
  3299. if (inta & CSR_INT_BIT_WAKEUP) {
  3300. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3301. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  3302. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3303. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3304. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3305. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3306. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3307. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3308. handled |= CSR_INT_BIT_WAKEUP;
  3309. }
  3310. /* All uCode command responses, including Tx command responses,
  3311. * Rx "responses" (frame-received notification), and other
  3312. * notifications from uCode come through here*/
  3313. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3314. iwl3945_rx_handle(priv);
  3315. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3316. }
  3317. if (inta & CSR_INT_BIT_FH_TX) {
  3318. IWL_DEBUG_ISR("Tx interrupt\n");
  3319. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3320. if (!iwl_grab_nic_access(priv)) {
  3321. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  3322. (FH39_SRVC_CHNL), 0x0);
  3323. iwl_release_nic_access(priv);
  3324. }
  3325. handled |= CSR_INT_BIT_FH_TX;
  3326. }
  3327. if (inta & ~handled)
  3328. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3329. if (inta & ~CSR_INI_SET_MASK) {
  3330. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  3331. inta & ~CSR_INI_SET_MASK);
  3332. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  3333. }
  3334. /* Re-enable all interrupts */
  3335. /* only Re-enable if disabled by irq */
  3336. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3337. iwl3945_enable_interrupts(priv);
  3338. #ifdef CONFIG_IWL3945_DEBUG
  3339. if (priv->debug_level & (IWL_DL_ISR)) {
  3340. inta = iwl_read32(priv, CSR_INT);
  3341. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3342. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3343. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3344. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3345. }
  3346. #endif
  3347. spin_unlock_irqrestore(&priv->lock, flags);
  3348. }
  3349. static irqreturn_t iwl3945_isr(int irq, void *data)
  3350. {
  3351. struct iwl_priv *priv = data;
  3352. u32 inta, inta_mask;
  3353. u32 inta_fh;
  3354. if (!priv)
  3355. return IRQ_NONE;
  3356. spin_lock(&priv->lock);
  3357. /* Disable (but don't clear!) interrupts here to avoid
  3358. * back-to-back ISRs and sporadic interrupts from our NIC.
  3359. * If we have something to service, the tasklet will re-enable ints.
  3360. * If we *don't* have something, we'll re-enable before leaving here. */
  3361. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  3362. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3363. /* Discover which interrupts are active/pending */
  3364. inta = iwl_read32(priv, CSR_INT);
  3365. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3366. /* Ignore interrupt if there's nothing in NIC to service.
  3367. * This may be due to IRQ shared with another device,
  3368. * or due to sporadic interrupts thrown from our NIC. */
  3369. if (!inta && !inta_fh) {
  3370. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3371. goto none;
  3372. }
  3373. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3374. /* Hardware disappeared */
  3375. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3376. goto unplugged;
  3377. }
  3378. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3379. inta, inta_mask, inta_fh);
  3380. inta &= ~CSR_INT_BIT_SCD;
  3381. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3382. if (likely(inta || inta_fh))
  3383. tasklet_schedule(&priv->irq_tasklet);
  3384. unplugged:
  3385. spin_unlock(&priv->lock);
  3386. return IRQ_HANDLED;
  3387. none:
  3388. /* re-enable interrupts here since we don't have anything to service. */
  3389. /* only Re-enable if disabled by irq */
  3390. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3391. iwl3945_enable_interrupts(priv);
  3392. spin_unlock(&priv->lock);
  3393. return IRQ_NONE;
  3394. }
  3395. /************************** EEPROM BANDS ****************************
  3396. *
  3397. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3398. * EEPROM contents to the specific channel number supported for each
  3399. * band.
  3400. *
  3401. * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
  3402. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3403. * The specific geography and calibration information for that channel
  3404. * is contained in the eeprom map itself.
  3405. *
  3406. * During init, we copy the eeprom information and channel map
  3407. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3408. *
  3409. * channel_map_24/52 provides the index in the channel_info array for a
  3410. * given channel. We have to have two separate maps as there is channel
  3411. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3412. * band_2
  3413. *
  3414. * A value of 0xff stored in the channel_map indicates that the channel
  3415. * is not supported by the hardware at all.
  3416. *
  3417. * A value of 0xfe in the channel_map indicates that the channel is not
  3418. * valid for Tx with the current hardware. This means that
  3419. * while the system can tune and receive on a given channel, it may not
  3420. * be able to associate or transmit any frames on that
  3421. * channel. There is no corresponding channel information for that
  3422. * entry.
  3423. *
  3424. *********************************************************************/
  3425. /* 2.4 GHz */
  3426. static const u8 iwl3945_eeprom_band_1[14] = {
  3427. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3428. };
  3429. /* 5.2 GHz bands */
  3430. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3431. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3432. };
  3433. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3434. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3435. };
  3436. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3437. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3438. };
  3439. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3440. 145, 149, 153, 157, 161, 165
  3441. };
  3442. static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
  3443. int *eeprom_ch_count,
  3444. const struct iwl_eeprom_channel
  3445. **eeprom_ch_info,
  3446. const u8 **eeprom_ch_index)
  3447. {
  3448. switch (band) {
  3449. case 1: /* 2.4GHz band */
  3450. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3451. *eeprom_ch_info = priv->eeprom39.band_1_channels;
  3452. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3453. break;
  3454. case 2: /* 4.9GHz band */
  3455. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3456. *eeprom_ch_info = priv->eeprom39.band_2_channels;
  3457. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3458. break;
  3459. case 3: /* 5.2GHz band */
  3460. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3461. *eeprom_ch_info = priv->eeprom39.band_3_channels;
  3462. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3463. break;
  3464. case 4: /* 5.5GHz band */
  3465. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3466. *eeprom_ch_info = priv->eeprom39.band_4_channels;
  3467. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3468. break;
  3469. case 5: /* 5.7GHz band */
  3470. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3471. *eeprom_ch_info = priv->eeprom39.band_5_channels;
  3472. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3473. break;
  3474. default:
  3475. BUG();
  3476. return;
  3477. }
  3478. }
  3479. /**
  3480. * iwl3945_get_channel_info - Find driver's private channel info
  3481. *
  3482. * Based on band and channel number.
  3483. */
  3484. const struct iwl_channel_info *
  3485. iwl3945_get_channel_info(const struct iwl_priv *priv,
  3486. enum ieee80211_band band, u16 channel)
  3487. {
  3488. int i;
  3489. switch (band) {
  3490. case IEEE80211_BAND_5GHZ:
  3491. for (i = 14; i < priv->channel_count; i++) {
  3492. if (priv->channel_info[i].channel == channel)
  3493. return &priv->channel_info[i];
  3494. }
  3495. break;
  3496. case IEEE80211_BAND_2GHZ:
  3497. if (channel >= 1 && channel <= 14)
  3498. return &priv->channel_info[channel - 1];
  3499. break;
  3500. case IEEE80211_NUM_BANDS:
  3501. WARN_ON(1);
  3502. }
  3503. return NULL;
  3504. }
  3505. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3506. ? # x " " : "")
  3507. /**
  3508. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3509. */
  3510. static int iwl3945_init_channel_map(struct iwl_priv *priv)
  3511. {
  3512. int eeprom_ch_count = 0;
  3513. const u8 *eeprom_ch_index = NULL;
  3514. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3515. int band, ch;
  3516. struct iwl_channel_info *ch_info;
  3517. if (priv->channel_count) {
  3518. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3519. return 0;
  3520. }
  3521. if (priv->eeprom39.version < 0x2f) {
  3522. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3523. priv->eeprom39.version);
  3524. return -EINVAL;
  3525. }
  3526. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3527. priv->channel_count =
  3528. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3529. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3530. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3531. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3532. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3533. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3534. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3535. priv->channel_count, GFP_KERNEL);
  3536. if (!priv->channel_info) {
  3537. IWL_ERR(priv, "Could not allocate channel_info\n");
  3538. priv->channel_count = 0;
  3539. return -ENOMEM;
  3540. }
  3541. ch_info = priv->channel_info;
  3542. /* Loop through the 5 EEPROM bands adding them in order to the
  3543. * channel map we maintain (that contains additional information than
  3544. * what just in the EEPROM) */
  3545. for (band = 1; band <= 5; band++) {
  3546. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3547. &eeprom_ch_info, &eeprom_ch_index);
  3548. /* Loop through each band adding each of the channels */
  3549. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3550. ch_info->channel = eeprom_ch_index[ch];
  3551. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3552. IEEE80211_BAND_5GHZ;
  3553. /* permanently store EEPROM's channel regulatory flags
  3554. * and max power in channel info database. */
  3555. ch_info->eeprom = eeprom_ch_info[ch];
  3556. /* Copy the run-time flags so they are there even on
  3557. * invalid channels */
  3558. ch_info->flags = eeprom_ch_info[ch].flags;
  3559. if (!(is_channel_valid(ch_info))) {
  3560. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3561. "No traffic\n",
  3562. ch_info->channel,
  3563. ch_info->flags,
  3564. is_channel_a_band(ch_info) ?
  3565. "5.2" : "2.4");
  3566. ch_info++;
  3567. continue;
  3568. }
  3569. /* Initialize regulatory-based run-time data */
  3570. ch_info->max_power_avg = ch_info->curr_txpow =
  3571. eeprom_ch_info[ch].max_power_avg;
  3572. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3573. ch_info->min_power = 0;
  3574. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3575. " %ddBm): Ad-Hoc %ssupported\n",
  3576. ch_info->channel,
  3577. is_channel_a_band(ch_info) ?
  3578. "5.2" : "2.4",
  3579. CHECK_AND_PRINT(VALID),
  3580. CHECK_AND_PRINT(IBSS),
  3581. CHECK_AND_PRINT(ACTIVE),
  3582. CHECK_AND_PRINT(RADAR),
  3583. CHECK_AND_PRINT(WIDE),
  3584. CHECK_AND_PRINT(DFS),
  3585. eeprom_ch_info[ch].flags,
  3586. eeprom_ch_info[ch].max_power_avg,
  3587. ((eeprom_ch_info[ch].
  3588. flags & EEPROM_CHANNEL_IBSS)
  3589. && !(eeprom_ch_info[ch].
  3590. flags & EEPROM_CHANNEL_RADAR))
  3591. ? "" : "not ");
  3592. /* Set the user_txpower_limit to the highest power
  3593. * supported by any channel */
  3594. if (eeprom_ch_info[ch].max_power_avg >
  3595. priv->user_txpower_limit)
  3596. priv->user_txpower_limit =
  3597. eeprom_ch_info[ch].max_power_avg;
  3598. ch_info++;
  3599. }
  3600. }
  3601. /* Set up txpower settings in driver for all channels */
  3602. if (iwl3945_txpower_set_from_eeprom(priv))
  3603. return -EIO;
  3604. return 0;
  3605. }
  3606. /*
  3607. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3608. */
  3609. static void iwl3945_free_channel_map(struct iwl_priv *priv)
  3610. {
  3611. kfree(priv->channel_info);
  3612. priv->channel_count = 0;
  3613. }
  3614. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3615. * sending probe req. This should be set long enough to hear probe responses
  3616. * from more than one AP. */
  3617. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3618. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3619. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3620. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3621. /* For faster active scanning, scan will move to the next channel if fewer than
  3622. * PLCP_QUIET_THRESH packets are heard on this channel within
  3623. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3624. * time if it's a quiet channel (nothing responded to our probe, and there's
  3625. * no other traffic).
  3626. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3627. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3628. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3629. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3630. * Must be set longer than active dwell time.
  3631. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3632. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3633. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3634. #define IWL_PASSIVE_DWELL_BASE (100)
  3635. #define IWL_CHANNEL_TUNE_TIME 5
  3636. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3637. static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
  3638. enum ieee80211_band band,
  3639. u8 n_probes)
  3640. {
  3641. if (band == IEEE80211_BAND_5GHZ)
  3642. return IWL_ACTIVE_DWELL_TIME_52 +
  3643. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3644. else
  3645. return IWL_ACTIVE_DWELL_TIME_24 +
  3646. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3647. }
  3648. static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
  3649. enum ieee80211_band band)
  3650. {
  3651. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3652. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3653. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3654. if (iwl3945_is_associated(priv)) {
  3655. /* If we're associated, we clamp the maximum passive
  3656. * dwell time to be 98% of the beacon interval (minus
  3657. * 2 * channel tune time) */
  3658. passive = priv->beacon_int;
  3659. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3660. passive = IWL_PASSIVE_DWELL_BASE;
  3661. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3662. }
  3663. return passive;
  3664. }
  3665. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  3666. enum ieee80211_band band,
  3667. u8 is_active, u8 n_probes,
  3668. struct iwl3945_scan_channel *scan_ch)
  3669. {
  3670. const struct ieee80211_channel *channels = NULL;
  3671. const struct ieee80211_supported_band *sband;
  3672. const struct iwl_channel_info *ch_info;
  3673. u16 passive_dwell = 0;
  3674. u16 active_dwell = 0;
  3675. int added, i;
  3676. sband = iwl_get_hw_mode(priv, band);
  3677. if (!sband)
  3678. return 0;
  3679. channels = sband->channels;
  3680. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3681. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3682. if (passive_dwell <= active_dwell)
  3683. passive_dwell = active_dwell + 1;
  3684. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3685. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3686. continue;
  3687. scan_ch->channel = channels[i].hw_value;
  3688. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3689. if (!is_channel_valid(ch_info)) {
  3690. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3691. scan_ch->channel);
  3692. continue;
  3693. }
  3694. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3695. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3696. /* If passive , set up for auto-switch
  3697. * and use long active_dwell time.
  3698. */
  3699. if (!is_active || is_channel_passive(ch_info) ||
  3700. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3701. scan_ch->type = 0; /* passive */
  3702. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3703. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3704. } else {
  3705. scan_ch->type = 1; /* active */
  3706. }
  3707. /* Set direct probe bits. These may be used both for active
  3708. * scan channels (probes gets sent right away),
  3709. * or for passive channels (probes get se sent only after
  3710. * hearing clear Rx packet).*/
  3711. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3712. if (n_probes)
  3713. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3714. } else {
  3715. /* uCode v1 does not allow setting direct probe bits on
  3716. * passive channel. */
  3717. if ((scan_ch->type & 1) && n_probes)
  3718. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3719. }
  3720. /* Set txpower levels to defaults */
  3721. scan_ch->tpc.dsp_atten = 110;
  3722. /* scan_pwr_info->tpc.dsp_atten; */
  3723. /*scan_pwr_info->tpc.tx_gain; */
  3724. if (band == IEEE80211_BAND_5GHZ)
  3725. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3726. else {
  3727. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3728. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3729. * power level:
  3730. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3731. */
  3732. }
  3733. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3734. scan_ch->channel,
  3735. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3736. (scan_ch->type & 1) ?
  3737. active_dwell : passive_dwell);
  3738. scan_ch++;
  3739. added++;
  3740. }
  3741. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3742. return added;
  3743. }
  3744. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  3745. struct ieee80211_rate *rates)
  3746. {
  3747. int i;
  3748. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3749. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3750. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3751. rates[i].hw_value_short = i;
  3752. rates[i].flags = 0;
  3753. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  3754. /*
  3755. * If CCK != 1M then set short preamble rate flag.
  3756. */
  3757. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  3758. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3759. }
  3760. }
  3761. }
  3762. /**
  3763. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  3764. */
  3765. static int iwl3945_init_geos(struct iwl_priv *priv)
  3766. {
  3767. struct iwl_channel_info *ch;
  3768. struct ieee80211_supported_band *sband;
  3769. struct ieee80211_channel *channels;
  3770. struct ieee80211_channel *geo_ch;
  3771. struct ieee80211_rate *rates;
  3772. int i = 0;
  3773. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  3774. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  3775. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  3776. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3777. return 0;
  3778. }
  3779. channels = kzalloc(sizeof(struct ieee80211_channel) *
  3780. priv->channel_count, GFP_KERNEL);
  3781. if (!channels)
  3782. return -ENOMEM;
  3783. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  3784. GFP_KERNEL);
  3785. if (!rates) {
  3786. kfree(channels);
  3787. return -ENOMEM;
  3788. }
  3789. /* 5.2GHz channels start after the 2.4GHz channels */
  3790. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3791. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  3792. /* just OFDM */
  3793. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  3794. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  3795. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3796. sband->channels = channels;
  3797. /* OFDM & CCK */
  3798. sband->bitrates = rates;
  3799. sband->n_bitrates = IWL_RATE_COUNT;
  3800. priv->ieee_channels = channels;
  3801. priv->ieee_rates = rates;
  3802. iwl3945_init_hw_rates(priv, rates);
  3803. for (i = 0; i < priv->channel_count; i++) {
  3804. ch = &priv->channel_info[i];
  3805. /* FIXME: might be removed if scan is OK*/
  3806. if (!is_channel_valid(ch))
  3807. continue;
  3808. if (is_channel_a_band(ch))
  3809. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3810. else
  3811. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3812. geo_ch = &sband->channels[sband->n_channels++];
  3813. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  3814. geo_ch->max_power = ch->max_power_avg;
  3815. geo_ch->max_antenna_gain = 0xff;
  3816. geo_ch->hw_value = ch->channel;
  3817. if (is_channel_valid(ch)) {
  3818. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  3819. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  3820. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  3821. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  3822. if (ch->flags & EEPROM_CHANNEL_RADAR)
  3823. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  3824. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  3825. priv->max_channel_txpower_limit =
  3826. ch->max_power_avg;
  3827. } else {
  3828. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  3829. }
  3830. /* Save flags for reg domain usage */
  3831. geo_ch->orig_flags = geo_ch->flags;
  3832. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  3833. ch->channel, geo_ch->center_freq,
  3834. is_channel_a_band(ch) ? "5.2" : "2.4",
  3835. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  3836. "restricted" : "valid",
  3837. geo_ch->flags);
  3838. }
  3839. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  3840. priv->cfg->sku & IWL_SKU_A) {
  3841. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  3842. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  3843. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  3844. priv->cfg->sku &= ~IWL_SKU_A;
  3845. }
  3846. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  3847. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  3848. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  3849. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3850. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3851. &priv->bands[IEEE80211_BAND_2GHZ];
  3852. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3853. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3854. &priv->bands[IEEE80211_BAND_5GHZ];
  3855. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3856. return 0;
  3857. }
  3858. /*
  3859. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  3860. */
  3861. static void iwl3945_free_geos(struct iwl_priv *priv)
  3862. {
  3863. kfree(priv->ieee_channels);
  3864. kfree(priv->ieee_rates);
  3865. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3866. }
  3867. /******************************************************************************
  3868. *
  3869. * uCode download functions
  3870. *
  3871. ******************************************************************************/
  3872. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  3873. {
  3874. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  3875. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  3876. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  3877. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  3878. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  3879. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  3880. }
  3881. /**
  3882. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  3883. * looking at all data.
  3884. */
  3885. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  3886. {
  3887. u32 val;
  3888. u32 save_len = len;
  3889. int rc = 0;
  3890. u32 errcnt;
  3891. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  3892. rc = iwl_grab_nic_access(priv);
  3893. if (rc)
  3894. return rc;
  3895. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  3896. IWL39_RTC_INST_LOWER_BOUND);
  3897. errcnt = 0;
  3898. for (; len > 0; len -= sizeof(u32), image++) {
  3899. /* read data comes through single port, auto-incr addr */
  3900. /* NOTE: Use the debugless read so we don't flood kernel log
  3901. * if IWL_DL_IO is set */
  3902. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  3903. if (val != le32_to_cpu(*image)) {
  3904. IWL_ERR(priv, "uCode INST section is invalid at "
  3905. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  3906. save_len - len, val, le32_to_cpu(*image));
  3907. rc = -EIO;
  3908. errcnt++;
  3909. if (errcnt >= 20)
  3910. break;
  3911. }
  3912. }
  3913. iwl_release_nic_access(priv);
  3914. if (!errcnt)
  3915. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  3916. return rc;
  3917. }
  3918. /**
  3919. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  3920. * using sample data 100 bytes apart. If these sample points are good,
  3921. * it's a pretty good bet that everything between them is good, too.
  3922. */
  3923. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  3924. {
  3925. u32 val;
  3926. int rc = 0;
  3927. u32 errcnt = 0;
  3928. u32 i;
  3929. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  3930. rc = iwl_grab_nic_access(priv);
  3931. if (rc)
  3932. return rc;
  3933. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  3934. /* read data comes through single port, auto-incr addr */
  3935. /* NOTE: Use the debugless read so we don't flood kernel log
  3936. * if IWL_DL_IO is set */
  3937. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  3938. i + IWL39_RTC_INST_LOWER_BOUND);
  3939. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  3940. if (val != le32_to_cpu(*image)) {
  3941. #if 0 /* Enable this if you want to see details */
  3942. IWL_ERR(priv, "uCode INST section is invalid at "
  3943. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  3944. i, val, *image);
  3945. #endif
  3946. rc = -EIO;
  3947. errcnt++;
  3948. if (errcnt >= 3)
  3949. break;
  3950. }
  3951. }
  3952. iwl_release_nic_access(priv);
  3953. return rc;
  3954. }
  3955. /**
  3956. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  3957. * and verify its contents
  3958. */
  3959. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  3960. {
  3961. __le32 *image;
  3962. u32 len;
  3963. int rc = 0;
  3964. /* Try bootstrap */
  3965. image = (__le32 *)priv->ucode_boot.v_addr;
  3966. len = priv->ucode_boot.len;
  3967. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3968. if (rc == 0) {
  3969. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  3970. return 0;
  3971. }
  3972. /* Try initialize */
  3973. image = (__le32 *)priv->ucode_init.v_addr;
  3974. len = priv->ucode_init.len;
  3975. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3976. if (rc == 0) {
  3977. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  3978. return 0;
  3979. }
  3980. /* Try runtime/protocol */
  3981. image = (__le32 *)priv->ucode_code.v_addr;
  3982. len = priv->ucode_code.len;
  3983. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3984. if (rc == 0) {
  3985. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  3986. return 0;
  3987. }
  3988. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  3989. /* Since nothing seems to match, show first several data entries in
  3990. * instruction SRAM, so maybe visual inspection will give a clue.
  3991. * Selection of bootstrap image (vs. other images) is arbitrary. */
  3992. image = (__le32 *)priv->ucode_boot.v_addr;
  3993. len = priv->ucode_boot.len;
  3994. rc = iwl3945_verify_inst_full(priv, image, len);
  3995. return rc;
  3996. }
  3997. static void iwl3945_nic_start(struct iwl_priv *priv)
  3998. {
  3999. /* Remove all resets to allow NIC to operate */
  4000. iwl_write32(priv, CSR_RESET, 0);
  4001. }
  4002. /**
  4003. * iwl3945_read_ucode - Read uCode images from disk file.
  4004. *
  4005. * Copy into buffers for card to fetch via bus-mastering
  4006. */
  4007. static int iwl3945_read_ucode(struct iwl_priv *priv)
  4008. {
  4009. struct iwl_ucode *ucode;
  4010. int ret = -EINVAL, index;
  4011. const struct firmware *ucode_raw;
  4012. /* firmware file name contains uCode/driver compatibility version */
  4013. const char *name_pre = priv->cfg->fw_name_pre;
  4014. const unsigned int api_max = priv->cfg->ucode_api_max;
  4015. const unsigned int api_min = priv->cfg->ucode_api_min;
  4016. char buf[25];
  4017. u8 *src;
  4018. size_t len;
  4019. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4020. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4021. * request_firmware() is synchronous, file is in memory on return. */
  4022. for (index = api_max; index >= api_min; index--) {
  4023. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4024. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4025. if (ret < 0) {
  4026. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  4027. buf, ret);
  4028. if (ret == -ENOENT)
  4029. continue;
  4030. else
  4031. goto error;
  4032. } else {
  4033. if (index < api_max)
  4034. IWL_ERR(priv, "Loaded firmware %s, "
  4035. "which is deprecated. "
  4036. " Please use API v%u instead.\n",
  4037. buf, api_max);
  4038. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4039. buf, ucode_raw->size);
  4040. break;
  4041. }
  4042. }
  4043. if (ret < 0)
  4044. goto error;
  4045. /* Make sure that we got at least our header! */
  4046. if (ucode_raw->size < sizeof(*ucode)) {
  4047. IWL_ERR(priv, "File size way too small!\n");
  4048. ret = -EINVAL;
  4049. goto err_release;
  4050. }
  4051. /* Data from ucode file: header followed by uCode images */
  4052. ucode = (void *)ucode_raw->data;
  4053. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4054. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4055. inst_size = le32_to_cpu(ucode->inst_size);
  4056. data_size = le32_to_cpu(ucode->data_size);
  4057. init_size = le32_to_cpu(ucode->init_size);
  4058. init_data_size = le32_to_cpu(ucode->init_data_size);
  4059. boot_size = le32_to_cpu(ucode->boot_size);
  4060. /* api_ver should match the api version forming part of the
  4061. * firmware filename ... but we don't check for that and only rely
  4062. * on the API version read from firware header from here on forward */
  4063. if (api_ver < api_min || api_ver > api_max) {
  4064. IWL_ERR(priv, "Driver unable to support your firmware API. "
  4065. "Driver supports v%u, firmware is v%u.\n",
  4066. api_max, api_ver);
  4067. priv->ucode_ver = 0;
  4068. ret = -EINVAL;
  4069. goto err_release;
  4070. }
  4071. if (api_ver != api_max)
  4072. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  4073. "got %u. New firmware can be obtained "
  4074. "from http://www.intellinuxwireless.org.\n",
  4075. api_max, api_ver);
  4076. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  4077. IWL_UCODE_MAJOR(priv->ucode_ver),
  4078. IWL_UCODE_MINOR(priv->ucode_ver),
  4079. IWL_UCODE_API(priv->ucode_ver),
  4080. IWL_UCODE_SERIAL(priv->ucode_ver));
  4081. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4082. priv->ucode_ver);
  4083. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4084. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4085. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4086. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4087. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4088. /* Verify size of file vs. image size info in file's header */
  4089. if (ucode_raw->size < sizeof(*ucode) +
  4090. inst_size + data_size + init_size +
  4091. init_data_size + boot_size) {
  4092. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4093. (int)ucode_raw->size);
  4094. ret = -EINVAL;
  4095. goto err_release;
  4096. }
  4097. /* Verify that uCode images will fit in card's SRAM */
  4098. if (inst_size > IWL39_MAX_INST_SIZE) {
  4099. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4100. inst_size);
  4101. ret = -EINVAL;
  4102. goto err_release;
  4103. }
  4104. if (data_size > IWL39_MAX_DATA_SIZE) {
  4105. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4106. data_size);
  4107. ret = -EINVAL;
  4108. goto err_release;
  4109. }
  4110. if (init_size > IWL39_MAX_INST_SIZE) {
  4111. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4112. init_size);
  4113. ret = -EINVAL;
  4114. goto err_release;
  4115. }
  4116. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  4117. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4118. init_data_size);
  4119. ret = -EINVAL;
  4120. goto err_release;
  4121. }
  4122. if (boot_size > IWL39_MAX_BSM_SIZE) {
  4123. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4124. boot_size);
  4125. ret = -EINVAL;
  4126. goto err_release;
  4127. }
  4128. /* Allocate ucode buffers for card's bus-master loading ... */
  4129. /* Runtime instructions and 2 copies of data:
  4130. * 1) unmodified from disk
  4131. * 2) backup cache for save/restore during power-downs */
  4132. priv->ucode_code.len = inst_size;
  4133. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4134. priv->ucode_data.len = data_size;
  4135. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4136. priv->ucode_data_backup.len = data_size;
  4137. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4138. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4139. !priv->ucode_data_backup.v_addr)
  4140. goto err_pci_alloc;
  4141. /* Initialization instructions and data */
  4142. if (init_size && init_data_size) {
  4143. priv->ucode_init.len = init_size;
  4144. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4145. priv->ucode_init_data.len = init_data_size;
  4146. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4147. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4148. goto err_pci_alloc;
  4149. }
  4150. /* Bootstrap (instructions only, no data) */
  4151. if (boot_size) {
  4152. priv->ucode_boot.len = boot_size;
  4153. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4154. if (!priv->ucode_boot.v_addr)
  4155. goto err_pci_alloc;
  4156. }
  4157. /* Copy images into buffers for card's bus-master reads ... */
  4158. /* Runtime instructions (first block of data in file) */
  4159. src = &ucode->data[0];
  4160. len = priv->ucode_code.len;
  4161. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4162. memcpy(priv->ucode_code.v_addr, src, len);
  4163. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4164. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4165. /* Runtime data (2nd block)
  4166. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4167. src = &ucode->data[inst_size];
  4168. len = priv->ucode_data.len;
  4169. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4170. memcpy(priv->ucode_data.v_addr, src, len);
  4171. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4172. /* Initialization instructions (3rd block) */
  4173. if (init_size) {
  4174. src = &ucode->data[inst_size + data_size];
  4175. len = priv->ucode_init.len;
  4176. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4177. len);
  4178. memcpy(priv->ucode_init.v_addr, src, len);
  4179. }
  4180. /* Initialization data (4th block) */
  4181. if (init_data_size) {
  4182. src = &ucode->data[inst_size + data_size + init_size];
  4183. len = priv->ucode_init_data.len;
  4184. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4185. (int)len);
  4186. memcpy(priv->ucode_init_data.v_addr, src, len);
  4187. }
  4188. /* Bootstrap instructions (5th block) */
  4189. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4190. len = priv->ucode_boot.len;
  4191. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4192. (int)len);
  4193. memcpy(priv->ucode_boot.v_addr, src, len);
  4194. /* We have our copies now, allow OS release its copies */
  4195. release_firmware(ucode_raw);
  4196. return 0;
  4197. err_pci_alloc:
  4198. IWL_ERR(priv, "failed to allocate pci memory\n");
  4199. ret = -ENOMEM;
  4200. iwl3945_dealloc_ucode_pci(priv);
  4201. err_release:
  4202. release_firmware(ucode_raw);
  4203. error:
  4204. return ret;
  4205. }
  4206. /**
  4207. * iwl3945_set_ucode_ptrs - Set uCode address location
  4208. *
  4209. * Tell initialization uCode where to find runtime uCode.
  4210. *
  4211. * BSM registers initially contain pointers to initialization uCode.
  4212. * We need to replace them to load runtime uCode inst and data,
  4213. * and to save runtime data when powering down.
  4214. */
  4215. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  4216. {
  4217. dma_addr_t pinst;
  4218. dma_addr_t pdata;
  4219. int rc = 0;
  4220. unsigned long flags;
  4221. /* bits 31:0 for 3945 */
  4222. pinst = priv->ucode_code.p_addr;
  4223. pdata = priv->ucode_data_backup.p_addr;
  4224. spin_lock_irqsave(&priv->lock, flags);
  4225. rc = iwl_grab_nic_access(priv);
  4226. if (rc) {
  4227. spin_unlock_irqrestore(&priv->lock, flags);
  4228. return rc;
  4229. }
  4230. /* Tell bootstrap uCode where to find image to load */
  4231. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4232. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4233. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4234. priv->ucode_data.len);
  4235. /* Inst byte count must be last to set up, bit 31 signals uCode
  4236. * that all new ptr/size info is in place */
  4237. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4238. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4239. iwl_release_nic_access(priv);
  4240. spin_unlock_irqrestore(&priv->lock, flags);
  4241. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4242. return rc;
  4243. }
  4244. /**
  4245. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4246. *
  4247. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4248. *
  4249. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4250. */
  4251. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  4252. {
  4253. /* Check alive response for "valid" sign from uCode */
  4254. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4255. /* We had an error bringing up the hardware, so take it
  4256. * all the way back down so we can try again */
  4257. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4258. goto restart;
  4259. }
  4260. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4261. * This is a paranoid check, because we would not have gotten the
  4262. * "initialize" alive if code weren't properly loaded. */
  4263. if (iwl3945_verify_ucode(priv)) {
  4264. /* Runtime instruction load was bad;
  4265. * take it all the way back down so we can try again */
  4266. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4267. goto restart;
  4268. }
  4269. /* Send pointers to protocol/runtime uCode image ... init code will
  4270. * load and launch runtime uCode, which will send us another "Alive"
  4271. * notification. */
  4272. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4273. if (iwl3945_set_ucode_ptrs(priv)) {
  4274. /* Runtime instruction load won't happen;
  4275. * take it all the way back down so we can try again */
  4276. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4277. goto restart;
  4278. }
  4279. return;
  4280. restart:
  4281. queue_work(priv->workqueue, &priv->restart);
  4282. }
  4283. /* temporary */
  4284. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4285. struct sk_buff *skb);
  4286. /**
  4287. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4288. * from protocol/runtime uCode (initialization uCode's
  4289. * Alive gets handled by iwl3945_init_alive_start()).
  4290. */
  4291. static void iwl3945_alive_start(struct iwl_priv *priv)
  4292. {
  4293. int rc = 0;
  4294. int thermal_spin = 0;
  4295. u32 rfkill;
  4296. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4297. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4298. /* We had an error bringing up the hardware, so take it
  4299. * all the way back down so we can try again */
  4300. IWL_DEBUG_INFO("Alive failed.\n");
  4301. goto restart;
  4302. }
  4303. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4304. * This is a paranoid check, because we would not have gotten the
  4305. * "runtime" alive if code weren't properly loaded. */
  4306. if (iwl3945_verify_ucode(priv)) {
  4307. /* Runtime instruction load was bad;
  4308. * take it all the way back down so we can try again */
  4309. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4310. goto restart;
  4311. }
  4312. iwl3945_clear_stations_table(priv);
  4313. rc = iwl_grab_nic_access(priv);
  4314. if (rc) {
  4315. IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
  4316. return;
  4317. }
  4318. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  4319. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4320. iwl_release_nic_access(priv);
  4321. if (rfkill & 0x1) {
  4322. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4323. /* if RFKILL is not on, then wait for thermal
  4324. * sensor in adapter to kick in */
  4325. while (iwl3945_hw_get_temperature(priv) == 0) {
  4326. thermal_spin++;
  4327. udelay(10);
  4328. }
  4329. if (thermal_spin)
  4330. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4331. thermal_spin * 10);
  4332. } else
  4333. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4334. /* After the ALIVE response, we can send commands to 3945 uCode */
  4335. set_bit(STATUS_ALIVE, &priv->status);
  4336. /* Clear out the uCode error bit if it is set */
  4337. clear_bit(STATUS_FW_ERROR, &priv->status);
  4338. if (iwl_is_rfkill(priv))
  4339. return;
  4340. ieee80211_wake_queues(priv->hw);
  4341. priv->active_rate = priv->rates_mask;
  4342. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4343. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4344. if (iwl3945_is_associated(priv)) {
  4345. struct iwl3945_rxon_cmd *active_rxon =
  4346. (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
  4347. memcpy(&priv->staging39_rxon, &priv->active39_rxon,
  4348. sizeof(priv->staging39_rxon));
  4349. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4350. } else {
  4351. /* Initialize our rx_config data */
  4352. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4353. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4354. }
  4355. /* Configure Bluetooth device coexistence support */
  4356. iwl3945_send_bt_config(priv);
  4357. /* Configure the adapter for unassociated operation */
  4358. iwl3945_commit_rxon(priv);
  4359. iwl3945_reg_txpower_periodic(priv);
  4360. iwl3945_led_register(priv);
  4361. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4362. set_bit(STATUS_READY, &priv->status);
  4363. wake_up_interruptible(&priv->wait_command_queue);
  4364. if (priv->error_recovering)
  4365. iwl3945_error_recovery(priv);
  4366. /* reassociate for ADHOC mode */
  4367. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4368. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4369. priv->vif);
  4370. if (beacon)
  4371. iwl3945_mac_beacon_update(priv->hw, beacon);
  4372. }
  4373. return;
  4374. restart:
  4375. queue_work(priv->workqueue, &priv->restart);
  4376. }
  4377. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  4378. static void __iwl3945_down(struct iwl_priv *priv)
  4379. {
  4380. unsigned long flags;
  4381. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4382. struct ieee80211_conf *conf = NULL;
  4383. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4384. conf = ieee80211_get_hw_conf(priv->hw);
  4385. if (!exit_pending)
  4386. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4387. iwl3945_led_unregister(priv);
  4388. iwl3945_clear_stations_table(priv);
  4389. /* Unblock any waiting calls */
  4390. wake_up_interruptible_all(&priv->wait_command_queue);
  4391. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4392. * exiting the module */
  4393. if (!exit_pending)
  4394. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4395. /* stop and reset the on-board processor */
  4396. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4397. /* tell the device to stop sending interrupts */
  4398. spin_lock_irqsave(&priv->lock, flags);
  4399. iwl3945_disable_interrupts(priv);
  4400. spin_unlock_irqrestore(&priv->lock, flags);
  4401. iwl_synchronize_irq(priv);
  4402. if (priv->mac80211_registered)
  4403. ieee80211_stop_queues(priv->hw);
  4404. /* If we have not previously called iwl3945_init() then
  4405. * clear all bits but the RF Kill and SUSPEND bits and return */
  4406. if (!iwl_is_init(priv)) {
  4407. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4408. STATUS_RF_KILL_HW |
  4409. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4410. STATUS_RF_KILL_SW |
  4411. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4412. STATUS_GEO_CONFIGURED |
  4413. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4414. STATUS_IN_SUSPEND |
  4415. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4416. STATUS_EXIT_PENDING;
  4417. goto exit;
  4418. }
  4419. /* ...otherwise clear out all the status bits but the RF Kill and
  4420. * SUSPEND bits and continue taking the NIC down. */
  4421. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4422. STATUS_RF_KILL_HW |
  4423. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4424. STATUS_RF_KILL_SW |
  4425. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4426. STATUS_GEO_CONFIGURED |
  4427. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4428. STATUS_IN_SUSPEND |
  4429. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4430. STATUS_FW_ERROR |
  4431. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4432. STATUS_EXIT_PENDING;
  4433. spin_lock_irqsave(&priv->lock, flags);
  4434. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4435. spin_unlock_irqrestore(&priv->lock, flags);
  4436. iwl3945_hw_txq_ctx_stop(priv);
  4437. iwl3945_hw_rxq_stop(priv);
  4438. spin_lock_irqsave(&priv->lock, flags);
  4439. if (!iwl_grab_nic_access(priv)) {
  4440. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  4441. APMG_CLK_VAL_DMA_CLK_RQT);
  4442. iwl_release_nic_access(priv);
  4443. }
  4444. spin_unlock_irqrestore(&priv->lock, flags);
  4445. udelay(5);
  4446. priv->cfg->ops->lib->apm_ops.reset(priv);
  4447. exit:
  4448. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4449. if (priv->ibss_beacon)
  4450. dev_kfree_skb(priv->ibss_beacon);
  4451. priv->ibss_beacon = NULL;
  4452. /* clear out any free frames */
  4453. iwl3945_clear_free_frames(priv);
  4454. }
  4455. static void iwl3945_down(struct iwl_priv *priv)
  4456. {
  4457. mutex_lock(&priv->mutex);
  4458. __iwl3945_down(priv);
  4459. mutex_unlock(&priv->mutex);
  4460. iwl3945_cancel_deferred_work(priv);
  4461. }
  4462. #define MAX_HW_RESTARTS 5
  4463. static int __iwl3945_up(struct iwl_priv *priv)
  4464. {
  4465. int rc, i;
  4466. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4467. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  4468. return -EIO;
  4469. }
  4470. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4471. IWL_WARN(priv, "Radio disabled by SW RF kill (module "
  4472. "parameter)\n");
  4473. return -ENODEV;
  4474. }
  4475. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4476. IWL_ERR(priv, "ucode not available for device bring up\n");
  4477. return -EIO;
  4478. }
  4479. /* If platform's RF_KILL switch is NOT set to KILL */
  4480. if (iwl_read32(priv, CSR_GP_CNTRL) &
  4481. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4482. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4483. else {
  4484. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4485. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4486. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  4487. return -ENODEV;
  4488. }
  4489. }
  4490. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4491. rc = iwl3945_hw_nic_init(priv);
  4492. if (rc) {
  4493. IWL_ERR(priv, "Unable to int nic\n");
  4494. return rc;
  4495. }
  4496. /* make sure rfkill handshake bits are cleared */
  4497. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4498. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4499. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4500. /* clear (again), then enable host interrupts */
  4501. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4502. iwl3945_enable_interrupts(priv);
  4503. /* really make sure rfkill handshake bits are cleared */
  4504. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4505. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4506. /* Copy original ucode data image from disk into backup cache.
  4507. * This will be used to initialize the on-board processor's
  4508. * data SRAM for a clean start when the runtime program first loads. */
  4509. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4510. priv->ucode_data.len);
  4511. /* We return success when we resume from suspend and rf_kill is on. */
  4512. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4513. return 0;
  4514. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4515. iwl3945_clear_stations_table(priv);
  4516. /* load bootstrap state machine,
  4517. * load bootstrap program into processor's memory,
  4518. * prepare to load the "initialize" uCode */
  4519. priv->cfg->ops->lib->load_ucode(priv);
  4520. if (rc) {
  4521. IWL_ERR(priv,
  4522. "Unable to set up bootstrap uCode: %d\n", rc);
  4523. continue;
  4524. }
  4525. /* start card; "initialize" will load runtime ucode */
  4526. iwl3945_nic_start(priv);
  4527. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4528. return 0;
  4529. }
  4530. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4531. __iwl3945_down(priv);
  4532. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4533. /* tried to restart and config the device for as long as our
  4534. * patience could withstand */
  4535. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  4536. return -EIO;
  4537. }
  4538. /*****************************************************************************
  4539. *
  4540. * Workqueue callbacks
  4541. *
  4542. *****************************************************************************/
  4543. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4544. {
  4545. struct iwl_priv *priv =
  4546. container_of(data, struct iwl_priv, init_alive_start.work);
  4547. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4548. return;
  4549. mutex_lock(&priv->mutex);
  4550. iwl3945_init_alive_start(priv);
  4551. mutex_unlock(&priv->mutex);
  4552. }
  4553. static void iwl3945_bg_alive_start(struct work_struct *data)
  4554. {
  4555. struct iwl_priv *priv =
  4556. container_of(data, struct iwl_priv, alive_start.work);
  4557. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4558. return;
  4559. mutex_lock(&priv->mutex);
  4560. iwl3945_alive_start(priv);
  4561. mutex_unlock(&priv->mutex);
  4562. }
  4563. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4564. {
  4565. struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
  4566. wake_up_interruptible(&priv->wait_command_queue);
  4567. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4568. return;
  4569. mutex_lock(&priv->mutex);
  4570. if (!iwl_is_rfkill(priv)) {
  4571. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4572. "HW and/or SW RF Kill no longer active, restarting "
  4573. "device\n");
  4574. if (!test_bit(STATUS_EXIT_PENDING, &priv->status) &&
  4575. test_bit(STATUS_ALIVE, &priv->status))
  4576. queue_work(priv->workqueue, &priv->restart);
  4577. } else {
  4578. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4579. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4580. "disabled by SW switch\n");
  4581. else
  4582. IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
  4583. "Kill switch must be turned off for "
  4584. "wireless networking to work.\n");
  4585. }
  4586. mutex_unlock(&priv->mutex);
  4587. iwl3945_rfkill_set_hw_state(priv);
  4588. }
  4589. static void iwl3945_rfkill_poll(struct work_struct *data)
  4590. {
  4591. struct iwl_priv *priv =
  4592. container_of(data, struct iwl_priv, rfkill_poll.work);
  4593. unsigned long status = priv->status;
  4594. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4595. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4596. else
  4597. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4598. if (test_bit(STATUS_RF_KILL_HW, &status) != test_bit(STATUS_RF_KILL_HW, &priv->status))
  4599. queue_work(priv->workqueue, &priv->rf_kill);
  4600. queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
  4601. round_jiffies_relative(2 * HZ));
  4602. }
  4603. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4604. static void iwl3945_bg_scan_check(struct work_struct *data)
  4605. {
  4606. struct iwl_priv *priv =
  4607. container_of(data, struct iwl_priv, scan_check.work);
  4608. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4609. return;
  4610. mutex_lock(&priv->mutex);
  4611. if (test_bit(STATUS_SCANNING, &priv->status) ||
  4612. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4613. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  4614. "Scan completion watchdog resetting adapter (%dms)\n",
  4615. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  4616. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4617. iwl3945_send_scan_abort(priv);
  4618. }
  4619. mutex_unlock(&priv->mutex);
  4620. }
  4621. static void iwl3945_bg_request_scan(struct work_struct *data)
  4622. {
  4623. struct iwl_priv *priv =
  4624. container_of(data, struct iwl_priv, request_scan);
  4625. struct iwl_host_cmd cmd = {
  4626. .id = REPLY_SCAN_CMD,
  4627. .len = sizeof(struct iwl3945_scan_cmd),
  4628. .meta.flags = CMD_SIZE_HUGE,
  4629. };
  4630. int rc = 0;
  4631. struct iwl3945_scan_cmd *scan;
  4632. struct ieee80211_conf *conf = NULL;
  4633. u8 n_probes = 2;
  4634. enum ieee80211_band band;
  4635. DECLARE_SSID_BUF(ssid);
  4636. conf = ieee80211_get_hw_conf(priv->hw);
  4637. mutex_lock(&priv->mutex);
  4638. if (!iwl_is_ready(priv)) {
  4639. IWL_WARN(priv, "request scan called when driver not ready.\n");
  4640. goto done;
  4641. }
  4642. /* Make sure the scan wasn't canceled before this queued work
  4643. * was given the chance to run... */
  4644. if (!test_bit(STATUS_SCANNING, &priv->status))
  4645. goto done;
  4646. /* This should never be called or scheduled if there is currently
  4647. * a scan active in the hardware. */
  4648. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  4649. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  4650. "Ignoring second request.\n");
  4651. rc = -EIO;
  4652. goto done;
  4653. }
  4654. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4655. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  4656. goto done;
  4657. }
  4658. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4659. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  4660. goto done;
  4661. }
  4662. if (iwl_is_rfkill(priv)) {
  4663. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  4664. goto done;
  4665. }
  4666. if (!test_bit(STATUS_READY, &priv->status)) {
  4667. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  4668. goto done;
  4669. }
  4670. if (!priv->scan_bands) {
  4671. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  4672. goto done;
  4673. }
  4674. if (!priv->scan39) {
  4675. priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  4676. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  4677. if (!priv->scan39) {
  4678. rc = -ENOMEM;
  4679. goto done;
  4680. }
  4681. }
  4682. scan = priv->scan39;
  4683. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  4684. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  4685. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  4686. if (iwl3945_is_associated(priv)) {
  4687. u16 interval = 0;
  4688. u32 extra;
  4689. u32 suspend_time = 100;
  4690. u32 scan_suspend_time = 100;
  4691. unsigned long flags;
  4692. IWL_DEBUG_INFO("Scanning while associated...\n");
  4693. spin_lock_irqsave(&priv->lock, flags);
  4694. interval = priv->beacon_int;
  4695. spin_unlock_irqrestore(&priv->lock, flags);
  4696. scan->suspend_time = 0;
  4697. scan->max_out_time = cpu_to_le32(200 * 1024);
  4698. if (!interval)
  4699. interval = suspend_time;
  4700. /*
  4701. * suspend time format:
  4702. * 0-19: beacon interval in usec (time before exec.)
  4703. * 20-23: 0
  4704. * 24-31: number of beacons (suspend between channels)
  4705. */
  4706. extra = (suspend_time / interval) << 24;
  4707. scan_suspend_time = 0xFF0FFFFF &
  4708. (extra | ((suspend_time % interval) * 1024));
  4709. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  4710. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  4711. scan_suspend_time, interval);
  4712. }
  4713. /* We should add the ability for user to lock to PASSIVE ONLY */
  4714. if (priv->one_direct_scan) {
  4715. IWL_DEBUG_SCAN
  4716. ("Kicking off one direct scan for '%s'\n",
  4717. print_ssid(ssid, priv->direct_ssid,
  4718. priv->direct_ssid_len));
  4719. scan->direct_scan[0].id = WLAN_EID_SSID;
  4720. scan->direct_scan[0].len = priv->direct_ssid_len;
  4721. memcpy(scan->direct_scan[0].ssid,
  4722. priv->direct_ssid, priv->direct_ssid_len);
  4723. n_probes++;
  4724. } else
  4725. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  4726. /* We don't build a direct scan probe request; the uCode will do
  4727. * that based on the direct_mask added to each channel entry */
  4728. scan->tx_cmd.len = cpu_to_le16(
  4729. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  4730. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  4731. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  4732. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  4733. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  4734. /* flags + rate selection */
  4735. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  4736. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  4737. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  4738. scan->good_CRC_th = 0;
  4739. band = IEEE80211_BAND_2GHZ;
  4740. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  4741. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  4742. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  4743. band = IEEE80211_BAND_5GHZ;
  4744. } else {
  4745. IWL_WARN(priv, "Invalid scan band count\n");
  4746. goto done;
  4747. }
  4748. /* select Rx antennas */
  4749. scan->flags |= iwl3945_get_antenna_flags(priv);
  4750. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  4751. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  4752. scan->channel_count =
  4753. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  4754. n_probes,
  4755. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  4756. if (scan->channel_count == 0) {
  4757. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  4758. goto done;
  4759. }
  4760. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  4761. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  4762. cmd.data = scan;
  4763. scan->len = cpu_to_le16(cmd.len);
  4764. set_bit(STATUS_SCAN_HW, &priv->status);
  4765. rc = iwl3945_send_cmd_sync(priv, &cmd);
  4766. if (rc)
  4767. goto done;
  4768. queue_delayed_work(priv->workqueue, &priv->scan_check,
  4769. IWL_SCAN_CHECK_WATCHDOG);
  4770. mutex_unlock(&priv->mutex);
  4771. return;
  4772. done:
  4773. /* can not perform scan make sure we clear scanning
  4774. * bits from status so next scan request can be performed.
  4775. * if we dont clear scanning status bit here all next scan
  4776. * will fail
  4777. */
  4778. clear_bit(STATUS_SCAN_HW, &priv->status);
  4779. clear_bit(STATUS_SCANNING, &priv->status);
  4780. /* inform mac80211 scan aborted */
  4781. queue_work(priv->workqueue, &priv->scan_completed);
  4782. mutex_unlock(&priv->mutex);
  4783. }
  4784. static void iwl3945_bg_up(struct work_struct *data)
  4785. {
  4786. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  4787. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4788. return;
  4789. mutex_lock(&priv->mutex);
  4790. __iwl3945_up(priv);
  4791. mutex_unlock(&priv->mutex);
  4792. iwl3945_rfkill_set_hw_state(priv);
  4793. }
  4794. static void iwl3945_bg_restart(struct work_struct *data)
  4795. {
  4796. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  4797. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4798. return;
  4799. iwl3945_down(priv);
  4800. queue_work(priv->workqueue, &priv->up);
  4801. }
  4802. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  4803. {
  4804. struct iwl_priv *priv =
  4805. container_of(data, struct iwl_priv, rx_replenish);
  4806. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4807. return;
  4808. mutex_lock(&priv->mutex);
  4809. iwl3945_rx_replenish(priv);
  4810. mutex_unlock(&priv->mutex);
  4811. }
  4812. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  4813. static void iwl3945_post_associate(struct iwl_priv *priv)
  4814. {
  4815. int rc = 0;
  4816. struct ieee80211_conf *conf = NULL;
  4817. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  4818. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  4819. return;
  4820. }
  4821. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  4822. priv->assoc_id, priv->active39_rxon.bssid_addr);
  4823. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4824. return;
  4825. if (!priv->vif || !priv->is_open)
  4826. return;
  4827. iwl3945_scan_cancel_timeout(priv, 200);
  4828. conf = ieee80211_get_hw_conf(priv->hw);
  4829. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4830. iwl3945_commit_rxon(priv);
  4831. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  4832. iwl3945_setup_rxon_timing(priv);
  4833. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  4834. sizeof(priv->rxon_timing), &priv->rxon_timing);
  4835. if (rc)
  4836. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  4837. "Attempting to continue.\n");
  4838. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  4839. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  4840. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  4841. priv->assoc_id, priv->beacon_int);
  4842. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  4843. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4844. else
  4845. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4846. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  4847. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  4848. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  4849. else
  4850. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4851. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  4852. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4853. }
  4854. iwl3945_commit_rxon(priv);
  4855. switch (priv->iw_mode) {
  4856. case NL80211_IFTYPE_STATION:
  4857. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  4858. break;
  4859. case NL80211_IFTYPE_ADHOC:
  4860. priv->assoc_id = 1;
  4861. iwl3945_add_station(priv, priv->bssid, 0, 0);
  4862. iwl3945_sync_sta(priv, IWL_STA_ID,
  4863. (priv->band == IEEE80211_BAND_5GHZ) ?
  4864. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  4865. CMD_ASYNC);
  4866. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  4867. iwl3945_send_beacon_cmd(priv);
  4868. break;
  4869. default:
  4870. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  4871. __func__, priv->iw_mode);
  4872. break;
  4873. }
  4874. iwl3945_activate_qos(priv, 0);
  4875. /* we have just associated, don't start scan too early */
  4876. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  4877. }
  4878. static void iwl3945_bg_abort_scan(struct work_struct *work)
  4879. {
  4880. struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
  4881. if (!iwl_is_ready(priv))
  4882. return;
  4883. mutex_lock(&priv->mutex);
  4884. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  4885. iwl3945_send_scan_abort(priv);
  4886. mutex_unlock(&priv->mutex);
  4887. }
  4888. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  4889. static void iwl3945_bg_scan_completed(struct work_struct *work)
  4890. {
  4891. struct iwl_priv *priv =
  4892. container_of(work, struct iwl_priv, scan_completed);
  4893. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  4894. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4895. return;
  4896. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  4897. iwl3945_mac_config(priv->hw, 0);
  4898. ieee80211_scan_completed(priv->hw);
  4899. /* Since setting the TXPOWER may have been deferred while
  4900. * performing the scan, fire one off */
  4901. mutex_lock(&priv->mutex);
  4902. iwl3945_hw_reg_send_txpower(priv);
  4903. mutex_unlock(&priv->mutex);
  4904. }
  4905. /*****************************************************************************
  4906. *
  4907. * mac80211 entry point functions
  4908. *
  4909. *****************************************************************************/
  4910. #define UCODE_READY_TIMEOUT (2 * HZ)
  4911. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  4912. {
  4913. struct iwl_priv *priv = hw->priv;
  4914. int ret;
  4915. IWL_DEBUG_MAC80211("enter\n");
  4916. /* we should be verifying the device is ready to be opened */
  4917. mutex_lock(&priv->mutex);
  4918. memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  4919. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  4920. * ucode filename and max sizes are card-specific. */
  4921. if (!priv->ucode_code.len) {
  4922. ret = iwl3945_read_ucode(priv);
  4923. if (ret) {
  4924. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  4925. mutex_unlock(&priv->mutex);
  4926. goto out_release_irq;
  4927. }
  4928. }
  4929. ret = __iwl3945_up(priv);
  4930. mutex_unlock(&priv->mutex);
  4931. iwl3945_rfkill_set_hw_state(priv);
  4932. if (ret)
  4933. goto out_release_irq;
  4934. IWL_DEBUG_INFO("Start UP work.\n");
  4935. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  4936. return 0;
  4937. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  4938. * mac80211 will not be run successfully. */
  4939. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  4940. test_bit(STATUS_READY, &priv->status),
  4941. UCODE_READY_TIMEOUT);
  4942. if (!ret) {
  4943. if (!test_bit(STATUS_READY, &priv->status)) {
  4944. IWL_ERR(priv,
  4945. "Wait for START_ALIVE timeout after %dms.\n",
  4946. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  4947. ret = -ETIMEDOUT;
  4948. goto out_release_irq;
  4949. }
  4950. }
  4951. /* ucode is running and will send rfkill notifications,
  4952. * no need to poll the killswitch state anymore */
  4953. cancel_delayed_work(&priv->rfkill_poll);
  4954. priv->is_open = 1;
  4955. IWL_DEBUG_MAC80211("leave\n");
  4956. return 0;
  4957. out_release_irq:
  4958. priv->is_open = 0;
  4959. IWL_DEBUG_MAC80211("leave - failed\n");
  4960. return ret;
  4961. }
  4962. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  4963. {
  4964. struct iwl_priv *priv = hw->priv;
  4965. IWL_DEBUG_MAC80211("enter\n");
  4966. if (!priv->is_open) {
  4967. IWL_DEBUG_MAC80211("leave - skip\n");
  4968. return;
  4969. }
  4970. priv->is_open = 0;
  4971. if (iwl_is_ready_rf(priv)) {
  4972. /* stop mac, cancel any scan request and clear
  4973. * RXON_FILTER_ASSOC_MSK BIT
  4974. */
  4975. mutex_lock(&priv->mutex);
  4976. iwl3945_scan_cancel_timeout(priv, 100);
  4977. mutex_unlock(&priv->mutex);
  4978. }
  4979. iwl3945_down(priv);
  4980. flush_workqueue(priv->workqueue);
  4981. /* start polling the killswitch state again */
  4982. queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
  4983. round_jiffies_relative(2 * HZ));
  4984. IWL_DEBUG_MAC80211("leave\n");
  4985. }
  4986. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  4987. {
  4988. struct iwl_priv *priv = hw->priv;
  4989. IWL_DEBUG_MAC80211("enter\n");
  4990. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  4991. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  4992. if (iwl3945_tx_skb(priv, skb))
  4993. dev_kfree_skb_any(skb);
  4994. IWL_DEBUG_MAC80211("leave\n");
  4995. return NETDEV_TX_OK;
  4996. }
  4997. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  4998. struct ieee80211_if_init_conf *conf)
  4999. {
  5000. struct iwl_priv *priv = hw->priv;
  5001. unsigned long flags;
  5002. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5003. if (priv->vif) {
  5004. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5005. return -EOPNOTSUPP;
  5006. }
  5007. spin_lock_irqsave(&priv->lock, flags);
  5008. priv->vif = conf->vif;
  5009. priv->iw_mode = conf->type;
  5010. spin_unlock_irqrestore(&priv->lock, flags);
  5011. mutex_lock(&priv->mutex);
  5012. if (conf->mac_addr) {
  5013. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5014. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5015. }
  5016. if (iwl_is_ready(priv))
  5017. iwl3945_set_mode(priv, conf->type);
  5018. mutex_unlock(&priv->mutex);
  5019. IWL_DEBUG_MAC80211("leave\n");
  5020. return 0;
  5021. }
  5022. /**
  5023. * iwl3945_mac_config - mac80211 config callback
  5024. *
  5025. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5026. * be set inappropriately and the driver currently sets the hardware up to
  5027. * use it whenever needed.
  5028. */
  5029. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5030. {
  5031. struct iwl_priv *priv = hw->priv;
  5032. const struct iwl_channel_info *ch_info;
  5033. struct ieee80211_conf *conf = &hw->conf;
  5034. unsigned long flags;
  5035. int ret = 0;
  5036. mutex_lock(&priv->mutex);
  5037. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5038. if (!iwl_is_ready(priv)) {
  5039. IWL_DEBUG_MAC80211("leave - not ready\n");
  5040. ret = -EIO;
  5041. goto out;
  5042. }
  5043. if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
  5044. test_bit(STATUS_SCANNING, &priv->status))) {
  5045. IWL_DEBUG_MAC80211("leave - scanning\n");
  5046. set_bit(STATUS_CONF_PENDING, &priv->status);
  5047. mutex_unlock(&priv->mutex);
  5048. return 0;
  5049. }
  5050. spin_lock_irqsave(&priv->lock, flags);
  5051. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5052. conf->channel->hw_value);
  5053. if (!is_channel_valid(ch_info)) {
  5054. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5055. conf->channel->hw_value, conf->channel->band);
  5056. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5057. spin_unlock_irqrestore(&priv->lock, flags);
  5058. ret = -EINVAL;
  5059. goto out;
  5060. }
  5061. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5062. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5063. /* The list of supported rates and rate mask can be different
  5064. * for each phymode; since the phymode may have changed, reset
  5065. * the rate mask to what mac80211 lists */
  5066. iwl3945_set_rate(priv);
  5067. spin_unlock_irqrestore(&priv->lock, flags);
  5068. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5069. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5070. iwl3945_hw_channel_switch(priv, conf->channel);
  5071. goto out;
  5072. }
  5073. #endif
  5074. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5075. if (!conf->radio_enabled) {
  5076. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5077. goto out;
  5078. }
  5079. if (iwl_is_rfkill(priv)) {
  5080. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5081. ret = -EIO;
  5082. goto out;
  5083. }
  5084. iwl3945_set_rate(priv);
  5085. if (memcmp(&priv->active39_rxon,
  5086. &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
  5087. iwl3945_commit_rxon(priv);
  5088. else
  5089. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5090. IWL_DEBUG_MAC80211("leave\n");
  5091. out:
  5092. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5093. mutex_unlock(&priv->mutex);
  5094. return ret;
  5095. }
  5096. static void iwl3945_config_ap(struct iwl_priv *priv)
  5097. {
  5098. int rc = 0;
  5099. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5100. return;
  5101. /* The following should be done only at AP bring up */
  5102. if (!(iwl3945_is_associated(priv))) {
  5103. /* RXON - unassoc (to set timing command) */
  5104. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5105. iwl3945_commit_rxon(priv);
  5106. /* RXON Timing */
  5107. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5108. iwl3945_setup_rxon_timing(priv);
  5109. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5110. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5111. if (rc)
  5112. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  5113. "Attempting to continue.\n");
  5114. /* FIXME: what should be the assoc_id for AP? */
  5115. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5116. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5117. priv->staging39_rxon.flags |=
  5118. RXON_FLG_SHORT_PREAMBLE_MSK;
  5119. else
  5120. priv->staging39_rxon.flags &=
  5121. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5122. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5123. if (priv->assoc_capability &
  5124. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5125. priv->staging39_rxon.flags |=
  5126. RXON_FLG_SHORT_SLOT_MSK;
  5127. else
  5128. priv->staging39_rxon.flags &=
  5129. ~RXON_FLG_SHORT_SLOT_MSK;
  5130. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5131. priv->staging39_rxon.flags &=
  5132. ~RXON_FLG_SHORT_SLOT_MSK;
  5133. }
  5134. /* restore RXON assoc */
  5135. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5136. iwl3945_commit_rxon(priv);
  5137. iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
  5138. }
  5139. iwl3945_send_beacon_cmd(priv);
  5140. /* FIXME - we need to add code here to detect a totally new
  5141. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5142. * clear sta table, add BCAST sta... */
  5143. }
  5144. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5145. struct ieee80211_vif *vif,
  5146. struct ieee80211_if_conf *conf)
  5147. {
  5148. struct iwl_priv *priv = hw->priv;
  5149. int rc;
  5150. if (conf == NULL)
  5151. return -EIO;
  5152. if (priv->vif != vif) {
  5153. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5154. return 0;
  5155. }
  5156. /* handle this temporarily here */
  5157. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5158. conf->changed & IEEE80211_IFCC_BEACON) {
  5159. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5160. if (!beacon)
  5161. return -ENOMEM;
  5162. mutex_lock(&priv->mutex);
  5163. rc = iwl3945_mac_beacon_update(hw, beacon);
  5164. mutex_unlock(&priv->mutex);
  5165. if (rc)
  5166. return rc;
  5167. }
  5168. if (!iwl_is_alive(priv))
  5169. return -EAGAIN;
  5170. mutex_lock(&priv->mutex);
  5171. if (conf->bssid)
  5172. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5173. /*
  5174. * very dubious code was here; the probe filtering flag is never set:
  5175. *
  5176. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5177. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5178. */
  5179. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5180. if (!conf->bssid) {
  5181. conf->bssid = priv->mac_addr;
  5182. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5183. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5184. conf->bssid);
  5185. }
  5186. if (priv->ibss_beacon)
  5187. dev_kfree_skb(priv->ibss_beacon);
  5188. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5189. }
  5190. if (iwl_is_rfkill(priv))
  5191. goto done;
  5192. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5193. !is_multicast_ether_addr(conf->bssid)) {
  5194. /* If there is currently a HW scan going on in the background
  5195. * then we need to cancel it else the RXON below will fail. */
  5196. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5197. IWL_WARN(priv, "Aborted scan still in progress "
  5198. "after 100ms\n");
  5199. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5200. mutex_unlock(&priv->mutex);
  5201. return -EAGAIN;
  5202. }
  5203. memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5204. /* TODO: Audit driver for usage of these members and see
  5205. * if mac80211 deprecates them (priv->bssid looks like it
  5206. * shouldn't be there, but I haven't scanned the IBSS code
  5207. * to verify) - jpk */
  5208. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5209. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5210. iwl3945_config_ap(priv);
  5211. else {
  5212. rc = iwl3945_commit_rxon(priv);
  5213. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5214. iwl3945_add_station(priv,
  5215. priv->active39_rxon.bssid_addr, 1, 0);
  5216. }
  5217. } else {
  5218. iwl3945_scan_cancel_timeout(priv, 100);
  5219. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5220. iwl3945_commit_rxon(priv);
  5221. }
  5222. done:
  5223. IWL_DEBUG_MAC80211("leave\n");
  5224. mutex_unlock(&priv->mutex);
  5225. return 0;
  5226. }
  5227. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5228. unsigned int changed_flags,
  5229. unsigned int *total_flags,
  5230. int mc_count, struct dev_addr_list *mc_list)
  5231. {
  5232. struct iwl_priv *priv = hw->priv;
  5233. __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
  5234. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5235. changed_flags, *total_flags);
  5236. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5237. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5238. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5239. else
  5240. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5241. }
  5242. if (changed_flags & FIF_ALLMULTI) {
  5243. if (*total_flags & FIF_ALLMULTI)
  5244. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5245. else
  5246. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5247. }
  5248. if (changed_flags & FIF_CONTROL) {
  5249. if (*total_flags & FIF_CONTROL)
  5250. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5251. else
  5252. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5253. }
  5254. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5255. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5256. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5257. else
  5258. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5259. }
  5260. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5261. * since mac80211 will call ieee80211_hw_config immediately.
  5262. * (mc_list is not supported at this time). Otherwise, we need to
  5263. * queue a background iwl_commit_rxon work.
  5264. */
  5265. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5266. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5267. }
  5268. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5269. struct ieee80211_if_init_conf *conf)
  5270. {
  5271. struct iwl_priv *priv = hw->priv;
  5272. IWL_DEBUG_MAC80211("enter\n");
  5273. mutex_lock(&priv->mutex);
  5274. if (iwl_is_ready_rf(priv)) {
  5275. iwl3945_scan_cancel_timeout(priv, 100);
  5276. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5277. iwl3945_commit_rxon(priv);
  5278. }
  5279. if (priv->vif == conf->vif) {
  5280. priv->vif = NULL;
  5281. memset(priv->bssid, 0, ETH_ALEN);
  5282. }
  5283. mutex_unlock(&priv->mutex);
  5284. IWL_DEBUG_MAC80211("leave\n");
  5285. }
  5286. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5287. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5288. struct ieee80211_vif *vif,
  5289. struct ieee80211_bss_conf *bss_conf,
  5290. u32 changes)
  5291. {
  5292. struct iwl_priv *priv = hw->priv;
  5293. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5294. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5295. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5296. bss_conf->use_short_preamble);
  5297. if (bss_conf->use_short_preamble)
  5298. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5299. else
  5300. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5301. }
  5302. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5303. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5304. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5305. priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5306. else
  5307. priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5308. }
  5309. if (changes & BSS_CHANGED_ASSOC) {
  5310. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5311. /* This should never happen as this function should
  5312. * never be called from interrupt context. */
  5313. if (WARN_ON_ONCE(in_interrupt()))
  5314. return;
  5315. if (bss_conf->assoc) {
  5316. priv->assoc_id = bss_conf->aid;
  5317. priv->beacon_int = bss_conf->beacon_int;
  5318. priv->timestamp = bss_conf->timestamp;
  5319. priv->assoc_capability = bss_conf->assoc_capability;
  5320. priv->next_scan_jiffies = jiffies +
  5321. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5322. mutex_lock(&priv->mutex);
  5323. iwl3945_post_associate(priv);
  5324. mutex_unlock(&priv->mutex);
  5325. } else {
  5326. priv->assoc_id = 0;
  5327. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5328. }
  5329. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5330. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5331. iwl3945_send_rxon_assoc(priv);
  5332. }
  5333. }
  5334. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5335. {
  5336. int rc = 0;
  5337. unsigned long flags;
  5338. struct iwl_priv *priv = hw->priv;
  5339. DECLARE_SSID_BUF(ssid_buf);
  5340. IWL_DEBUG_MAC80211("enter\n");
  5341. mutex_lock(&priv->mutex);
  5342. spin_lock_irqsave(&priv->lock, flags);
  5343. if (!iwl_is_ready_rf(priv)) {
  5344. rc = -EIO;
  5345. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5346. goto out_unlock;
  5347. }
  5348. /* we don't schedule scan within next_scan_jiffies period */
  5349. if (priv->next_scan_jiffies &&
  5350. time_after(priv->next_scan_jiffies, jiffies)) {
  5351. rc = -EAGAIN;
  5352. goto out_unlock;
  5353. }
  5354. /* if we just finished scan ask for delay for a broadcast scan */
  5355. if ((len == 0) && priv->last_scan_jiffies &&
  5356. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5357. jiffies)) {
  5358. rc = -EAGAIN;
  5359. goto out_unlock;
  5360. }
  5361. if (len) {
  5362. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5363. print_ssid(ssid_buf, ssid, len), (int)len);
  5364. priv->one_direct_scan = 1;
  5365. priv->direct_ssid_len = (u8)
  5366. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5367. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5368. } else
  5369. priv->one_direct_scan = 0;
  5370. rc = iwl3945_scan_initiate(priv);
  5371. IWL_DEBUG_MAC80211("leave\n");
  5372. out_unlock:
  5373. spin_unlock_irqrestore(&priv->lock, flags);
  5374. mutex_unlock(&priv->mutex);
  5375. return rc;
  5376. }
  5377. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5378. struct ieee80211_vif *vif,
  5379. struct ieee80211_sta *sta,
  5380. struct ieee80211_key_conf *key)
  5381. {
  5382. struct iwl_priv *priv = hw->priv;
  5383. const u8 *addr;
  5384. int rc = 0;
  5385. u8 sta_id;
  5386. static const u8 bcast_addr[ETH_ALEN] =
  5387. { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  5388. IWL_DEBUG_MAC80211("enter\n");
  5389. if (iwl3945_mod_params.sw_crypto) {
  5390. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5391. return -EOPNOTSUPP;
  5392. }
  5393. addr = sta ? sta->addr : bcast_addr;
  5394. sta_id = iwl3945_hw_find_station(priv, addr);
  5395. if (sta_id == IWL_INVALID_STATION) {
  5396. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5397. addr);
  5398. return -EINVAL;
  5399. }
  5400. mutex_lock(&priv->mutex);
  5401. iwl3945_scan_cancel_timeout(priv, 100);
  5402. switch (cmd) {
  5403. case SET_KEY:
  5404. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5405. if (!rc) {
  5406. iwl3945_set_rxon_hwcrypto(priv, 1);
  5407. iwl3945_commit_rxon(priv);
  5408. key->hw_key_idx = sta_id;
  5409. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5410. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5411. }
  5412. break;
  5413. case DISABLE_KEY:
  5414. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5415. if (!rc) {
  5416. iwl3945_set_rxon_hwcrypto(priv, 0);
  5417. iwl3945_commit_rxon(priv);
  5418. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5419. }
  5420. break;
  5421. default:
  5422. rc = -EINVAL;
  5423. }
  5424. IWL_DEBUG_MAC80211("leave\n");
  5425. mutex_unlock(&priv->mutex);
  5426. return rc;
  5427. }
  5428. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5429. const struct ieee80211_tx_queue_params *params)
  5430. {
  5431. struct iwl_priv *priv = hw->priv;
  5432. unsigned long flags;
  5433. int q;
  5434. IWL_DEBUG_MAC80211("enter\n");
  5435. if (!iwl_is_ready_rf(priv)) {
  5436. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5437. return -EIO;
  5438. }
  5439. if (queue >= AC_NUM) {
  5440. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5441. return 0;
  5442. }
  5443. q = AC_NUM - 1 - queue;
  5444. spin_lock_irqsave(&priv->lock, flags);
  5445. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5446. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5447. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5448. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5449. cpu_to_le16((params->txop * 32));
  5450. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5451. priv->qos_data.qos_active = 1;
  5452. spin_unlock_irqrestore(&priv->lock, flags);
  5453. mutex_lock(&priv->mutex);
  5454. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5455. iwl3945_activate_qos(priv, 1);
  5456. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5457. iwl3945_activate_qos(priv, 0);
  5458. mutex_unlock(&priv->mutex);
  5459. IWL_DEBUG_MAC80211("leave\n");
  5460. return 0;
  5461. }
  5462. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5463. struct ieee80211_tx_queue_stats *stats)
  5464. {
  5465. struct iwl_priv *priv = hw->priv;
  5466. int i, avail;
  5467. struct iwl_tx_queue *txq;
  5468. struct iwl_queue *q;
  5469. unsigned long flags;
  5470. IWL_DEBUG_MAC80211("enter\n");
  5471. if (!iwl_is_ready_rf(priv)) {
  5472. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5473. return -EIO;
  5474. }
  5475. spin_lock_irqsave(&priv->lock, flags);
  5476. for (i = 0; i < AC_NUM; i++) {
  5477. txq = &priv->txq[i];
  5478. q = &txq->q;
  5479. avail = iwl_queue_space(q);
  5480. stats[i].len = q->n_window - avail;
  5481. stats[i].limit = q->n_window - q->high_mark;
  5482. stats[i].count = q->n_window;
  5483. }
  5484. spin_unlock_irqrestore(&priv->lock, flags);
  5485. IWL_DEBUG_MAC80211("leave\n");
  5486. return 0;
  5487. }
  5488. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5489. {
  5490. struct iwl_priv *priv = hw->priv;
  5491. unsigned long flags;
  5492. mutex_lock(&priv->mutex);
  5493. IWL_DEBUG_MAC80211("enter\n");
  5494. iwl_reset_qos(priv);
  5495. spin_lock_irqsave(&priv->lock, flags);
  5496. priv->assoc_id = 0;
  5497. priv->assoc_capability = 0;
  5498. priv->call_post_assoc_from_beacon = 0;
  5499. /* new association get rid of ibss beacon skb */
  5500. if (priv->ibss_beacon)
  5501. dev_kfree_skb(priv->ibss_beacon);
  5502. priv->ibss_beacon = NULL;
  5503. priv->beacon_int = priv->hw->conf.beacon_int;
  5504. priv->timestamp = 0;
  5505. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5506. priv->beacon_int = 0;
  5507. spin_unlock_irqrestore(&priv->lock, flags);
  5508. if (!iwl_is_ready_rf(priv)) {
  5509. IWL_DEBUG_MAC80211("leave - not ready\n");
  5510. mutex_unlock(&priv->mutex);
  5511. return;
  5512. }
  5513. /* we are restarting association process
  5514. * clear RXON_FILTER_ASSOC_MSK bit
  5515. */
  5516. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5517. iwl3945_scan_cancel_timeout(priv, 100);
  5518. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5519. iwl3945_commit_rxon(priv);
  5520. }
  5521. /* Per mac80211.h: This is only used in IBSS mode... */
  5522. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5523. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5524. mutex_unlock(&priv->mutex);
  5525. return;
  5526. }
  5527. iwl3945_set_rate(priv);
  5528. mutex_unlock(&priv->mutex);
  5529. IWL_DEBUG_MAC80211("leave\n");
  5530. }
  5531. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5532. {
  5533. struct iwl_priv *priv = hw->priv;
  5534. unsigned long flags;
  5535. IWL_DEBUG_MAC80211("enter\n");
  5536. if (!iwl_is_ready_rf(priv)) {
  5537. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5538. return -EIO;
  5539. }
  5540. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5541. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5542. return -EIO;
  5543. }
  5544. spin_lock_irqsave(&priv->lock, flags);
  5545. if (priv->ibss_beacon)
  5546. dev_kfree_skb(priv->ibss_beacon);
  5547. priv->ibss_beacon = skb;
  5548. priv->assoc_id = 0;
  5549. IWL_DEBUG_MAC80211("leave\n");
  5550. spin_unlock_irqrestore(&priv->lock, flags);
  5551. iwl_reset_qos(priv);
  5552. iwl3945_post_associate(priv);
  5553. return 0;
  5554. }
  5555. /*****************************************************************************
  5556. *
  5557. * sysfs attributes
  5558. *
  5559. *****************************************************************************/
  5560. #ifdef CONFIG_IWL3945_DEBUG
  5561. /*
  5562. * The following adds a new attribute to the sysfs representation
  5563. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5564. * used for controlling the debug level.
  5565. *
  5566. * See the level definitions in iwl for details.
  5567. */
  5568. static ssize_t show_debug_level(struct device *d,
  5569. struct device_attribute *attr, char *buf)
  5570. {
  5571. struct iwl_priv *priv = d->driver_data;
  5572. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5573. }
  5574. static ssize_t store_debug_level(struct device *d,
  5575. struct device_attribute *attr,
  5576. const char *buf, size_t count)
  5577. {
  5578. struct iwl_priv *priv = d->driver_data;
  5579. unsigned long val;
  5580. int ret;
  5581. ret = strict_strtoul(buf, 0, &val);
  5582. if (ret)
  5583. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  5584. else
  5585. priv->debug_level = val;
  5586. return strnlen(buf, count);
  5587. }
  5588. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5589. show_debug_level, store_debug_level);
  5590. #endif /* CONFIG_IWL3945_DEBUG */
  5591. static ssize_t show_temperature(struct device *d,
  5592. struct device_attribute *attr, char *buf)
  5593. {
  5594. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5595. if (!iwl_is_alive(priv))
  5596. return -EAGAIN;
  5597. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5598. }
  5599. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5600. static ssize_t show_tx_power(struct device *d,
  5601. struct device_attribute *attr, char *buf)
  5602. {
  5603. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5604. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  5605. }
  5606. static ssize_t store_tx_power(struct device *d,
  5607. struct device_attribute *attr,
  5608. const char *buf, size_t count)
  5609. {
  5610. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5611. char *p = (char *)buf;
  5612. u32 val;
  5613. val = simple_strtoul(p, &p, 10);
  5614. if (p == buf)
  5615. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  5616. else
  5617. iwl3945_hw_reg_set_txpower(priv, val);
  5618. return count;
  5619. }
  5620. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5621. static ssize_t show_flags(struct device *d,
  5622. struct device_attribute *attr, char *buf)
  5623. {
  5624. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5625. return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
  5626. }
  5627. static ssize_t store_flags(struct device *d,
  5628. struct device_attribute *attr,
  5629. const char *buf, size_t count)
  5630. {
  5631. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5632. u32 flags = simple_strtoul(buf, NULL, 0);
  5633. mutex_lock(&priv->mutex);
  5634. if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
  5635. /* Cancel any currently running scans... */
  5636. if (iwl3945_scan_cancel_timeout(priv, 100))
  5637. IWL_WARN(priv, "Could not cancel scan.\n");
  5638. else {
  5639. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  5640. flags);
  5641. priv->staging39_rxon.flags = cpu_to_le32(flags);
  5642. iwl3945_commit_rxon(priv);
  5643. }
  5644. }
  5645. mutex_unlock(&priv->mutex);
  5646. return count;
  5647. }
  5648. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  5649. static ssize_t show_filter_flags(struct device *d,
  5650. struct device_attribute *attr, char *buf)
  5651. {
  5652. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5653. return sprintf(buf, "0x%04X\n",
  5654. le32_to_cpu(priv->active39_rxon.filter_flags));
  5655. }
  5656. static ssize_t store_filter_flags(struct device *d,
  5657. struct device_attribute *attr,
  5658. const char *buf, size_t count)
  5659. {
  5660. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5661. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  5662. mutex_lock(&priv->mutex);
  5663. if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
  5664. /* Cancel any currently running scans... */
  5665. if (iwl3945_scan_cancel_timeout(priv, 100))
  5666. IWL_WARN(priv, "Could not cancel scan.\n");
  5667. else {
  5668. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  5669. "0x%04X\n", filter_flags);
  5670. priv->staging39_rxon.filter_flags =
  5671. cpu_to_le32(filter_flags);
  5672. iwl3945_commit_rxon(priv);
  5673. }
  5674. }
  5675. mutex_unlock(&priv->mutex);
  5676. return count;
  5677. }
  5678. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  5679. store_filter_flags);
  5680. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5681. static ssize_t show_measurement(struct device *d,
  5682. struct device_attribute *attr, char *buf)
  5683. {
  5684. struct iwl_priv *priv = dev_get_drvdata(d);
  5685. struct iwl_spectrum_notification measure_report;
  5686. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  5687. u8 *data = (u8 *)&measure_report;
  5688. unsigned long flags;
  5689. spin_lock_irqsave(&priv->lock, flags);
  5690. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  5691. spin_unlock_irqrestore(&priv->lock, flags);
  5692. return 0;
  5693. }
  5694. memcpy(&measure_report, &priv->measure_report, size);
  5695. priv->measurement_status = 0;
  5696. spin_unlock_irqrestore(&priv->lock, flags);
  5697. while (size && (PAGE_SIZE - len)) {
  5698. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5699. PAGE_SIZE - len, 1);
  5700. len = strlen(buf);
  5701. if (PAGE_SIZE - len)
  5702. buf[len++] = '\n';
  5703. ofs += 16;
  5704. size -= min(size, 16U);
  5705. }
  5706. return len;
  5707. }
  5708. static ssize_t store_measurement(struct device *d,
  5709. struct device_attribute *attr,
  5710. const char *buf, size_t count)
  5711. {
  5712. struct iwl_priv *priv = dev_get_drvdata(d);
  5713. struct ieee80211_measurement_params params = {
  5714. .channel = le16_to_cpu(priv->active39_rxon.channel),
  5715. .start_time = cpu_to_le64(priv->last_tsf),
  5716. .duration = cpu_to_le16(1),
  5717. };
  5718. u8 type = IWL_MEASURE_BASIC;
  5719. u8 buffer[32];
  5720. u8 channel;
  5721. if (count) {
  5722. char *p = buffer;
  5723. strncpy(buffer, buf, min(sizeof(buffer), count));
  5724. channel = simple_strtoul(p, NULL, 0);
  5725. if (channel)
  5726. params.channel = channel;
  5727. p = buffer;
  5728. while (*p && *p != ' ')
  5729. p++;
  5730. if (*p)
  5731. type = simple_strtoul(p + 1, NULL, 0);
  5732. }
  5733. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  5734. "channel %d (for '%s')\n", type, params.channel, buf);
  5735. iwl3945_get_measurement(priv, &params, type);
  5736. return count;
  5737. }
  5738. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  5739. show_measurement, store_measurement);
  5740. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  5741. static ssize_t store_retry_rate(struct device *d,
  5742. struct device_attribute *attr,
  5743. const char *buf, size_t count)
  5744. {
  5745. struct iwl_priv *priv = dev_get_drvdata(d);
  5746. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  5747. if (priv->retry_rate <= 0)
  5748. priv->retry_rate = 1;
  5749. return count;
  5750. }
  5751. static ssize_t show_retry_rate(struct device *d,
  5752. struct device_attribute *attr, char *buf)
  5753. {
  5754. struct iwl_priv *priv = dev_get_drvdata(d);
  5755. return sprintf(buf, "%d", priv->retry_rate);
  5756. }
  5757. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  5758. store_retry_rate);
  5759. static ssize_t store_power_level(struct device *d,
  5760. struct device_attribute *attr,
  5761. const char *buf, size_t count)
  5762. {
  5763. struct iwl_priv *priv = dev_get_drvdata(d);
  5764. int rc;
  5765. int mode;
  5766. mode = simple_strtoul(buf, NULL, 0);
  5767. mutex_lock(&priv->mutex);
  5768. if (!iwl_is_ready(priv)) {
  5769. rc = -EAGAIN;
  5770. goto out;
  5771. }
  5772. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  5773. (mode == IWL39_POWER_AC))
  5774. mode = IWL39_POWER_AC;
  5775. else
  5776. mode |= IWL_POWER_ENABLED;
  5777. if (mode != priv->power_mode) {
  5778. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  5779. if (rc) {
  5780. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  5781. goto out;
  5782. }
  5783. priv->power_mode = mode;
  5784. }
  5785. rc = count;
  5786. out:
  5787. mutex_unlock(&priv->mutex);
  5788. return rc;
  5789. }
  5790. #define MAX_WX_STRING 80
  5791. /* Values are in microsecond */
  5792. static const s32 timeout_duration[] = {
  5793. 350000,
  5794. 250000,
  5795. 75000,
  5796. 37000,
  5797. 25000,
  5798. };
  5799. static const s32 period_duration[] = {
  5800. 400000,
  5801. 700000,
  5802. 1000000,
  5803. 1000000,
  5804. 1000000
  5805. };
  5806. static ssize_t show_power_level(struct device *d,
  5807. struct device_attribute *attr, char *buf)
  5808. {
  5809. struct iwl_priv *priv = dev_get_drvdata(d);
  5810. int level = IWL_POWER_LEVEL(priv->power_mode);
  5811. char *p = buf;
  5812. p += sprintf(p, "%d ", level);
  5813. switch (level) {
  5814. case IWL_POWER_MODE_CAM:
  5815. case IWL39_POWER_AC:
  5816. p += sprintf(p, "(AC)");
  5817. break;
  5818. case IWL39_POWER_BATTERY:
  5819. p += sprintf(p, "(BATTERY)");
  5820. break;
  5821. default:
  5822. p += sprintf(p,
  5823. "(Timeout %dms, Period %dms)",
  5824. timeout_duration[level - 1] / 1000,
  5825. period_duration[level - 1] / 1000);
  5826. }
  5827. if (!(priv->power_mode & IWL_POWER_ENABLED))
  5828. p += sprintf(p, " OFF\n");
  5829. else
  5830. p += sprintf(p, " \n");
  5831. return p - buf + 1;
  5832. }
  5833. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  5834. store_power_level);
  5835. static ssize_t show_channels(struct device *d,
  5836. struct device_attribute *attr, char *buf)
  5837. {
  5838. /* all this shit doesn't belong into sysfs anyway */
  5839. return 0;
  5840. }
  5841. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  5842. static ssize_t show_statistics(struct device *d,
  5843. struct device_attribute *attr, char *buf)
  5844. {
  5845. struct iwl_priv *priv = dev_get_drvdata(d);
  5846. u32 size = sizeof(struct iwl3945_notif_statistics);
  5847. u32 len = 0, ofs = 0;
  5848. u8 *data = (u8 *)&priv->statistics_39;
  5849. int rc = 0;
  5850. if (!iwl_is_alive(priv))
  5851. return -EAGAIN;
  5852. mutex_lock(&priv->mutex);
  5853. rc = iwl3945_send_statistics_request(priv);
  5854. mutex_unlock(&priv->mutex);
  5855. if (rc) {
  5856. len = sprintf(buf,
  5857. "Error sending statistics request: 0x%08X\n", rc);
  5858. return len;
  5859. }
  5860. while (size && (PAGE_SIZE - len)) {
  5861. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5862. PAGE_SIZE - len, 1);
  5863. len = strlen(buf);
  5864. if (PAGE_SIZE - len)
  5865. buf[len++] = '\n';
  5866. ofs += 16;
  5867. size -= min(size, 16U);
  5868. }
  5869. return len;
  5870. }
  5871. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  5872. static ssize_t show_antenna(struct device *d,
  5873. struct device_attribute *attr, char *buf)
  5874. {
  5875. struct iwl_priv *priv = dev_get_drvdata(d);
  5876. if (!iwl_is_alive(priv))
  5877. return -EAGAIN;
  5878. return sprintf(buf, "%d\n", priv->antenna);
  5879. }
  5880. static ssize_t store_antenna(struct device *d,
  5881. struct device_attribute *attr,
  5882. const char *buf, size_t count)
  5883. {
  5884. int ant;
  5885. struct iwl_priv *priv = dev_get_drvdata(d);
  5886. if (count == 0)
  5887. return 0;
  5888. if (sscanf(buf, "%1i", &ant) != 1) {
  5889. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  5890. return count;
  5891. }
  5892. if ((ant >= 0) && (ant <= 2)) {
  5893. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  5894. priv->antenna = (enum iwl3945_antenna)ant;
  5895. } else
  5896. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  5897. return count;
  5898. }
  5899. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  5900. static ssize_t show_status(struct device *d,
  5901. struct device_attribute *attr, char *buf)
  5902. {
  5903. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5904. if (!iwl_is_alive(priv))
  5905. return -EAGAIN;
  5906. return sprintf(buf, "0x%08x\n", (int)priv->status);
  5907. }
  5908. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  5909. static ssize_t dump_error_log(struct device *d,
  5910. struct device_attribute *attr,
  5911. const char *buf, size_t count)
  5912. {
  5913. char *p = (char *)buf;
  5914. if (p[0] == '1')
  5915. iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
  5916. return strnlen(buf, count);
  5917. }
  5918. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  5919. static ssize_t dump_event_log(struct device *d,
  5920. struct device_attribute *attr,
  5921. const char *buf, size_t count)
  5922. {
  5923. char *p = (char *)buf;
  5924. if (p[0] == '1')
  5925. iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
  5926. return strnlen(buf, count);
  5927. }
  5928. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  5929. /*****************************************************************************
  5930. *
  5931. * driver setup and tear down
  5932. *
  5933. *****************************************************************************/
  5934. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  5935. {
  5936. priv->workqueue = create_workqueue(DRV_NAME);
  5937. init_waitqueue_head(&priv->wait_command_queue);
  5938. INIT_WORK(&priv->up, iwl3945_bg_up);
  5939. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  5940. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  5941. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  5942. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  5943. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  5944. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  5945. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  5946. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  5947. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  5948. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  5949. INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
  5950. iwl3945_hw_setup_deferred_work(priv);
  5951. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  5952. iwl3945_irq_tasklet, (unsigned long)priv);
  5953. }
  5954. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  5955. {
  5956. iwl3945_hw_cancel_deferred_work(priv);
  5957. cancel_delayed_work_sync(&priv->init_alive_start);
  5958. cancel_delayed_work(&priv->scan_check);
  5959. cancel_delayed_work(&priv->alive_start);
  5960. cancel_work_sync(&priv->beacon_update);
  5961. }
  5962. static struct attribute *iwl3945_sysfs_entries[] = {
  5963. &dev_attr_antenna.attr,
  5964. &dev_attr_channels.attr,
  5965. &dev_attr_dump_errors.attr,
  5966. &dev_attr_dump_events.attr,
  5967. &dev_attr_flags.attr,
  5968. &dev_attr_filter_flags.attr,
  5969. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5970. &dev_attr_measurement.attr,
  5971. #endif
  5972. &dev_attr_power_level.attr,
  5973. &dev_attr_retry_rate.attr,
  5974. &dev_attr_statistics.attr,
  5975. &dev_attr_status.attr,
  5976. &dev_attr_temperature.attr,
  5977. &dev_attr_tx_power.attr,
  5978. #ifdef CONFIG_IWL3945_DEBUG
  5979. &dev_attr_debug_level.attr,
  5980. #endif
  5981. NULL
  5982. };
  5983. static struct attribute_group iwl3945_attribute_group = {
  5984. .name = NULL, /* put in device directory */
  5985. .attrs = iwl3945_sysfs_entries,
  5986. };
  5987. static struct ieee80211_ops iwl3945_hw_ops = {
  5988. .tx = iwl3945_mac_tx,
  5989. .start = iwl3945_mac_start,
  5990. .stop = iwl3945_mac_stop,
  5991. .add_interface = iwl3945_mac_add_interface,
  5992. .remove_interface = iwl3945_mac_remove_interface,
  5993. .config = iwl3945_mac_config,
  5994. .config_interface = iwl3945_mac_config_interface,
  5995. .configure_filter = iwl3945_configure_filter,
  5996. .set_key = iwl3945_mac_set_key,
  5997. .get_tx_stats = iwl3945_mac_get_tx_stats,
  5998. .conf_tx = iwl3945_mac_conf_tx,
  5999. .reset_tsf = iwl3945_mac_reset_tsf,
  6000. .bss_info_changed = iwl3945_bss_info_changed,
  6001. .hw_scan = iwl3945_mac_hw_scan
  6002. };
  6003. static int iwl3945_init_drv(struct iwl_priv *priv)
  6004. {
  6005. int ret;
  6006. priv->retry_rate = 1;
  6007. priv->ibss_beacon = NULL;
  6008. spin_lock_init(&priv->lock);
  6009. spin_lock_init(&priv->power_data_39.lock);
  6010. spin_lock_init(&priv->sta_lock);
  6011. spin_lock_init(&priv->hcmd_lock);
  6012. INIT_LIST_HEAD(&priv->free_frames);
  6013. mutex_init(&priv->mutex);
  6014. /* Clear the driver's (not device's) station table */
  6015. iwl3945_clear_stations_table(priv);
  6016. priv->data_retry_limit = -1;
  6017. priv->ieee_channels = NULL;
  6018. priv->ieee_rates = NULL;
  6019. priv->band = IEEE80211_BAND_2GHZ;
  6020. priv->iw_mode = NL80211_IFTYPE_STATION;
  6021. iwl_reset_qos(priv);
  6022. priv->qos_data.qos_active = 0;
  6023. priv->qos_data.qos_cap.val = 0;
  6024. priv->rates_mask = IWL_RATES_MASK;
  6025. /* If power management is turned on, default to AC mode */
  6026. priv->power_mode = IWL39_POWER_AC;
  6027. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6028. ret = iwl3945_init_channel_map(priv);
  6029. if (ret) {
  6030. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  6031. goto err;
  6032. }
  6033. ret = iwl3945_init_geos(priv);
  6034. if (ret) {
  6035. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  6036. goto err_free_channel_map;
  6037. }
  6038. return 0;
  6039. err_free_channel_map:
  6040. iwl3945_free_channel_map(priv);
  6041. err:
  6042. return ret;
  6043. }
  6044. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6045. {
  6046. int err = 0;
  6047. struct iwl_priv *priv;
  6048. struct ieee80211_hw *hw;
  6049. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  6050. unsigned long flags;
  6051. /***********************
  6052. * 1. Allocating HW data
  6053. * ********************/
  6054. /* mac80211 allocates memory for this device instance, including
  6055. * space for this driver's private structure */
  6056. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  6057. if (hw == NULL) {
  6058. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6059. err = -ENOMEM;
  6060. goto out;
  6061. }
  6062. priv = hw->priv;
  6063. SET_IEEE80211_DEV(hw, &pdev->dev);
  6064. if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
  6065. (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
  6066. IWL_ERR(priv,
  6067. "invalid queues_num, should be between %d and %d\n",
  6068. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6069. err = -EINVAL;
  6070. goto out;
  6071. }
  6072. /*
  6073. * Disabling hardware scan means that mac80211 will perform scans
  6074. * "the hard way", rather than using device's scan.
  6075. */
  6076. if (iwl3945_mod_params.disable_hw_scan) {
  6077. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6078. iwl3945_hw_ops.hw_scan = NULL;
  6079. }
  6080. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6081. priv->cfg = cfg;
  6082. priv->pci_dev = pdev;
  6083. #ifdef CONFIG_IWL3945_DEBUG
  6084. priv->debug_level = iwl3945_mod_params.debug;
  6085. atomic_set(&priv->restrict_refcnt, 0);
  6086. #endif
  6087. hw->rate_control_algorithm = "iwl-3945-rs";
  6088. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6089. /* Select antenna (may be helpful if only one antenna is connected) */
  6090. priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
  6091. /* Tell mac80211 our characteristics */
  6092. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6093. IEEE80211_HW_NOISE_DBM;
  6094. hw->wiphy->interface_modes =
  6095. BIT(NL80211_IFTYPE_STATION) |
  6096. BIT(NL80211_IFTYPE_ADHOC);
  6097. hw->wiphy->fw_handles_regulatory = true;
  6098. /* 4 EDCA QOS priorities */
  6099. hw->queues = 4;
  6100. /***************************
  6101. * 2. Initializing PCI bus
  6102. * *************************/
  6103. if (pci_enable_device(pdev)) {
  6104. err = -ENODEV;
  6105. goto out_ieee80211_free_hw;
  6106. }
  6107. pci_set_master(pdev);
  6108. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6109. if (!err)
  6110. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6111. if (err) {
  6112. IWL_WARN(priv, "No suitable DMA available.\n");
  6113. goto out_pci_disable_device;
  6114. }
  6115. pci_set_drvdata(pdev, priv);
  6116. err = pci_request_regions(pdev, DRV_NAME);
  6117. if (err)
  6118. goto out_pci_disable_device;
  6119. /***********************
  6120. * 3. Read REV Register
  6121. * ********************/
  6122. priv->hw_base = pci_iomap(pdev, 0, 0);
  6123. if (!priv->hw_base) {
  6124. err = -ENODEV;
  6125. goto out_pci_release_regions;
  6126. }
  6127. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6128. (unsigned long long) pci_resource_len(pdev, 0));
  6129. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6130. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6131. * PCI Tx retries from interfering with C3 CPU state */
  6132. pci_write_config_byte(pdev, 0x41, 0x00);
  6133. /* amp init */
  6134. err = priv->cfg->ops->lib->apm_ops.init(priv);
  6135. if (err < 0) {
  6136. IWL_DEBUG_INFO("Failed to init APMG\n");
  6137. goto out_iounmap;
  6138. }
  6139. /***********************
  6140. * 4. Read EEPROM
  6141. * ********************/
  6142. /* Read the EEPROM */
  6143. err = iwl3945_eeprom_init(priv);
  6144. if (err) {
  6145. IWL_ERR(priv, "Unable to init EEPROM\n");
  6146. goto out_remove_sysfs;
  6147. }
  6148. /* MAC Address location in EEPROM same for 3945/4965 */
  6149. get_eeprom_mac(priv, priv->mac_addr);
  6150. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6151. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6152. /***********************
  6153. * 5. Setup HW Constants
  6154. * ********************/
  6155. /* Device-specific setup */
  6156. if (iwl3945_hw_set_hw_params(priv)) {
  6157. IWL_ERR(priv, "failed to set hw settings\n");
  6158. goto out_iounmap;
  6159. }
  6160. /***********************
  6161. * 6. Setup priv
  6162. * ********************/
  6163. err = iwl3945_init_drv(priv);
  6164. if (err) {
  6165. IWL_ERR(priv, "initializing driver failed\n");
  6166. goto out_free_geos;
  6167. }
  6168. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  6169. priv->cfg->name);
  6170. /***********************************
  6171. * 7. Initialize Module Parameters
  6172. * **********************************/
  6173. /* Initialize module parameter values here */
  6174. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6175. if (iwl3945_mod_params.disable) {
  6176. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6177. IWL_DEBUG_INFO("Radio disabled.\n");
  6178. }
  6179. /***********************
  6180. * 8. Setup Services
  6181. * ********************/
  6182. spin_lock_irqsave(&priv->lock, flags);
  6183. iwl3945_disable_interrupts(priv);
  6184. spin_unlock_irqrestore(&priv->lock, flags);
  6185. pci_enable_msi(priv->pci_dev);
  6186. err = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  6187. DRV_NAME, priv);
  6188. if (err) {
  6189. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  6190. goto out_disable_msi;
  6191. }
  6192. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6193. if (err) {
  6194. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  6195. goto out_release_irq;
  6196. }
  6197. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6198. iwl3945_setup_deferred_work(priv);
  6199. iwl3945_setup_rx_handlers(priv);
  6200. /*********************************
  6201. * 9. Setup and Register mac80211
  6202. * *******************************/
  6203. err = ieee80211_register_hw(priv->hw);
  6204. if (err) {
  6205. IWL_ERR(priv, "Failed to register network device: %d\n", err);
  6206. goto out_remove_sysfs;
  6207. }
  6208. priv->hw->conf.beacon_int = 100;
  6209. priv->mac80211_registered = 1;
  6210. err = iwl3945_rfkill_init(priv);
  6211. if (err)
  6212. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  6213. "Ignoring error: %d\n", err);
  6214. /* Start monitoring the killswitch */
  6215. queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
  6216. 2 * HZ);
  6217. return 0;
  6218. out_remove_sysfs:
  6219. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6220. out_free_geos:
  6221. iwl3945_free_geos(priv);
  6222. out_release_irq:
  6223. free_irq(priv->pci_dev->irq, priv);
  6224. destroy_workqueue(priv->workqueue);
  6225. priv->workqueue = NULL;
  6226. iwl3945_unset_hw_params(priv);
  6227. out_disable_msi:
  6228. pci_disable_msi(priv->pci_dev);
  6229. out_iounmap:
  6230. pci_iounmap(pdev, priv->hw_base);
  6231. out_pci_release_regions:
  6232. pci_release_regions(pdev);
  6233. out_pci_disable_device:
  6234. pci_disable_device(pdev);
  6235. pci_set_drvdata(pdev, NULL);
  6236. out_ieee80211_free_hw:
  6237. ieee80211_free_hw(priv->hw);
  6238. out:
  6239. return err;
  6240. }
  6241. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6242. {
  6243. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6244. unsigned long flags;
  6245. if (!priv)
  6246. return;
  6247. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6248. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6249. if (priv->mac80211_registered) {
  6250. ieee80211_unregister_hw(priv->hw);
  6251. priv->mac80211_registered = 0;
  6252. } else {
  6253. iwl3945_down(priv);
  6254. }
  6255. /* make sure we flush any pending irq or
  6256. * tasklet for the driver
  6257. */
  6258. spin_lock_irqsave(&priv->lock, flags);
  6259. iwl3945_disable_interrupts(priv);
  6260. spin_unlock_irqrestore(&priv->lock, flags);
  6261. iwl_synchronize_irq(priv);
  6262. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6263. iwl3945_rfkill_unregister(priv);
  6264. cancel_delayed_work(&priv->rfkill_poll);
  6265. iwl3945_dealloc_ucode_pci(priv);
  6266. if (priv->rxq.bd)
  6267. iwl_rx_queue_free(priv, &priv->rxq);
  6268. iwl3945_hw_txq_ctx_free(priv);
  6269. iwl3945_unset_hw_params(priv);
  6270. iwl3945_clear_stations_table(priv);
  6271. /*netif_stop_queue(dev); */
  6272. flush_workqueue(priv->workqueue);
  6273. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6274. * priv->workqueue... so we can't take down the workqueue
  6275. * until now... */
  6276. destroy_workqueue(priv->workqueue);
  6277. priv->workqueue = NULL;
  6278. free_irq(pdev->irq, priv);
  6279. pci_disable_msi(pdev);
  6280. pci_iounmap(pdev, priv->hw_base);
  6281. pci_release_regions(pdev);
  6282. pci_disable_device(pdev);
  6283. pci_set_drvdata(pdev, NULL);
  6284. iwl3945_free_channel_map(priv);
  6285. iwl3945_free_geos(priv);
  6286. kfree(priv->scan39);
  6287. if (priv->ibss_beacon)
  6288. dev_kfree_skb(priv->ibss_beacon);
  6289. ieee80211_free_hw(priv->hw);
  6290. }
  6291. #ifdef CONFIG_PM
  6292. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6293. {
  6294. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6295. if (priv->is_open) {
  6296. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6297. iwl3945_mac_stop(priv->hw);
  6298. priv->is_open = 1;
  6299. }
  6300. pci_save_state(pdev);
  6301. pci_disable_device(pdev);
  6302. pci_set_power_state(pdev, PCI_D3hot);
  6303. return 0;
  6304. }
  6305. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6306. {
  6307. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6308. pci_set_power_state(pdev, PCI_D0);
  6309. pci_enable_device(pdev);
  6310. pci_restore_state(pdev);
  6311. if (priv->is_open)
  6312. iwl3945_mac_start(priv->hw);
  6313. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6314. return 0;
  6315. }
  6316. #endif /* CONFIG_PM */
  6317. /*************** RFKILL FUNCTIONS **********/
  6318. #ifdef CONFIG_IWL3945_RFKILL
  6319. /* software rf-kill from user */
  6320. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6321. {
  6322. struct iwl_priv *priv = data;
  6323. int err = 0;
  6324. if (!priv->rfkill)
  6325. return 0;
  6326. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6327. return 0;
  6328. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6329. mutex_lock(&priv->mutex);
  6330. switch (state) {
  6331. case RFKILL_STATE_UNBLOCKED:
  6332. if (iwl_is_rfkill_hw(priv)) {
  6333. err = -EBUSY;
  6334. goto out_unlock;
  6335. }
  6336. iwl3945_radio_kill_sw(priv, 0);
  6337. break;
  6338. case RFKILL_STATE_SOFT_BLOCKED:
  6339. iwl3945_radio_kill_sw(priv, 1);
  6340. break;
  6341. default:
  6342. IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
  6343. break;
  6344. }
  6345. out_unlock:
  6346. mutex_unlock(&priv->mutex);
  6347. return err;
  6348. }
  6349. int iwl3945_rfkill_init(struct iwl_priv *priv)
  6350. {
  6351. struct device *device = wiphy_dev(priv->hw->wiphy);
  6352. int ret = 0;
  6353. BUG_ON(device == NULL);
  6354. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6355. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6356. if (!priv->rfkill) {
  6357. IWL_ERR(priv, "Unable to allocate rfkill device.\n");
  6358. ret = -ENOMEM;
  6359. goto error;
  6360. }
  6361. priv->rfkill->name = priv->cfg->name;
  6362. priv->rfkill->data = priv;
  6363. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6364. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6365. priv->rfkill->user_claim_unsupported = 1;
  6366. priv->rfkill->dev.class->suspend = NULL;
  6367. priv->rfkill->dev.class->resume = NULL;
  6368. ret = rfkill_register(priv->rfkill);
  6369. if (ret) {
  6370. IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
  6371. goto freed_rfkill;
  6372. }
  6373. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6374. return ret;
  6375. freed_rfkill:
  6376. if (priv->rfkill != NULL)
  6377. rfkill_free(priv->rfkill);
  6378. priv->rfkill = NULL;
  6379. error:
  6380. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6381. return ret;
  6382. }
  6383. void iwl3945_rfkill_unregister(struct iwl_priv *priv)
  6384. {
  6385. if (priv->rfkill)
  6386. rfkill_unregister(priv->rfkill);
  6387. priv->rfkill = NULL;
  6388. }
  6389. /* set rf-kill to the right state. */
  6390. void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
  6391. {
  6392. if (!priv->rfkill)
  6393. return;
  6394. if (iwl_is_rfkill_hw(priv)) {
  6395. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6396. return;
  6397. }
  6398. if (!iwl_is_rfkill_sw(priv))
  6399. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6400. else
  6401. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6402. }
  6403. #endif
  6404. /*****************************************************************************
  6405. *
  6406. * driver and module entry point
  6407. *
  6408. *****************************************************************************/
  6409. static struct pci_driver iwl3945_driver = {
  6410. .name = DRV_NAME,
  6411. .id_table = iwl3945_hw_card_ids,
  6412. .probe = iwl3945_pci_probe,
  6413. .remove = __devexit_p(iwl3945_pci_remove),
  6414. #ifdef CONFIG_PM
  6415. .suspend = iwl3945_pci_suspend,
  6416. .resume = iwl3945_pci_resume,
  6417. #endif
  6418. };
  6419. static int __init iwl3945_init(void)
  6420. {
  6421. int ret;
  6422. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6423. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6424. ret = iwl3945_rate_control_register();
  6425. if (ret) {
  6426. printk(KERN_ERR DRV_NAME
  6427. "Unable to register rate control algorithm: %d\n", ret);
  6428. return ret;
  6429. }
  6430. ret = pci_register_driver(&iwl3945_driver);
  6431. if (ret) {
  6432. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6433. goto error_register;
  6434. }
  6435. return ret;
  6436. error_register:
  6437. iwl3945_rate_control_unregister();
  6438. return ret;
  6439. }
  6440. static void __exit iwl3945_exit(void)
  6441. {
  6442. pci_unregister_driver(&iwl3945_driver);
  6443. iwl3945_rate_control_unregister();
  6444. }
  6445. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6446. module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
  6447. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6448. module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
  6449. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6450. module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
  6451. MODULE_PARM_DESC(swcrypto,
  6452. "using software crypto (default 1 [software])\n");
  6453. module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
  6454. MODULE_PARM_DESC(debug, "debug output mask");
  6455. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
  6456. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6457. module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
  6458. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6459. module_exit(iwl3945_exit);
  6460. module_init(iwl3945_init);