therm_throt.c 15 KB

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  1. /*
  2. * Thermal throttle event support code (such as syslog messaging and rate
  3. * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
  4. *
  5. * This allows consistent reporting of CPU thermal throttle events.
  6. *
  7. * Maintains a counter in /sys that keeps track of the number of thermal
  8. * events, such that the user knows how bad the thermal problem might be
  9. * (since the logging to syslog and mcelog is rate limited).
  10. *
  11. * Author: Dmitriy Zavin (dmitriyz@google.com)
  12. *
  13. * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
  14. * Inspired by Ross Biro's and Al Borchers' counter code.
  15. */
  16. #include <linux/interrupt.h>
  17. #include <linux/notifier.h>
  18. #include <linux/jiffies.h>
  19. #include <linux/kernel.h>
  20. #include <linux/percpu.h>
  21. #include <linux/export.h>
  22. #include <linux/types.h>
  23. #include <linux/init.h>
  24. #include <linux/smp.h>
  25. #include <linux/cpu.h>
  26. #include <asm/processor.h>
  27. #include <asm/apic.h>
  28. #include <asm/idle.h>
  29. #include <asm/mce.h>
  30. #include <asm/msr.h>
  31. /* How long to wait between reporting thermal events */
  32. #define CHECK_INTERVAL (300 * HZ)
  33. #define THERMAL_THROTTLING_EVENT 0
  34. #define POWER_LIMIT_EVENT 1
  35. /*
  36. * Current thermal event state:
  37. */
  38. struct _thermal_state {
  39. bool new_event;
  40. int event;
  41. u64 next_check;
  42. unsigned long count;
  43. unsigned long last_count;
  44. };
  45. struct thermal_state {
  46. struct _thermal_state core_throttle;
  47. struct _thermal_state core_power_limit;
  48. struct _thermal_state package_throttle;
  49. struct _thermal_state package_power_limit;
  50. struct _thermal_state core_thresh0;
  51. struct _thermal_state core_thresh1;
  52. struct _thermal_state pkg_thresh0;
  53. struct _thermal_state pkg_thresh1;
  54. };
  55. /* Callback to handle core threshold interrupts */
  56. int (*platform_thermal_notify)(__u64 msr_val);
  57. EXPORT_SYMBOL(platform_thermal_notify);
  58. /* Callback to handle core package threshold_interrupts */
  59. int (*platform_thermal_package_notify)(__u64 msr_val);
  60. EXPORT_SYMBOL_GPL(platform_thermal_package_notify);
  61. /* Callback support of rate control, return true, if
  62. * callback has rate control */
  63. bool (*platform_thermal_package_rate_control)(void);
  64. EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);
  65. static DEFINE_PER_CPU(struct thermal_state, thermal_state);
  66. static atomic_t therm_throt_en = ATOMIC_INIT(0);
  67. static u32 lvtthmr_init __read_mostly;
  68. #ifdef CONFIG_SYSFS
  69. #define define_therm_throt_device_one_ro(_name) \
  70. static DEVICE_ATTR(_name, 0444, \
  71. therm_throt_device_show_##_name, \
  72. NULL) \
  73. #define define_therm_throt_device_show_func(event, name) \
  74. \
  75. static ssize_t therm_throt_device_show_##event##_##name( \
  76. struct device *dev, \
  77. struct device_attribute *attr, \
  78. char *buf) \
  79. { \
  80. unsigned int cpu = dev->id; \
  81. ssize_t ret; \
  82. \
  83. preempt_disable(); /* CPU hotplug */ \
  84. if (cpu_online(cpu)) { \
  85. ret = sprintf(buf, "%lu\n", \
  86. per_cpu(thermal_state, cpu).event.name); \
  87. } else \
  88. ret = 0; \
  89. preempt_enable(); \
  90. \
  91. return ret; \
  92. }
  93. define_therm_throt_device_show_func(core_throttle, count);
  94. define_therm_throt_device_one_ro(core_throttle_count);
  95. define_therm_throt_device_show_func(core_power_limit, count);
  96. define_therm_throt_device_one_ro(core_power_limit_count);
  97. define_therm_throt_device_show_func(package_throttle, count);
  98. define_therm_throt_device_one_ro(package_throttle_count);
  99. define_therm_throt_device_show_func(package_power_limit, count);
  100. define_therm_throt_device_one_ro(package_power_limit_count);
  101. static struct attribute *thermal_throttle_attrs[] = {
  102. &dev_attr_core_throttle_count.attr,
  103. NULL
  104. };
  105. static struct attribute_group thermal_attr_group = {
  106. .attrs = thermal_throttle_attrs,
  107. .name = "thermal_throttle"
  108. };
  109. #endif /* CONFIG_SYSFS */
  110. #define CORE_LEVEL 0
  111. #define PACKAGE_LEVEL 1
  112. /***
  113. * therm_throt_process - Process thermal throttling event from interrupt
  114. * @curr: Whether the condition is current or not (boolean), since the
  115. * thermal interrupt normally gets called both when the thermal
  116. * event begins and once the event has ended.
  117. *
  118. * This function is called by the thermal interrupt after the
  119. * IRQ has been acknowledged.
  120. *
  121. * It will take care of rate limiting and printing messages to the syslog.
  122. *
  123. * Returns: 0 : Event should NOT be further logged, i.e. still in
  124. * "timeout" from previous log message.
  125. * 1 : Event should be logged further, and a message has been
  126. * printed to the syslog.
  127. */
  128. static int therm_throt_process(bool new_event, int event, int level)
  129. {
  130. struct _thermal_state *state;
  131. unsigned int this_cpu = smp_processor_id();
  132. bool old_event;
  133. u64 now;
  134. struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
  135. now = get_jiffies_64();
  136. if (level == CORE_LEVEL) {
  137. if (event == THERMAL_THROTTLING_EVENT)
  138. state = &pstate->core_throttle;
  139. else if (event == POWER_LIMIT_EVENT)
  140. state = &pstate->core_power_limit;
  141. else
  142. return 0;
  143. } else if (level == PACKAGE_LEVEL) {
  144. if (event == THERMAL_THROTTLING_EVENT)
  145. state = &pstate->package_throttle;
  146. else if (event == POWER_LIMIT_EVENT)
  147. state = &pstate->package_power_limit;
  148. else
  149. return 0;
  150. } else
  151. return 0;
  152. old_event = state->new_event;
  153. state->new_event = new_event;
  154. if (new_event)
  155. state->count++;
  156. if (time_before64(now, state->next_check) &&
  157. state->count != state->last_count)
  158. return 0;
  159. state->next_check = now + CHECK_INTERVAL;
  160. state->last_count = state->count;
  161. /* if we just entered the thermal event */
  162. if (new_event) {
  163. if (event == THERMAL_THROTTLING_EVENT)
  164. printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
  165. this_cpu,
  166. level == CORE_LEVEL ? "Core" : "Package",
  167. state->count);
  168. else
  169. printk(KERN_CRIT "CPU%d: %s power limit notification (total events = %lu)\n",
  170. this_cpu,
  171. level == CORE_LEVEL ? "Core" : "Package",
  172. state->count);
  173. return 1;
  174. }
  175. if (old_event) {
  176. if (event == THERMAL_THROTTLING_EVENT)
  177. printk(KERN_INFO "CPU%d: %s temperature/speed normal\n",
  178. this_cpu,
  179. level == CORE_LEVEL ? "Core" : "Package");
  180. else
  181. printk(KERN_INFO "CPU%d: %s power limit normal\n",
  182. this_cpu,
  183. level == CORE_LEVEL ? "Core" : "Package");
  184. return 1;
  185. }
  186. return 0;
  187. }
  188. static int thresh_event_valid(int level, int event)
  189. {
  190. struct _thermal_state *state;
  191. unsigned int this_cpu = smp_processor_id();
  192. struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
  193. u64 now = get_jiffies_64();
  194. if (level == PACKAGE_LEVEL)
  195. state = (event == 0) ? &pstate->pkg_thresh0 :
  196. &pstate->pkg_thresh1;
  197. else
  198. state = (event == 0) ? &pstate->core_thresh0 :
  199. &pstate->core_thresh1;
  200. if (time_before64(now, state->next_check))
  201. return 0;
  202. state->next_check = now + CHECK_INTERVAL;
  203. return 1;
  204. }
  205. #ifdef CONFIG_SYSFS
  206. /* Add/Remove thermal_throttle interface for CPU device: */
  207. static __cpuinit int thermal_throttle_add_dev(struct device *dev,
  208. unsigned int cpu)
  209. {
  210. int err;
  211. struct cpuinfo_x86 *c = &cpu_data(cpu);
  212. err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
  213. if (err)
  214. return err;
  215. if (cpu_has(c, X86_FEATURE_PLN))
  216. err = sysfs_add_file_to_group(&dev->kobj,
  217. &dev_attr_core_power_limit_count.attr,
  218. thermal_attr_group.name);
  219. if (cpu_has(c, X86_FEATURE_PTS)) {
  220. err = sysfs_add_file_to_group(&dev->kobj,
  221. &dev_attr_package_throttle_count.attr,
  222. thermal_attr_group.name);
  223. if (cpu_has(c, X86_FEATURE_PLN))
  224. err = sysfs_add_file_to_group(&dev->kobj,
  225. &dev_attr_package_power_limit_count.attr,
  226. thermal_attr_group.name);
  227. }
  228. return err;
  229. }
  230. static __cpuinit void thermal_throttle_remove_dev(struct device *dev)
  231. {
  232. sysfs_remove_group(&dev->kobj, &thermal_attr_group);
  233. }
  234. /* Mutex protecting device creation against CPU hotplug: */
  235. static DEFINE_MUTEX(therm_cpu_lock);
  236. /* Get notified when a cpu comes on/off. Be hotplug friendly. */
  237. static __cpuinit int
  238. thermal_throttle_cpu_callback(struct notifier_block *nfb,
  239. unsigned long action,
  240. void *hcpu)
  241. {
  242. unsigned int cpu = (unsigned long)hcpu;
  243. struct device *dev;
  244. int err = 0;
  245. dev = get_cpu_device(cpu);
  246. switch (action) {
  247. case CPU_UP_PREPARE:
  248. case CPU_UP_PREPARE_FROZEN:
  249. mutex_lock(&therm_cpu_lock);
  250. err = thermal_throttle_add_dev(dev, cpu);
  251. mutex_unlock(&therm_cpu_lock);
  252. WARN_ON(err);
  253. break;
  254. case CPU_UP_CANCELED:
  255. case CPU_UP_CANCELED_FROZEN:
  256. case CPU_DEAD:
  257. case CPU_DEAD_FROZEN:
  258. mutex_lock(&therm_cpu_lock);
  259. thermal_throttle_remove_dev(dev);
  260. mutex_unlock(&therm_cpu_lock);
  261. break;
  262. }
  263. return notifier_from_errno(err);
  264. }
  265. static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata =
  266. {
  267. .notifier_call = thermal_throttle_cpu_callback,
  268. };
  269. static __init int thermal_throttle_init_device(void)
  270. {
  271. unsigned int cpu = 0;
  272. int err;
  273. if (!atomic_read(&therm_throt_en))
  274. return 0;
  275. register_hotcpu_notifier(&thermal_throttle_cpu_notifier);
  276. #ifdef CONFIG_HOTPLUG_CPU
  277. mutex_lock(&therm_cpu_lock);
  278. #endif
  279. /* connect live CPUs to sysfs */
  280. for_each_online_cpu(cpu) {
  281. err = thermal_throttle_add_dev(get_cpu_device(cpu), cpu);
  282. WARN_ON(err);
  283. }
  284. #ifdef CONFIG_HOTPLUG_CPU
  285. mutex_unlock(&therm_cpu_lock);
  286. #endif
  287. return 0;
  288. }
  289. device_initcall(thermal_throttle_init_device);
  290. #endif /* CONFIG_SYSFS */
  291. static void notify_package_thresholds(__u64 msr_val)
  292. {
  293. bool notify_thres_0 = false;
  294. bool notify_thres_1 = false;
  295. if (!platform_thermal_package_notify)
  296. return;
  297. /* lower threshold check */
  298. if (msr_val & THERM_LOG_THRESHOLD0)
  299. notify_thres_0 = true;
  300. /* higher threshold check */
  301. if (msr_val & THERM_LOG_THRESHOLD1)
  302. notify_thres_1 = true;
  303. if (!notify_thres_0 && !notify_thres_1)
  304. return;
  305. if (platform_thermal_package_rate_control &&
  306. platform_thermal_package_rate_control()) {
  307. /* Rate control is implemented in callback */
  308. platform_thermal_package_notify(msr_val);
  309. return;
  310. }
  311. /* lower threshold reached */
  312. if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
  313. platform_thermal_package_notify(msr_val);
  314. /* higher threshold reached */
  315. if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
  316. platform_thermal_package_notify(msr_val);
  317. }
  318. static void notify_thresholds(__u64 msr_val)
  319. {
  320. /* check whether the interrupt handler is defined;
  321. * otherwise simply return
  322. */
  323. if (!platform_thermal_notify)
  324. return;
  325. /* lower threshold reached */
  326. if ((msr_val & THERM_LOG_THRESHOLD0) &&
  327. thresh_event_valid(CORE_LEVEL, 0))
  328. platform_thermal_notify(msr_val);
  329. /* higher threshold reached */
  330. if ((msr_val & THERM_LOG_THRESHOLD1) &&
  331. thresh_event_valid(CORE_LEVEL, 1))
  332. platform_thermal_notify(msr_val);
  333. }
  334. /* Thermal transition interrupt handler */
  335. static void intel_thermal_interrupt(void)
  336. {
  337. __u64 msr_val;
  338. rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  339. /* Check for violation of core thermal thresholds*/
  340. notify_thresholds(msr_val);
  341. if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
  342. THERMAL_THROTTLING_EVENT,
  343. CORE_LEVEL) != 0)
  344. mce_log_therm_throt_event(msr_val);
  345. if (this_cpu_has(X86_FEATURE_PLN))
  346. therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
  347. POWER_LIMIT_EVENT,
  348. CORE_LEVEL);
  349. if (this_cpu_has(X86_FEATURE_PTS)) {
  350. rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
  351. /* check violations of package thermal thresholds */
  352. notify_package_thresholds(msr_val);
  353. therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
  354. THERMAL_THROTTLING_EVENT,
  355. PACKAGE_LEVEL);
  356. if (this_cpu_has(X86_FEATURE_PLN))
  357. therm_throt_process(msr_val &
  358. PACKAGE_THERM_STATUS_POWER_LIMIT,
  359. POWER_LIMIT_EVENT,
  360. PACKAGE_LEVEL);
  361. }
  362. }
  363. static void unexpected_thermal_interrupt(void)
  364. {
  365. printk(KERN_ERR "CPU%d: Unexpected LVT thermal interrupt!\n",
  366. smp_processor_id());
  367. }
  368. static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
  369. asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
  370. {
  371. irq_enter();
  372. exit_idle();
  373. inc_irq_stat(irq_thermal_count);
  374. smp_thermal_vector();
  375. irq_exit();
  376. /* Ack only at the end to avoid potential reentry */
  377. ack_APIC_irq();
  378. }
  379. /* Thermal monitoring depends on APIC, ACPI and clock modulation */
  380. static int intel_thermal_supported(struct cpuinfo_x86 *c)
  381. {
  382. if (!cpu_has_apic)
  383. return 0;
  384. if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
  385. return 0;
  386. return 1;
  387. }
  388. void __init mcheck_intel_therm_init(void)
  389. {
  390. /*
  391. * This function is only called on boot CPU. Save the init thermal
  392. * LVT value on BSP and use that value to restore APs' thermal LVT
  393. * entry BIOS programmed later
  394. */
  395. if (intel_thermal_supported(&boot_cpu_data))
  396. lvtthmr_init = apic_read(APIC_LVTTHMR);
  397. }
  398. void intel_init_thermal(struct cpuinfo_x86 *c)
  399. {
  400. unsigned int cpu = smp_processor_id();
  401. int tm2 = 0;
  402. u32 l, h;
  403. if (!intel_thermal_supported(c))
  404. return;
  405. /*
  406. * First check if its enabled already, in which case there might
  407. * be some SMM goo which handles it, so we can't even put a handler
  408. * since it might be delivered via SMI already:
  409. */
  410. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  411. h = lvtthmr_init;
  412. /*
  413. * The initial value of thermal LVT entries on all APs always reads
  414. * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
  415. * sequence to them and LVT registers are reset to 0s except for
  416. * the mask bits which are set to 1s when APs receive INIT IPI.
  417. * If BIOS takes over the thermal interrupt and sets its interrupt
  418. * delivery mode to SMI (not fixed), it restores the value that the
  419. * BIOS has programmed on AP based on BSP's info we saved since BIOS
  420. * is always setting the same value for all threads/cores.
  421. */
  422. if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
  423. apic_write(APIC_LVTTHMR, lvtthmr_init);
  424. if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
  425. printk(KERN_DEBUG
  426. "CPU%d: Thermal monitoring handled by SMI\n", cpu);
  427. return;
  428. }
  429. /* Check whether a vector already exists */
  430. if (h & APIC_VECTOR_MASK) {
  431. printk(KERN_DEBUG
  432. "CPU%d: Thermal LVT vector (%#x) already installed\n",
  433. cpu, (h & APIC_VECTOR_MASK));
  434. return;
  435. }
  436. /* early Pentium M models use different method for enabling TM2 */
  437. if (cpu_has(c, X86_FEATURE_TM2)) {
  438. if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
  439. rdmsr(MSR_THERM2_CTL, l, h);
  440. if (l & MSR_THERM2_CTL_TM_SELECT)
  441. tm2 = 1;
  442. } else if (l & MSR_IA32_MISC_ENABLE_TM2)
  443. tm2 = 1;
  444. }
  445. /* We'll mask the thermal vector in the lapic till we're ready: */
  446. h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
  447. apic_write(APIC_LVTTHMR, h);
  448. rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
  449. if (cpu_has(c, X86_FEATURE_PLN))
  450. wrmsr(MSR_IA32_THERM_INTERRUPT,
  451. l | (THERM_INT_LOW_ENABLE
  452. | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
  453. else
  454. wrmsr(MSR_IA32_THERM_INTERRUPT,
  455. l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
  456. if (cpu_has(c, X86_FEATURE_PTS)) {
  457. rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
  458. if (cpu_has(c, X86_FEATURE_PLN))
  459. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  460. l | (PACKAGE_THERM_INT_LOW_ENABLE
  461. | PACKAGE_THERM_INT_HIGH_ENABLE
  462. | PACKAGE_THERM_INT_PLN_ENABLE), h);
  463. else
  464. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  465. l | (PACKAGE_THERM_INT_LOW_ENABLE
  466. | PACKAGE_THERM_INT_HIGH_ENABLE), h);
  467. }
  468. smp_thermal_vector = intel_thermal_interrupt;
  469. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  470. wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
  471. /* Unmask the thermal vector: */
  472. l = apic_read(APIC_LVTTHMR);
  473. apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
  474. printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n",
  475. tm2 ? "TM2" : "TM1");
  476. /* enable thermal throttle processing */
  477. atomic_set(&therm_throt_en, 1);
  478. }