dm_common.c 41 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. struct dig_t dm_digtable;
  30. static struct ps_t dm_pstable;
  31. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  32. 0x7f8001fe,
  33. 0x788001e2,
  34. 0x71c001c7,
  35. 0x6b8001ae,
  36. 0x65400195,
  37. 0x5fc0017f,
  38. 0x5a400169,
  39. 0x55400155,
  40. 0x50800142,
  41. 0x4c000130,
  42. 0x47c0011f,
  43. 0x43c0010f,
  44. 0x40000100,
  45. 0x3c8000f2,
  46. 0x390000e4,
  47. 0x35c000d7,
  48. 0x32c000cb,
  49. 0x300000c0,
  50. 0x2d4000b5,
  51. 0x2ac000ab,
  52. 0x288000a2,
  53. 0x26000098,
  54. 0x24000090,
  55. 0x22000088,
  56. 0x20000080,
  57. 0x1e400079,
  58. 0x1c800072,
  59. 0x1b00006c,
  60. 0x19800066,
  61. 0x18000060,
  62. 0x16c0005b,
  63. 0x15800056,
  64. 0x14400051,
  65. 0x1300004c,
  66. 0x12000048,
  67. 0x11000044,
  68. 0x10000040,
  69. };
  70. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  71. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  72. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  73. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  74. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  75. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  76. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  77. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  78. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  79. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  80. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  81. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  82. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  83. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  84. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  85. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  86. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  87. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  88. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  89. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  90. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  91. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  92. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  93. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  94. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  95. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  96. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  97. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  98. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  99. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  100. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  101. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  102. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  103. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  104. };
  105. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  106. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  107. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  108. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  109. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  110. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  111. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  112. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  113. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  114. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  115. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  116. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  117. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  118. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  119. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  120. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  121. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  122. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  123. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  124. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  125. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  126. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  127. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  128. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  129. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  130. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  131. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  132. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  133. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  134. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  135. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  136. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  137. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  138. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  139. };
  140. static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
  141. {
  142. dm_digtable.dig_enable_flag = true;
  143. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  144. dm_digtable.cur_igvalue = 0x20;
  145. dm_digtable.pre_igvalue = 0x0;
  146. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  147. dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
  148. dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
  149. dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
  150. dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
  151. dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  152. dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  153. dm_digtable.rx_gain_range_max = DM_DIG_MAX;
  154. dm_digtable.rx_gain_range_min = DM_DIG_MIN;
  155. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  156. dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
  157. dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
  158. dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
  159. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  160. }
  161. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  162. {
  163. struct rtl_priv *rtlpriv = rtl_priv(hw);
  164. long rssi_val_min = 0;
  165. if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
  166. (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
  167. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
  168. rssi_val_min =
  169. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
  170. rtlpriv->dm.undecorated_smoothed_pwdb) ?
  171. rtlpriv->dm.undecorated_smoothed_pwdb :
  172. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  173. else
  174. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  175. } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
  176. dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
  177. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  178. } else if (dm_digtable.curmultista_connectstate ==
  179. DIG_MULTISTA_CONNECT) {
  180. rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  181. }
  182. return (u8) rssi_val_min;
  183. }
  184. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  185. {
  186. u32 ret_value;
  187. struct rtl_priv *rtlpriv = rtl_priv(hw);
  188. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  189. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  190. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  191. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  192. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  193. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  194. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  195. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  196. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  197. falsealm_cnt->cnt_rate_illegal +
  198. falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
  199. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  200. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  201. falsealm_cnt->cnt_cck_fail = ret_value;
  202. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  203. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  204. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  205. falsealm_cnt->cnt_rate_illegal +
  206. falsealm_cnt->cnt_crc8_fail +
  207. falsealm_cnt->cnt_mcs_fail +
  208. falsealm_cnt->cnt_cck_fail);
  209. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  210. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  211. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  212. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  213. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  214. ("cnt_parity_fail = %d, cnt_rate_illegal = %d, "
  215. "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  216. falsealm_cnt->cnt_parity_fail,
  217. falsealm_cnt->cnt_rate_illegal,
  218. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail));
  219. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  220. ("cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  221. falsealm_cnt->cnt_ofdm_fail,
  222. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all));
  223. }
  224. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  225. {
  226. struct rtl_priv *rtlpriv = rtl_priv(hw);
  227. u8 value_igi = dm_digtable.cur_igvalue;
  228. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  229. value_igi--;
  230. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  231. value_igi += 0;
  232. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  233. value_igi++;
  234. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  235. value_igi += 2;
  236. if (value_igi > DM_DIG_FA_UPPER)
  237. value_igi = DM_DIG_FA_UPPER;
  238. else if (value_igi < DM_DIG_FA_LOWER)
  239. value_igi = DM_DIG_FA_LOWER;
  240. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  241. value_igi = 0x32;
  242. dm_digtable.cur_igvalue = value_igi;
  243. rtl92c_dm_write_dig(hw);
  244. }
  245. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  246. {
  247. struct rtl_priv *rtlpriv = rtl_priv(hw);
  248. if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
  249. if ((dm_digtable.backoff_val - 2) <
  250. dm_digtable.backoff_val_range_min)
  251. dm_digtable.backoff_val =
  252. dm_digtable.backoff_val_range_min;
  253. else
  254. dm_digtable.backoff_val -= 2;
  255. } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
  256. if ((dm_digtable.backoff_val + 2) >
  257. dm_digtable.backoff_val_range_max)
  258. dm_digtable.backoff_val =
  259. dm_digtable.backoff_val_range_max;
  260. else
  261. dm_digtable.backoff_val += 2;
  262. }
  263. if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
  264. dm_digtable.rx_gain_range_max)
  265. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
  266. else if ((dm_digtable.rssi_val_min + 10 -
  267. dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
  268. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
  269. else
  270. dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
  271. dm_digtable.backoff_val;
  272. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  273. ("rssi_val_min = %x backoff_val %x\n",
  274. dm_digtable.rssi_val_min, dm_digtable.backoff_val));
  275. rtl92c_dm_write_dig(hw);
  276. }
  277. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  278. {
  279. static u8 binitialized; /* initialized to false */
  280. struct rtl_priv *rtlpriv = rtl_priv(hw);
  281. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  282. long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  283. bool b_multi_sta = false;
  284. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  285. b_multi_sta = true;
  286. if ((b_multi_sta == false) || (dm_digtable.cursta_connectctate !=
  287. DIG_STA_DISCONNECT)) {
  288. binitialized = false;
  289. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  290. return;
  291. } else if (binitialized == false) {
  292. binitialized = true;
  293. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  294. dm_digtable.cur_igvalue = 0x20;
  295. rtl92c_dm_write_dig(hw);
  296. }
  297. if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
  298. if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
  299. (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  300. if (dm_digtable.dig_ext_port_stage ==
  301. DIG_EXT_PORT_STAGE_2) {
  302. dm_digtable.cur_igvalue = 0x20;
  303. rtl92c_dm_write_dig(hw);
  304. }
  305. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  306. } else if (rssi_strength > dm_digtable.rssi_highthresh) {
  307. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  308. rtl92c_dm_ctrl_initgain_by_fa(hw);
  309. }
  310. } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  311. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  312. dm_digtable.cur_igvalue = 0x20;
  313. rtl92c_dm_write_dig(hw);
  314. }
  315. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  316. ("curmultista_connectstate = "
  317. "%x dig_ext_port_stage %x\n",
  318. dm_digtable.curmultista_connectstate,
  319. dm_digtable.dig_ext_port_stage));
  320. }
  321. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  322. {
  323. struct rtl_priv *rtlpriv = rtl_priv(hw);
  324. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  325. ("presta_connectstate = %x,"
  326. " cursta_connectctate = %x\n",
  327. dm_digtable.presta_connectstate,
  328. dm_digtable.cursta_connectctate));
  329. if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
  330. || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
  331. || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  332. if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
  333. dm_digtable.rssi_val_min =
  334. rtl92c_dm_initial_gain_min_pwdb(hw);
  335. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  336. }
  337. } else {
  338. dm_digtable.rssi_val_min = 0;
  339. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  340. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  341. dm_digtable.cur_igvalue = 0x20;
  342. dm_digtable.pre_igvalue = 0;
  343. rtl92c_dm_write_dig(hw);
  344. }
  345. }
  346. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  347. {
  348. struct rtl_priv *rtlpriv = rtl_priv(hw);
  349. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  350. if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  351. dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  352. if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  353. if (dm_digtable.rssi_val_min <= 25)
  354. dm_digtable.cur_cck_pd_state =
  355. CCK_PD_STAGE_LowRssi;
  356. else
  357. dm_digtable.cur_cck_pd_state =
  358. CCK_PD_STAGE_HighRssi;
  359. } else {
  360. if (dm_digtable.rssi_val_min <= 20)
  361. dm_digtable.cur_cck_pd_state =
  362. CCK_PD_STAGE_LowRssi;
  363. else
  364. dm_digtable.cur_cck_pd_state =
  365. CCK_PD_STAGE_HighRssi;
  366. }
  367. } else {
  368. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  369. }
  370. if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
  371. if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  372. if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
  373. dm_digtable.cur_cck_fa_state =
  374. CCK_FA_STAGE_High;
  375. else
  376. dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
  377. if (dm_digtable.pre_cck_fa_state !=
  378. dm_digtable.cur_cck_fa_state) {
  379. if (dm_digtable.cur_cck_fa_state ==
  380. CCK_FA_STAGE_Low)
  381. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  382. 0x83);
  383. else
  384. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  385. 0xcd);
  386. dm_digtable.pre_cck_fa_state =
  387. dm_digtable.cur_cck_fa_state;
  388. }
  389. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
  390. if (IS_92C_SERIAL(rtlhal->version))
  391. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  392. MASKBYTE2, 0xd7);
  393. } else {
  394. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  395. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
  396. if (IS_92C_SERIAL(rtlhal->version))
  397. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  398. MASKBYTE2, 0xd3);
  399. }
  400. dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
  401. }
  402. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  403. ("CCKPDStage=%x\n", dm_digtable.cur_cck_pd_state));
  404. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  405. ("is92C=%x\n", IS_92C_SERIAL(rtlhal->version)));
  406. }
  407. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  408. {
  409. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  410. if (mac->act_scanning == true)
  411. return;
  412. if ((mac->link_state > MAC80211_NOLINK) &&
  413. (mac->link_state < MAC80211_LINKED))
  414. dm_digtable.cursta_connectctate = DIG_STA_BEFORE_CONNECT;
  415. else if (mac->link_state >= MAC80211_LINKED)
  416. dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
  417. else
  418. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  419. rtl92c_dm_initial_gain_sta(hw);
  420. rtl92c_dm_initial_gain_multi_sta(hw);
  421. rtl92c_dm_cck_packet_detection_thresh(hw);
  422. dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
  423. }
  424. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  425. {
  426. struct rtl_priv *rtlpriv = rtl_priv(hw);
  427. if (rtlpriv->dm.b_dm_initialgain_enable == false)
  428. return;
  429. if (dm_digtable.dig_enable_flag == false)
  430. return;
  431. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  432. }
  433. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  434. {
  435. struct rtl_priv *rtlpriv = rtl_priv(hw);
  436. rtlpriv->dm.bdynamic_txpower_enable = false;
  437. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  438. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  439. }
  440. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  441. {
  442. struct rtl_priv *rtlpriv = rtl_priv(hw);
  443. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  444. ("cur_igvalue = 0x%x, "
  445. "pre_igvalue = 0x%x, backoff_val = %d\n",
  446. dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
  447. dm_digtable.backoff_val));
  448. if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
  449. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  450. dm_digtable.cur_igvalue);
  451. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  452. dm_digtable.cur_igvalue);
  453. dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
  454. }
  455. }
  456. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  457. {
  458. struct rtl_priv *rtlpriv = rtl_priv(hw);
  459. long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
  460. u8 h2c_parameter[3] = { 0 };
  461. return;
  462. if (tmpentry_max_pwdb != 0) {
  463. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
  464. tmpentry_max_pwdb;
  465. } else {
  466. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
  467. }
  468. if (tmpentry_min_pwdb != 0xff) {
  469. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
  470. tmpentry_min_pwdb;
  471. } else {
  472. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
  473. }
  474. h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
  475. h2c_parameter[0] = 0;
  476. rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
  477. }
  478. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  479. {
  480. struct rtl_priv *rtlpriv = rtl_priv(hw);
  481. rtlpriv->dm.bcurrent_turbo_edca = false;
  482. rtlpriv->dm.bis_any_nonbepkts = false;
  483. rtlpriv->dm.bis_cur_rdlstate = false;
  484. }
  485. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  486. {
  487. struct rtl_priv *rtlpriv = rtl_priv(hw);
  488. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  489. static u64 last_txok_cnt;
  490. static u64 last_rxok_cnt;
  491. u64 cur_txok_cnt;
  492. u64 cur_rxok_cnt;
  493. u32 edca_be_ul = 0x5ea42b;
  494. u32 edca_be_dl = 0x5ea42b;
  495. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  496. goto dm_checkedcaturbo_exit;
  497. if (mac->link_state != MAC80211_LINKED) {
  498. rtlpriv->dm.bcurrent_turbo_edca = false;
  499. return;
  500. }
  501. if (!mac->ht_enable) { /*FIX MERGE */
  502. if (!(edca_be_ul & 0xffff0000))
  503. edca_be_ul |= 0x005e0000;
  504. if (!(edca_be_dl & 0xffff0000))
  505. edca_be_dl |= 0x005e0000;
  506. }
  507. if ((!rtlpriv->dm.bis_any_nonbepkts) &&
  508. (!rtlpriv->dm.b_disable_framebursting)) {
  509. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  510. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  511. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  512. if (!rtlpriv->dm.bis_cur_rdlstate ||
  513. !rtlpriv->dm.bcurrent_turbo_edca) {
  514. rtl_write_dword(rtlpriv,
  515. REG_EDCA_BE_PARAM,
  516. edca_be_dl);
  517. rtlpriv->dm.bis_cur_rdlstate = true;
  518. }
  519. } else {
  520. if (rtlpriv->dm.bis_cur_rdlstate ||
  521. !rtlpriv->dm.bcurrent_turbo_edca) {
  522. rtl_write_dword(rtlpriv,
  523. REG_EDCA_BE_PARAM,
  524. edca_be_ul);
  525. rtlpriv->dm.bis_cur_rdlstate = false;
  526. }
  527. }
  528. rtlpriv->dm.bcurrent_turbo_edca = true;
  529. } else {
  530. if (rtlpriv->dm.bcurrent_turbo_edca) {
  531. u8 tmp = AC0_BE;
  532. rtlpriv->cfg->ops->set_hw_reg(hw,
  533. HW_VAR_AC_PARAM,
  534. (u8 *) (&tmp));
  535. rtlpriv->dm.bcurrent_turbo_edca = false;
  536. }
  537. }
  538. dm_checkedcaturbo_exit:
  539. rtlpriv->dm.bis_any_nonbepkts = false;
  540. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  541. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  542. }
  543. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  544. *hw)
  545. {
  546. struct rtl_priv *rtlpriv = rtl_priv(hw);
  547. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  548. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  549. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  550. u8 thermalvalue, delta, delta_lck, delta_iqk;
  551. long ele_a, ele_d, temp_cck, val_x, value32;
  552. long val_y, ele_c;
  553. u8 ofdm_index[2], cck_index, ofdm_index_old[2], cck_index_old;
  554. int i;
  555. bool is2t = IS_92C_SERIAL(rtlhal->version);
  556. u8 txpwr_level[2] = {0, 0};
  557. u8 ofdm_min_index = 6, rf;
  558. rtlpriv->dm.btxpower_trackingInit = true;
  559. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  560. ("rtl92c_dm_txpower_tracking_callback_thermalmeter\n"));
  561. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  562. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  563. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  564. "eeprom_thermalmeter 0x%x\n",
  565. thermalvalue, rtlpriv->dm.thermalvalue,
  566. rtlefuse->eeprom_thermalmeter));
  567. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  568. rtlefuse->eeprom_thermalmeter));
  569. if (is2t)
  570. rf = 2;
  571. else
  572. rf = 1;
  573. if (thermalvalue) {
  574. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  575. MASKDWORD) & MASKOFDM_D;
  576. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  577. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  578. ofdm_index_old[0] = (u8) i;
  579. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  580. ("Initial pathA ele_d reg0x%x = 0x%lx, "
  581. "ofdm_index=0x%x\n",
  582. ROFDM0_XATXIQIMBALANCE,
  583. ele_d, ofdm_index_old[0]));
  584. break;
  585. }
  586. }
  587. if (is2t) {
  588. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  589. MASKDWORD) & MASKOFDM_D;
  590. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  591. if (ele_d == (ofdmswing_table[i] &
  592. MASKOFDM_D)) {
  593. ofdm_index_old[1] = (u8) i;
  594. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  595. DBG_LOUD,
  596. ("Initial pathB ele_d reg0x%x = "
  597. "0x%lx, ofdm_index=0x%x\n",
  598. ROFDM0_XBTXIQIMBALANCE, ele_d,
  599. ofdm_index_old[1]));
  600. break;
  601. }
  602. }
  603. }
  604. temp_cck =
  605. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  606. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  607. if (rtlpriv->dm.b_cck_inch14) {
  608. if (memcmp((void *)&temp_cck,
  609. (void *)&cckswing_table_ch14[i][2],
  610. 4) == 0) {
  611. cck_index_old = (u8) i;
  612. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  613. DBG_LOUD,
  614. ("Initial reg0x%x = 0x%lx, "
  615. "cck_index=0x%x, ch 14 %d\n",
  616. RCCK0_TXFILTER2, temp_cck,
  617. cck_index_old,
  618. rtlpriv->dm.b_cck_inch14));
  619. break;
  620. }
  621. } else {
  622. if (memcmp((void *)&temp_cck,
  623. (void *)
  624. &cckswing_table_ch1ch13[i][2],
  625. 4) == 0) {
  626. cck_index_old = (u8) i;
  627. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  628. DBG_LOUD,
  629. ("Initial reg0x%x = 0x%lx, "
  630. "cck_index=0x%x, ch14 %d\n",
  631. RCCK0_TXFILTER2, temp_cck,
  632. cck_index_old,
  633. rtlpriv->dm.b_cck_inch14));
  634. break;
  635. }
  636. }
  637. }
  638. if (!rtlpriv->dm.thermalvalue) {
  639. rtlpriv->dm.thermalvalue =
  640. rtlefuse->eeprom_thermalmeter;
  641. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  642. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  643. for (i = 0; i < rf; i++)
  644. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  645. rtlpriv->dm.cck_index = cck_index_old;
  646. }
  647. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  648. (thermalvalue - rtlpriv->dm.thermalvalue) :
  649. (rtlpriv->dm.thermalvalue - thermalvalue);
  650. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  651. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  652. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  653. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  654. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  655. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  656. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  657. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  658. "eeprom_thermalmeter 0x%x delta 0x%x "
  659. "delta_lck 0x%x delta_iqk 0x%x\n",
  660. thermalvalue, rtlpriv->dm.thermalvalue,
  661. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  662. delta_iqk));
  663. if (delta_lck > 1) {
  664. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  665. rtl92c_phy_lc_calibrate(hw);
  666. }
  667. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  668. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  669. for (i = 0; i < rf; i++)
  670. rtlpriv->dm.ofdm_index[i] -= delta;
  671. rtlpriv->dm.cck_index -= delta;
  672. } else {
  673. for (i = 0; i < rf; i++)
  674. rtlpriv->dm.ofdm_index[i] += delta;
  675. rtlpriv->dm.cck_index += delta;
  676. }
  677. if (is2t) {
  678. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  679. ("temp OFDM_A_index=0x%x, "
  680. "OFDM_B_index=0x%x,"
  681. "cck_index=0x%x\n",
  682. rtlpriv->dm.ofdm_index[0],
  683. rtlpriv->dm.ofdm_index[1],
  684. rtlpriv->dm.cck_index));
  685. } else {
  686. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  687. ("temp OFDM_A_index=0x%x,"
  688. "cck_index=0x%x\n",
  689. rtlpriv->dm.ofdm_index[0],
  690. rtlpriv->dm.cck_index));
  691. }
  692. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  693. for (i = 0; i < rf; i++)
  694. ofdm_index[i] =
  695. rtlpriv->dm.ofdm_index[i]
  696. + 1;
  697. cck_index = rtlpriv->dm.cck_index + 1;
  698. } else {
  699. for (i = 0; i < rf; i++)
  700. ofdm_index[i] =
  701. rtlpriv->dm.ofdm_index[i];
  702. cck_index = rtlpriv->dm.cck_index;
  703. }
  704. for (i = 0; i < rf; i++) {
  705. if (txpwr_level[i] >= 0 &&
  706. txpwr_level[i] <= 26) {
  707. if (thermalvalue >
  708. rtlefuse->eeprom_thermalmeter) {
  709. if (delta < 5)
  710. ofdm_index[i] -= 1;
  711. else
  712. ofdm_index[i] -= 2;
  713. } else if (delta > 5 && thermalvalue <
  714. rtlefuse->
  715. eeprom_thermalmeter) {
  716. ofdm_index[i] += 1;
  717. }
  718. } else if (txpwr_level[i] >= 27 &&
  719. txpwr_level[i] <= 32
  720. && thermalvalue >
  721. rtlefuse->eeprom_thermalmeter) {
  722. if (delta < 5)
  723. ofdm_index[i] -= 1;
  724. else
  725. ofdm_index[i] -= 2;
  726. } else if (txpwr_level[i] >= 32 &&
  727. txpwr_level[i] <= 38 &&
  728. thermalvalue >
  729. rtlefuse->eeprom_thermalmeter
  730. && delta > 5) {
  731. ofdm_index[i] -= 1;
  732. }
  733. }
  734. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  735. if (thermalvalue >
  736. rtlefuse->eeprom_thermalmeter) {
  737. if (delta < 5)
  738. cck_index -= 1;
  739. else
  740. cck_index -= 2;
  741. } else if (delta > 5 && thermalvalue <
  742. rtlefuse->eeprom_thermalmeter) {
  743. cck_index += 1;
  744. }
  745. } else if (txpwr_level[i] >= 27 &&
  746. txpwr_level[i] <= 32 &&
  747. thermalvalue >
  748. rtlefuse->eeprom_thermalmeter) {
  749. if (delta < 5)
  750. cck_index -= 1;
  751. else
  752. cck_index -= 2;
  753. } else if (txpwr_level[i] >= 32 &&
  754. txpwr_level[i] <= 38 &&
  755. thermalvalue > rtlefuse->eeprom_thermalmeter
  756. && delta > 5) {
  757. cck_index -= 1;
  758. }
  759. for (i = 0; i < rf; i++) {
  760. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  761. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  762. else if (ofdm_index[i] < ofdm_min_index)
  763. ofdm_index[i] = ofdm_min_index;
  764. }
  765. if (cck_index > CCK_TABLE_SIZE - 1)
  766. cck_index = CCK_TABLE_SIZE - 1;
  767. else if (cck_index < 0)
  768. cck_index = 0;
  769. if (is2t) {
  770. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  771. ("new OFDM_A_index=0x%x, "
  772. "OFDM_B_index=0x%x,"
  773. "cck_index=0x%x\n",
  774. ofdm_index[0], ofdm_index[1],
  775. cck_index));
  776. } else {
  777. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  778. ("new OFDM_A_index=0x%x,"
  779. "cck_index=0x%x\n",
  780. ofdm_index[0], cck_index));
  781. }
  782. }
  783. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  784. ele_d =
  785. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  786. val_x = rtlphy->reg_e94;
  787. val_y = rtlphy->reg_e9c;
  788. if (val_x != 0) {
  789. if ((val_x & 0x00000200) != 0)
  790. val_x = val_x | 0xFFFFFC00;
  791. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  792. if ((val_y & 0x00000200) != 0)
  793. val_y = val_y | 0xFFFFFC00;
  794. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  795. value32 = (ele_d << 22) |
  796. ((ele_c & 0x3F) << 16) | ele_a;
  797. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  798. MASKDWORD, value32);
  799. value32 = (ele_c & 0x000003C0) >> 6;
  800. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  801. value32);
  802. value32 = ((val_x * ele_d) >> 7) & 0x01;
  803. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  804. BIT(31), value32);
  805. value32 = ((val_y * ele_d) >> 7) & 0x01;
  806. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  807. BIT(29), value32);
  808. } else {
  809. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  810. MASKDWORD,
  811. ofdmswing_table[ofdm_index[0]]);
  812. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  813. 0x00);
  814. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  815. BIT(31) | BIT(29), 0x00);
  816. }
  817. if (!rtlpriv->dm.b_cck_inch14) {
  818. rtl_write_byte(rtlpriv, 0xa22,
  819. cckswing_table_ch1ch13[cck_index]
  820. [0]);
  821. rtl_write_byte(rtlpriv, 0xa23,
  822. cckswing_table_ch1ch13[cck_index]
  823. [1]);
  824. rtl_write_byte(rtlpriv, 0xa24,
  825. cckswing_table_ch1ch13[cck_index]
  826. [2]);
  827. rtl_write_byte(rtlpriv, 0xa25,
  828. cckswing_table_ch1ch13[cck_index]
  829. [3]);
  830. rtl_write_byte(rtlpriv, 0xa26,
  831. cckswing_table_ch1ch13[cck_index]
  832. [4]);
  833. rtl_write_byte(rtlpriv, 0xa27,
  834. cckswing_table_ch1ch13[cck_index]
  835. [5]);
  836. rtl_write_byte(rtlpriv, 0xa28,
  837. cckswing_table_ch1ch13[cck_index]
  838. [6]);
  839. rtl_write_byte(rtlpriv, 0xa29,
  840. cckswing_table_ch1ch13[cck_index]
  841. [7]);
  842. } else {
  843. rtl_write_byte(rtlpriv, 0xa22,
  844. cckswing_table_ch14[cck_index]
  845. [0]);
  846. rtl_write_byte(rtlpriv, 0xa23,
  847. cckswing_table_ch14[cck_index]
  848. [1]);
  849. rtl_write_byte(rtlpriv, 0xa24,
  850. cckswing_table_ch14[cck_index]
  851. [2]);
  852. rtl_write_byte(rtlpriv, 0xa25,
  853. cckswing_table_ch14[cck_index]
  854. [3]);
  855. rtl_write_byte(rtlpriv, 0xa26,
  856. cckswing_table_ch14[cck_index]
  857. [4]);
  858. rtl_write_byte(rtlpriv, 0xa27,
  859. cckswing_table_ch14[cck_index]
  860. [5]);
  861. rtl_write_byte(rtlpriv, 0xa28,
  862. cckswing_table_ch14[cck_index]
  863. [6]);
  864. rtl_write_byte(rtlpriv, 0xa29,
  865. cckswing_table_ch14[cck_index]
  866. [7]);
  867. }
  868. if (is2t) {
  869. ele_d = (ofdmswing_table[ofdm_index[1]] &
  870. 0xFFC00000) >> 22;
  871. val_x = rtlphy->reg_eb4;
  872. val_y = rtlphy->reg_ebc;
  873. if (val_x != 0) {
  874. if ((val_x & 0x00000200) != 0)
  875. val_x = val_x | 0xFFFFFC00;
  876. ele_a = ((val_x * ele_d) >> 8) &
  877. 0x000003FF;
  878. if ((val_y & 0x00000200) != 0)
  879. val_y = val_y | 0xFFFFFC00;
  880. ele_c = ((val_y * ele_d) >> 8) &
  881. 0x00003FF;
  882. value32 = (ele_d << 22) |
  883. ((ele_c & 0x3F) << 16) | ele_a;
  884. rtl_set_bbreg(hw,
  885. ROFDM0_XBTXIQIMBALANCE,
  886. MASKDWORD, value32);
  887. value32 = (ele_c & 0x000003C0) >> 6;
  888. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  889. MASKH4BITS, value32);
  890. value32 = ((val_x * ele_d) >> 7) & 0x01;
  891. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  892. BIT(27), value32);
  893. value32 = ((val_y * ele_d) >> 7) & 0x01;
  894. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  895. BIT(25), value32);
  896. } else {
  897. rtl_set_bbreg(hw,
  898. ROFDM0_XBTXIQIMBALANCE,
  899. MASKDWORD,
  900. ofdmswing_table[ofdm_index
  901. [1]]);
  902. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  903. MASKH4BITS, 0x00);
  904. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  905. BIT(27) | BIT(25), 0x00);
  906. }
  907. }
  908. }
  909. if (delta_iqk > 3) {
  910. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  911. rtl92c_phy_iq_calibrate(hw, false);
  912. }
  913. if (rtlpriv->dm.txpower_track_control)
  914. rtlpriv->dm.thermalvalue = thermalvalue;
  915. }
  916. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
  917. }
  918. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  919. struct ieee80211_hw *hw)
  920. {
  921. struct rtl_priv *rtlpriv = rtl_priv(hw);
  922. rtlpriv->dm.btxpower_tracking = true;
  923. rtlpriv->dm.btxpower_trackingInit = false;
  924. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  925. ("pMgntInfo->btxpower_tracking = %d\n",
  926. rtlpriv->dm.btxpower_tracking));
  927. }
  928. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  929. {
  930. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  931. }
  932. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  933. {
  934. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  935. }
  936. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  937. struct ieee80211_hw *hw)
  938. {
  939. struct rtl_priv *rtlpriv = rtl_priv(hw);
  940. static u8 tm_trigger;
  941. if (!rtlpriv->dm.btxpower_tracking)
  942. return;
  943. if (!tm_trigger) {
  944. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  945. 0x60);
  946. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  947. ("Trigger 92S Thermal Meter!!\n"));
  948. tm_trigger = 1;
  949. return;
  950. } else {
  951. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  952. ("Schedule TxPowerTracking direct call!!\n"));
  953. rtl92c_dm_txpower_tracking_directcall(hw);
  954. tm_trigger = 0;
  955. }
  956. }
  957. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  958. {
  959. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  960. }
  961. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  962. {
  963. struct rtl_priv *rtlpriv = rtl_priv(hw);
  964. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  965. p_ra->ratr_state = DM_RATR_STA_INIT;
  966. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  967. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  968. rtlpriv->dm.b_useramask = true;
  969. else
  970. rtlpriv->dm.b_useramask = false;
  971. }
  972. static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
  973. {
  974. struct rtl_priv *rtlpriv = rtl_priv(hw);
  975. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  976. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  977. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  978. u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
  979. if (is_hal_stop(rtlhal)) {
  980. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  981. ("<---- driver is going to unload\n"));
  982. return;
  983. }
  984. if (!rtlpriv->dm.b_useramask) {
  985. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  986. ("<---- driver does not control rate adaptive mask\n"));
  987. return;
  988. }
  989. if (mac->link_state == MAC80211_LINKED) {
  990. switch (p_ra->pre_ratr_state) {
  991. case DM_RATR_STA_HIGH:
  992. high_rssithresh_for_ra = 50;
  993. low_rssithresh_for_ra = 20;
  994. break;
  995. case DM_RATR_STA_MIDDLE:
  996. high_rssithresh_for_ra = 55;
  997. low_rssithresh_for_ra = 20;
  998. break;
  999. case DM_RATR_STA_LOW:
  1000. high_rssithresh_for_ra = 50;
  1001. low_rssithresh_for_ra = 25;
  1002. break;
  1003. default:
  1004. high_rssithresh_for_ra = 50;
  1005. low_rssithresh_for_ra = 20;
  1006. break;
  1007. }
  1008. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1009. (long)high_rssithresh_for_ra)
  1010. p_ra->ratr_state = DM_RATR_STA_HIGH;
  1011. else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1012. (long)low_rssithresh_for_ra)
  1013. p_ra->ratr_state = DM_RATR_STA_MIDDLE;
  1014. else
  1015. p_ra->ratr_state = DM_RATR_STA_LOW;
  1016. if (p_ra->pre_ratr_state != p_ra->ratr_state) {
  1017. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1018. ("RSSI = %ld\n",
  1019. rtlpriv->dm.undecorated_smoothed_pwdb));
  1020. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1021. ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
  1022. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1023. ("PreState = %d, CurState = %d\n",
  1024. p_ra->pre_ratr_state, p_ra->ratr_state));
  1025. rtlpriv->cfg->ops->update_rate_mask(hw,
  1026. p_ra->ratr_state);
  1027. p_ra->pre_ratr_state = p_ra->ratr_state;
  1028. }
  1029. }
  1030. }
  1031. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1032. {
  1033. dm_pstable.pre_ccastate = CCA_MAX;
  1034. dm_pstable.cur_ccasate = CCA_MAX;
  1035. dm_pstable.pre_rfstate = RF_MAX;
  1036. dm_pstable.cur_rfstate = RF_MAX;
  1037. dm_pstable.rssi_val_min = 0;
  1038. }
  1039. static void rtl92c_dm_1r_cca(struct ieee80211_hw *hw)
  1040. {
  1041. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1042. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1043. if (dm_pstable.rssi_val_min != 0) {
  1044. if (dm_pstable.pre_ccastate == CCA_2R) {
  1045. if (dm_pstable.rssi_val_min >= 35)
  1046. dm_pstable.cur_ccasate = CCA_1R;
  1047. else
  1048. dm_pstable.cur_ccasate = CCA_2R;
  1049. } else {
  1050. if (dm_pstable.rssi_val_min <= 30)
  1051. dm_pstable.cur_ccasate = CCA_2R;
  1052. else
  1053. dm_pstable.cur_ccasate = CCA_1R;
  1054. }
  1055. } else {
  1056. dm_pstable.cur_ccasate = CCA_MAX;
  1057. }
  1058. if (dm_pstable.pre_ccastate != dm_pstable.cur_ccasate) {
  1059. if (dm_pstable.cur_ccasate == CCA_1R) {
  1060. if (get_rf_type(rtlphy) == RF_2T2R) {
  1061. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
  1062. MASKBYTE0, 0x13);
  1063. rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x20);
  1064. } else {
  1065. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
  1066. MASKBYTE0, 0x23);
  1067. rtl_set_bbreg(hw, 0xe70, 0x7fc00000, 0x10c);
  1068. }
  1069. } else {
  1070. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0,
  1071. 0x33);
  1072. rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x63);
  1073. }
  1074. dm_pstable.pre_ccastate = dm_pstable.cur_ccasate;
  1075. }
  1076. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, ("CCAStage = %s\n",
  1077. (dm_pstable.cur_ccasate ==
  1078. 0) ? "1RCCA" : "2RCCA"));
  1079. }
  1080. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  1081. {
  1082. static u8 initialize;
  1083. static u32 reg_874, reg_c70, reg_85c, reg_a74;
  1084. if (initialize == 0) {
  1085. reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1086. MASKDWORD) & 0x1CC000) >> 14;
  1087. reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  1088. MASKDWORD) & BIT(3)) >> 3;
  1089. reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1090. MASKDWORD) & 0xFF000000) >> 24;
  1091. reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
  1092. initialize = 1;
  1093. }
  1094. if (!bforce_in_normal) {
  1095. if (dm_pstable.rssi_val_min != 0) {
  1096. if (dm_pstable.pre_rfstate == RF_NORMAL) {
  1097. if (dm_pstable.rssi_val_min >= 30)
  1098. dm_pstable.cur_rfstate = RF_SAVE;
  1099. else
  1100. dm_pstable.cur_rfstate = RF_NORMAL;
  1101. } else {
  1102. if (dm_pstable.rssi_val_min <= 25)
  1103. dm_pstable.cur_rfstate = RF_NORMAL;
  1104. else
  1105. dm_pstable.cur_rfstate = RF_SAVE;
  1106. }
  1107. } else {
  1108. dm_pstable.cur_rfstate = RF_MAX;
  1109. }
  1110. } else {
  1111. dm_pstable.cur_rfstate = RF_NORMAL;
  1112. }
  1113. if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
  1114. if (dm_pstable.cur_rfstate == RF_SAVE) {
  1115. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1116. 0x1C0000, 0x2);
  1117. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1118. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1119. 0xFF000000, 0x63);
  1120. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1121. 0xC000, 0x2);
  1122. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1123. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1124. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1125. } else {
  1126. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1127. 0x1CC000, reg_874);
  1128. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1129. reg_c70);
  1130. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1131. reg_85c);
  1132. rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
  1133. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1134. }
  1135. dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
  1136. }
  1137. }
  1138. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1139. {
  1140. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1141. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1142. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1143. if (((mac->link_state == MAC80211_NOLINK)) &&
  1144. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1145. dm_pstable.rssi_val_min = 0;
  1146. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1147. ("Not connected to any\n"));
  1148. }
  1149. if (mac->link_state == MAC80211_LINKED) {
  1150. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1151. dm_pstable.rssi_val_min =
  1152. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1153. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1154. ("AP Client PWDB = 0x%lx\n",
  1155. dm_pstable.rssi_val_min));
  1156. } else {
  1157. dm_pstable.rssi_val_min =
  1158. rtlpriv->dm.undecorated_smoothed_pwdb;
  1159. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1160. ("STA Default Port PWDB = 0x%lx\n",
  1161. dm_pstable.rssi_val_min));
  1162. }
  1163. } else {
  1164. dm_pstable.rssi_val_min =
  1165. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1166. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1167. ("AP Ext Port PWDB = 0x%lx\n",
  1168. dm_pstable.rssi_val_min));
  1169. }
  1170. if (IS_92C_SERIAL(rtlhal->version))
  1171. rtl92c_dm_1r_cca(hw);
  1172. }
  1173. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1174. {
  1175. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1176. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1177. rtl92c_dm_diginit(hw);
  1178. rtl92c_dm_init_dynamic_txpower(hw);
  1179. rtl92c_dm_init_edca_turbo(hw);
  1180. rtl92c_dm_init_rate_adaptive_mask(hw);
  1181. rtl92c_dm_initialize_txpower_tracking(hw);
  1182. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1183. }
  1184. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1185. {
  1186. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1187. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1188. bool b_fw_current_inpsmode = false;
  1189. bool b_fw_ps_awake = true;
  1190. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1191. (u8 *) (&b_fw_current_inpsmode));
  1192. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1193. (u8 *) (&b_fw_ps_awake));
  1194. if ((ppsc->rfpwr_state == ERFON) && ((!b_fw_current_inpsmode) &&
  1195. b_fw_ps_awake)
  1196. && (!ppsc->rfchange_inprogress)) {
  1197. rtl92c_dm_pwdb_monitor(hw);
  1198. rtl92c_dm_dig(hw);
  1199. rtl92c_dm_false_alarm_counter_statistics(hw);
  1200. rtl92c_dm_dynamic_bb_powersaving(hw);
  1201. rtl92c_dm_dynamic_txpower(hw);
  1202. rtl92c_dm_check_txpower_tracking(hw);
  1203. rtl92c_dm_refresh_rate_adaptive_mask(hw);
  1204. rtl92c_dm_check_edca_turbo(hw);
  1205. }
  1206. }