main.c 54 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static u8 parse_mpdudensity(u8 mpdudensity)
  20. {
  21. /*
  22. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  23. * 0 for no restriction
  24. * 1 for 1/4 us
  25. * 2 for 1/2 us
  26. * 3 for 1 us
  27. * 4 for 2 us
  28. * 5 for 4 us
  29. * 6 for 8 us
  30. * 7 for 16 us
  31. */
  32. switch (mpdudensity) {
  33. case 0:
  34. return 0;
  35. case 1:
  36. case 2:
  37. case 3:
  38. /* Our lower layer calculations limit our precision to
  39. 1 microsecond */
  40. return 1;
  41. case 4:
  42. return 2;
  43. case 5:
  44. return 4;
  45. case 6:
  46. return 8;
  47. case 7:
  48. return 16;
  49. default:
  50. return 0;
  51. }
  52. }
  53. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  54. {
  55. unsigned long flags;
  56. bool ret;
  57. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  58. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  59. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  60. return ret;
  61. }
  62. void ath9k_ps_wakeup(struct ath_softc *sc)
  63. {
  64. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  65. unsigned long flags;
  66. enum ath9k_power_mode power_mode;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. if (++sc->ps_usecount != 1)
  69. goto unlock;
  70. power_mode = sc->sc_ah->power_mode;
  71. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  72. /*
  73. * While the hardware is asleep, the cycle counters contain no
  74. * useful data. Better clear them now so that they don't mess up
  75. * survey data results.
  76. */
  77. if (power_mode != ATH9K_PM_AWAKE) {
  78. spin_lock(&common->cc_lock);
  79. ath_hw_cycle_counters_update(common);
  80. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  81. spin_unlock(&common->cc_lock);
  82. }
  83. unlock:
  84. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  85. }
  86. void ath9k_ps_restore(struct ath_softc *sc)
  87. {
  88. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  89. unsigned long flags;
  90. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  91. if (--sc->ps_usecount != 0)
  92. goto unlock;
  93. spin_lock(&common->cc_lock);
  94. ath_hw_cycle_counters_update(common);
  95. spin_unlock(&common->cc_lock);
  96. if (sc->ps_idle)
  97. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  98. else if (sc->ps_enabled &&
  99. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  100. PS_WAIT_FOR_CAB |
  101. PS_WAIT_FOR_PSPOLL_DATA |
  102. PS_WAIT_FOR_TX_ACK)))
  103. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  104. unlock:
  105. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  106. }
  107. static void ath_start_ani(struct ath_common *common)
  108. {
  109. struct ath_hw *ah = common->ah;
  110. unsigned long timestamp = jiffies_to_msecs(jiffies);
  111. struct ath_softc *sc = (struct ath_softc *) common->priv;
  112. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  113. return;
  114. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  115. return;
  116. common->ani.longcal_timer = timestamp;
  117. common->ani.shortcal_timer = timestamp;
  118. common->ani.checkani_timer = timestamp;
  119. mod_timer(&common->ani.timer,
  120. jiffies +
  121. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  122. }
  123. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  124. {
  125. struct ath_hw *ah = sc->sc_ah;
  126. struct ath9k_channel *chan = &ah->channels[channel];
  127. struct survey_info *survey = &sc->survey[channel];
  128. if (chan->noisefloor) {
  129. survey->filled |= SURVEY_INFO_NOISE_DBM;
  130. survey->noise = chan->noisefloor;
  131. }
  132. }
  133. /*
  134. * Updates the survey statistics and returns the busy time since last
  135. * update in %, if the measurement duration was long enough for the
  136. * result to be useful, -1 otherwise.
  137. */
  138. static int ath_update_survey_stats(struct ath_softc *sc)
  139. {
  140. struct ath_hw *ah = sc->sc_ah;
  141. struct ath_common *common = ath9k_hw_common(ah);
  142. int pos = ah->curchan - &ah->channels[0];
  143. struct survey_info *survey = &sc->survey[pos];
  144. struct ath_cycle_counters *cc = &common->cc_survey;
  145. unsigned int div = common->clockrate * 1000;
  146. int ret = 0;
  147. if (!ah->curchan)
  148. return -1;
  149. if (ah->power_mode == ATH9K_PM_AWAKE)
  150. ath_hw_cycle_counters_update(common);
  151. if (cc->cycles > 0) {
  152. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  153. SURVEY_INFO_CHANNEL_TIME_BUSY |
  154. SURVEY_INFO_CHANNEL_TIME_RX |
  155. SURVEY_INFO_CHANNEL_TIME_TX;
  156. survey->channel_time += cc->cycles / div;
  157. survey->channel_time_busy += cc->rx_busy / div;
  158. survey->channel_time_rx += cc->rx_frame / div;
  159. survey->channel_time_tx += cc->tx_frame / div;
  160. }
  161. if (cc->cycles < div)
  162. return -1;
  163. if (cc->cycles > 0)
  164. ret = cc->rx_busy * 100 / cc->cycles;
  165. memset(cc, 0, sizeof(*cc));
  166. ath_update_survey_nf(sc, pos);
  167. return ret;
  168. }
  169. /*
  170. * Set/change channels. If the channel is really being changed, it's done
  171. * by reseting the chip. To accomplish this we must first cleanup any pending
  172. * DMA, then restart stuff.
  173. */
  174. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  175. struct ath9k_channel *hchan)
  176. {
  177. struct ath_hw *ah = sc->sc_ah;
  178. struct ath_common *common = ath9k_hw_common(ah);
  179. struct ieee80211_conf *conf = &common->hw->conf;
  180. bool fastcc = true, stopped;
  181. struct ieee80211_channel *channel = hw->conf.channel;
  182. struct ath9k_hw_cal_data *caldata = NULL;
  183. int r;
  184. if (sc->sc_flags & SC_OP_INVALID)
  185. return -EIO;
  186. sc->hw_busy_count = 0;
  187. del_timer_sync(&common->ani.timer);
  188. cancel_work_sync(&sc->paprd_work);
  189. cancel_work_sync(&sc->hw_check_work);
  190. cancel_delayed_work_sync(&sc->tx_complete_work);
  191. cancel_delayed_work_sync(&sc->hw_pll_work);
  192. ath9k_ps_wakeup(sc);
  193. spin_lock_bh(&sc->sc_pcu_lock);
  194. /*
  195. * This is only performed if the channel settings have
  196. * actually changed.
  197. *
  198. * To switch channels clear any pending DMA operations;
  199. * wait long enough for the RX fifo to drain, reset the
  200. * hardware at the new frequency, and then re-enable
  201. * the relevant bits of the h/w.
  202. */
  203. ath9k_hw_disable_interrupts(ah);
  204. stopped = ath_drain_all_txq(sc, false);
  205. if (!ath_stoprecv(sc))
  206. stopped = false;
  207. if (!ath9k_hw_check_alive(ah))
  208. stopped = false;
  209. /* XXX: do not flush receive queue here. We don't want
  210. * to flush data frames already in queue because of
  211. * changing channel. */
  212. if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
  213. fastcc = false;
  214. if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
  215. caldata = &sc->caldata;
  216. ath_dbg(common, ATH_DBG_CONFIG,
  217. "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
  218. sc->sc_ah->curchan->channel,
  219. channel->center_freq, conf_is_ht40(conf),
  220. fastcc);
  221. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  222. if (r) {
  223. ath_err(common,
  224. "Unable to reset channel (%u MHz), reset status %d\n",
  225. channel->center_freq, r);
  226. goto ps_restore;
  227. }
  228. if (ath_startrecv(sc) != 0) {
  229. ath_err(common, "Unable to restart recv logic\n");
  230. r = -EIO;
  231. goto ps_restore;
  232. }
  233. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  234. sc->config.txpowlimit, &sc->curtxpow);
  235. ath9k_hw_set_interrupts(ah, ah->imask);
  236. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
  237. if (sc->sc_flags & SC_OP_BEACONS)
  238. ath_beacon_config(sc, NULL);
  239. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  240. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
  241. ath_start_ani(common);
  242. }
  243. ps_restore:
  244. ieee80211_wake_queues(hw);
  245. spin_unlock_bh(&sc->sc_pcu_lock);
  246. ath9k_ps_restore(sc);
  247. return r;
  248. }
  249. static void ath_paprd_activate(struct ath_softc *sc)
  250. {
  251. struct ath_hw *ah = sc->sc_ah;
  252. struct ath9k_hw_cal_data *caldata = ah->caldata;
  253. struct ath_common *common = ath9k_hw_common(ah);
  254. int chain;
  255. if (!caldata || !caldata->paprd_done)
  256. return;
  257. ath9k_ps_wakeup(sc);
  258. ar9003_paprd_enable(ah, false);
  259. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  260. if (!(common->tx_chainmask & BIT(chain)))
  261. continue;
  262. ar9003_paprd_populate_single_table(ah, caldata, chain);
  263. }
  264. ar9003_paprd_enable(ah, true);
  265. ath9k_ps_restore(sc);
  266. }
  267. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  268. {
  269. struct ieee80211_hw *hw = sc->hw;
  270. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  271. struct ath_hw *ah = sc->sc_ah;
  272. struct ath_common *common = ath9k_hw_common(ah);
  273. struct ath_tx_control txctl;
  274. int time_left;
  275. memset(&txctl, 0, sizeof(txctl));
  276. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  277. memset(tx_info, 0, sizeof(*tx_info));
  278. tx_info->band = hw->conf.channel->band;
  279. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  280. tx_info->control.rates[0].idx = 0;
  281. tx_info->control.rates[0].count = 1;
  282. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  283. tx_info->control.rates[1].idx = -1;
  284. init_completion(&sc->paprd_complete);
  285. sc->paprd_pending = true;
  286. txctl.paprd = BIT(chain);
  287. if (ath_tx_start(hw, skb, &txctl) != 0) {
  288. ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
  289. dev_kfree_skb_any(skb);
  290. return false;
  291. }
  292. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  293. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  294. sc->paprd_pending = false;
  295. if (!time_left)
  296. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
  297. "Timeout waiting for paprd training on TX chain %d\n",
  298. chain);
  299. return !!time_left;
  300. }
  301. void ath_paprd_calibrate(struct work_struct *work)
  302. {
  303. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  304. struct ieee80211_hw *hw = sc->hw;
  305. struct ath_hw *ah = sc->sc_ah;
  306. struct ieee80211_hdr *hdr;
  307. struct sk_buff *skb = NULL;
  308. struct ath9k_hw_cal_data *caldata = ah->caldata;
  309. struct ath_common *common = ath9k_hw_common(ah);
  310. int ftype;
  311. int chain_ok = 0;
  312. int chain;
  313. int len = 1800;
  314. if (!caldata)
  315. return;
  316. if (ar9003_paprd_init_table(ah) < 0)
  317. return;
  318. skb = alloc_skb(len, GFP_KERNEL);
  319. if (!skb)
  320. return;
  321. skb_put(skb, len);
  322. memset(skb->data, 0, len);
  323. hdr = (struct ieee80211_hdr *)skb->data;
  324. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  325. hdr->frame_control = cpu_to_le16(ftype);
  326. hdr->duration_id = cpu_to_le16(10);
  327. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  328. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  329. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  330. ath9k_ps_wakeup(sc);
  331. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  332. if (!(common->tx_chainmask & BIT(chain)))
  333. continue;
  334. chain_ok = 0;
  335. ath_dbg(common, ATH_DBG_CALIBRATE,
  336. "Sending PAPRD frame for thermal measurement "
  337. "on chain %d\n", chain);
  338. if (!ath_paprd_send_frame(sc, skb, chain))
  339. goto fail_paprd;
  340. ar9003_paprd_setup_gain_table(ah, chain);
  341. ath_dbg(common, ATH_DBG_CALIBRATE,
  342. "Sending PAPRD training frame on chain %d\n", chain);
  343. if (!ath_paprd_send_frame(sc, skb, chain))
  344. goto fail_paprd;
  345. if (!ar9003_paprd_is_done(ah))
  346. break;
  347. if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
  348. break;
  349. chain_ok = 1;
  350. }
  351. kfree_skb(skb);
  352. if (chain_ok) {
  353. caldata->paprd_done = true;
  354. ath_paprd_activate(sc);
  355. }
  356. fail_paprd:
  357. ath9k_ps_restore(sc);
  358. }
  359. /*
  360. * This routine performs the periodic noise floor calibration function
  361. * that is used to adjust and optimize the chip performance. This
  362. * takes environmental changes (location, temperature) into account.
  363. * When the task is complete, it reschedules itself depending on the
  364. * appropriate interval that was calculated.
  365. */
  366. void ath_ani_calibrate(unsigned long data)
  367. {
  368. struct ath_softc *sc = (struct ath_softc *)data;
  369. struct ath_hw *ah = sc->sc_ah;
  370. struct ath_common *common = ath9k_hw_common(ah);
  371. bool longcal = false;
  372. bool shortcal = false;
  373. bool aniflag = false;
  374. unsigned int timestamp = jiffies_to_msecs(jiffies);
  375. u32 cal_interval, short_cal_interval, long_cal_interval;
  376. unsigned long flags;
  377. if (ah->caldata && ah->caldata->nfcal_interference)
  378. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  379. else
  380. long_cal_interval = ATH_LONG_CALINTERVAL;
  381. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  382. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  383. /* Only calibrate if awake */
  384. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  385. goto set_timer;
  386. ath9k_ps_wakeup(sc);
  387. /* Long calibration runs independently of short calibration. */
  388. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  389. longcal = true;
  390. ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  391. common->ani.longcal_timer = timestamp;
  392. }
  393. /* Short calibration applies only while caldone is false */
  394. if (!common->ani.caldone) {
  395. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  396. shortcal = true;
  397. ath_dbg(common, ATH_DBG_ANI,
  398. "shortcal @%lu\n", jiffies);
  399. common->ani.shortcal_timer = timestamp;
  400. common->ani.resetcal_timer = timestamp;
  401. }
  402. } else {
  403. if ((timestamp - common->ani.resetcal_timer) >=
  404. ATH_RESTART_CALINTERVAL) {
  405. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  406. if (common->ani.caldone)
  407. common->ani.resetcal_timer = timestamp;
  408. }
  409. }
  410. /* Verify whether we must check ANI */
  411. if ((timestamp - common->ani.checkani_timer) >=
  412. ah->config.ani_poll_interval) {
  413. aniflag = true;
  414. common->ani.checkani_timer = timestamp;
  415. }
  416. /* Skip all processing if there's nothing to do. */
  417. if (longcal || shortcal || aniflag) {
  418. /* Call ANI routine if necessary */
  419. if (aniflag) {
  420. spin_lock_irqsave(&common->cc_lock, flags);
  421. ath9k_hw_ani_monitor(ah, ah->curchan);
  422. ath_update_survey_stats(sc);
  423. spin_unlock_irqrestore(&common->cc_lock, flags);
  424. }
  425. /* Perform calibration if necessary */
  426. if (longcal || shortcal) {
  427. common->ani.caldone =
  428. ath9k_hw_calibrate(ah,
  429. ah->curchan,
  430. common->rx_chainmask,
  431. longcal);
  432. }
  433. }
  434. ath9k_ps_restore(sc);
  435. set_timer:
  436. /*
  437. * Set timer interval based on previous results.
  438. * The interval must be the shortest necessary to satisfy ANI,
  439. * short calibration and long calibration.
  440. */
  441. cal_interval = ATH_LONG_CALINTERVAL;
  442. if (sc->sc_ah->config.enable_ani)
  443. cal_interval = min(cal_interval,
  444. (u32)ah->config.ani_poll_interval);
  445. if (!common->ani.caldone)
  446. cal_interval = min(cal_interval, (u32)short_cal_interval);
  447. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  448. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  449. if (!ah->caldata->paprd_done)
  450. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  451. else if (!ah->paprd_table_write_done)
  452. ath_paprd_activate(sc);
  453. }
  454. }
  455. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  456. {
  457. struct ath_node *an;
  458. struct ath_hw *ah = sc->sc_ah;
  459. an = (struct ath_node *)sta->drv_priv;
  460. #ifdef CONFIG_ATH9K_DEBUGFS
  461. spin_lock(&sc->nodes_lock);
  462. list_add(&an->list, &sc->nodes);
  463. spin_unlock(&sc->nodes_lock);
  464. an->sta = sta;
  465. #endif
  466. if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
  467. sc->sc_flags |= SC_OP_ENABLE_APM;
  468. if (sc->sc_flags & SC_OP_TXAGGR) {
  469. ath_tx_node_init(sc, an);
  470. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  471. sta->ht_cap.ampdu_factor);
  472. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  473. }
  474. }
  475. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  476. {
  477. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  478. #ifdef CONFIG_ATH9K_DEBUGFS
  479. spin_lock(&sc->nodes_lock);
  480. list_del(&an->list);
  481. spin_unlock(&sc->nodes_lock);
  482. an->sta = NULL;
  483. #endif
  484. if (sc->sc_flags & SC_OP_TXAGGR)
  485. ath_tx_node_cleanup(sc, an);
  486. }
  487. void ath_hw_check(struct work_struct *work)
  488. {
  489. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  490. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  491. unsigned long flags;
  492. int busy;
  493. ath9k_ps_wakeup(sc);
  494. if (ath9k_hw_check_alive(sc->sc_ah))
  495. goto out;
  496. spin_lock_irqsave(&common->cc_lock, flags);
  497. busy = ath_update_survey_stats(sc);
  498. spin_unlock_irqrestore(&common->cc_lock, flags);
  499. ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
  500. "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
  501. if (busy >= 99) {
  502. if (++sc->hw_busy_count >= 3)
  503. ath_reset(sc, true);
  504. } else if (busy >= 0)
  505. sc->hw_busy_count = 0;
  506. out:
  507. ath9k_ps_restore(sc);
  508. }
  509. void ath9k_tasklet(unsigned long data)
  510. {
  511. struct ath_softc *sc = (struct ath_softc *)data;
  512. struct ath_hw *ah = sc->sc_ah;
  513. struct ath_common *common = ath9k_hw_common(ah);
  514. u32 status = sc->intrstatus;
  515. u32 rxmask;
  516. if (status & ATH9K_INT_FATAL) {
  517. ath_reset(sc, true);
  518. return;
  519. }
  520. ath9k_ps_wakeup(sc);
  521. spin_lock(&sc->sc_pcu_lock);
  522. /*
  523. * Only run the baseband hang check if beacons stop working in AP or
  524. * IBSS mode, because it has a high false positive rate. For station
  525. * mode it should not be necessary, since the upper layers will detect
  526. * this through a beacon miss automatically and the following channel
  527. * change will trigger a hardware reset anyway
  528. */
  529. if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
  530. !ath9k_hw_check_alive(ah))
  531. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  532. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  533. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  534. ATH9K_INT_RXORN);
  535. else
  536. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  537. if (status & rxmask) {
  538. /* Check for high priority Rx first */
  539. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  540. (status & ATH9K_INT_RXHP))
  541. ath_rx_tasklet(sc, 0, true);
  542. ath_rx_tasklet(sc, 0, false);
  543. }
  544. if (status & ATH9K_INT_TX) {
  545. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  546. ath_tx_edma_tasklet(sc);
  547. else
  548. ath_tx_tasklet(sc);
  549. }
  550. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  551. /*
  552. * TSF sync does not look correct; remain awake to sync with
  553. * the next Beacon.
  554. */
  555. ath_dbg(common, ATH_DBG_PS,
  556. "TSFOOR - Sync with next Beacon\n");
  557. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  558. }
  559. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  560. if (status & ATH9K_INT_GENTIMER)
  561. ath_gen_timer_isr(sc->sc_ah);
  562. /* re-enable hardware interrupt */
  563. ath9k_hw_enable_interrupts(ah);
  564. spin_unlock(&sc->sc_pcu_lock);
  565. ath9k_ps_restore(sc);
  566. }
  567. irqreturn_t ath_isr(int irq, void *dev)
  568. {
  569. #define SCHED_INTR ( \
  570. ATH9K_INT_FATAL | \
  571. ATH9K_INT_RXORN | \
  572. ATH9K_INT_RXEOL | \
  573. ATH9K_INT_RX | \
  574. ATH9K_INT_RXLP | \
  575. ATH9K_INT_RXHP | \
  576. ATH9K_INT_TX | \
  577. ATH9K_INT_BMISS | \
  578. ATH9K_INT_CST | \
  579. ATH9K_INT_TSFOOR | \
  580. ATH9K_INT_GENTIMER)
  581. struct ath_softc *sc = dev;
  582. struct ath_hw *ah = sc->sc_ah;
  583. struct ath_common *common = ath9k_hw_common(ah);
  584. enum ath9k_int status;
  585. bool sched = false;
  586. /*
  587. * The hardware is not ready/present, don't
  588. * touch anything. Note this can happen early
  589. * on if the IRQ is shared.
  590. */
  591. if (sc->sc_flags & SC_OP_INVALID)
  592. return IRQ_NONE;
  593. /* shared irq, not for us */
  594. if (!ath9k_hw_intrpend(ah))
  595. return IRQ_NONE;
  596. /*
  597. * Figure out the reason(s) for the interrupt. Note
  598. * that the hal returns a pseudo-ISR that may include
  599. * bits we haven't explicitly enabled so we mask the
  600. * value to insure we only process bits we requested.
  601. */
  602. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  603. status &= ah->imask; /* discard unasked-for bits */
  604. /*
  605. * If there are no status bits set, then this interrupt was not
  606. * for me (should have been caught above).
  607. */
  608. if (!status)
  609. return IRQ_NONE;
  610. /* Cache the status */
  611. sc->intrstatus = status;
  612. if (status & SCHED_INTR)
  613. sched = true;
  614. /*
  615. * If a FATAL or RXORN interrupt is received, we have to reset the
  616. * chip immediately.
  617. */
  618. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  619. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  620. goto chip_reset;
  621. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  622. (status & ATH9K_INT_BB_WATCHDOG)) {
  623. spin_lock(&common->cc_lock);
  624. ath_hw_cycle_counters_update(common);
  625. ar9003_hw_bb_watchdog_dbg_info(ah);
  626. spin_unlock(&common->cc_lock);
  627. goto chip_reset;
  628. }
  629. if (status & ATH9K_INT_SWBA)
  630. tasklet_schedule(&sc->bcon_tasklet);
  631. if (status & ATH9K_INT_TXURN)
  632. ath9k_hw_updatetxtriglevel(ah, true);
  633. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  634. if (status & ATH9K_INT_RXEOL) {
  635. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  636. ath9k_hw_set_interrupts(ah, ah->imask);
  637. }
  638. }
  639. if (status & ATH9K_INT_MIB) {
  640. /*
  641. * Disable interrupts until we service the MIB
  642. * interrupt; otherwise it will continue to
  643. * fire.
  644. */
  645. ath9k_hw_disable_interrupts(ah);
  646. /*
  647. * Let the hal handle the event. We assume
  648. * it will clear whatever condition caused
  649. * the interrupt.
  650. */
  651. spin_lock(&common->cc_lock);
  652. ath9k_hw_proc_mib_event(ah);
  653. spin_unlock(&common->cc_lock);
  654. ath9k_hw_enable_interrupts(ah);
  655. }
  656. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  657. if (status & ATH9K_INT_TIM_TIMER) {
  658. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  659. goto chip_reset;
  660. /* Clear RxAbort bit so that we can
  661. * receive frames */
  662. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  663. ath9k_hw_setrxabort(sc->sc_ah, 0);
  664. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  665. }
  666. chip_reset:
  667. ath_debug_stat_interrupt(sc, status);
  668. if (sched) {
  669. /* turn off every interrupt */
  670. ath9k_hw_disable_interrupts(ah);
  671. tasklet_schedule(&sc->intr_tq);
  672. }
  673. return IRQ_HANDLED;
  674. #undef SCHED_INTR
  675. }
  676. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  677. struct ieee80211_hw *hw,
  678. struct ieee80211_vif *vif,
  679. struct ieee80211_bss_conf *bss_conf)
  680. {
  681. struct ath_hw *ah = sc->sc_ah;
  682. struct ath_common *common = ath9k_hw_common(ah);
  683. if (bss_conf->assoc) {
  684. ath_dbg(common, ATH_DBG_CONFIG,
  685. "Bss Info ASSOC %d, bssid: %pM\n",
  686. bss_conf->aid, common->curbssid);
  687. /* New association, store aid */
  688. common->curaid = bss_conf->aid;
  689. ath9k_hw_write_associd(ah);
  690. /*
  691. * Request a re-configuration of Beacon related timers
  692. * on the receipt of the first Beacon frame (i.e.,
  693. * after time sync with the AP).
  694. */
  695. sc->ps_flags |= PS_BEACON_SYNC;
  696. /* Configure the beacon */
  697. ath_beacon_config(sc, vif);
  698. /* Reset rssi stats */
  699. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  700. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  701. sc->sc_flags |= SC_OP_ANI_RUN;
  702. ath_start_ani(common);
  703. } else {
  704. ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  705. common->curaid = 0;
  706. /* Stop ANI */
  707. sc->sc_flags &= ~SC_OP_ANI_RUN;
  708. del_timer_sync(&common->ani.timer);
  709. }
  710. }
  711. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  712. {
  713. struct ath_hw *ah = sc->sc_ah;
  714. struct ath_common *common = ath9k_hw_common(ah);
  715. struct ieee80211_channel *channel = hw->conf.channel;
  716. int r;
  717. ath9k_ps_wakeup(sc);
  718. spin_lock_bh(&sc->sc_pcu_lock);
  719. ath9k_hw_configpcipowersave(ah, 0, 0);
  720. if (!ah->curchan)
  721. ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
  722. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  723. if (r) {
  724. ath_err(common,
  725. "Unable to reset channel (%u MHz), reset status %d\n",
  726. channel->center_freq, r);
  727. }
  728. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  729. sc->config.txpowlimit, &sc->curtxpow);
  730. if (ath_startrecv(sc) != 0) {
  731. ath_err(common, "Unable to restart recv logic\n");
  732. goto out;
  733. }
  734. if (sc->sc_flags & SC_OP_BEACONS)
  735. ath_beacon_config(sc, NULL); /* restart beacons */
  736. /* Re-Enable interrupts */
  737. ath9k_hw_set_interrupts(ah, ah->imask);
  738. /* Enable LED */
  739. ath9k_hw_cfg_output(ah, ah->led_pin,
  740. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  741. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  742. ieee80211_wake_queues(hw);
  743. out:
  744. spin_unlock_bh(&sc->sc_pcu_lock);
  745. ath9k_ps_restore(sc);
  746. }
  747. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  748. {
  749. struct ath_hw *ah = sc->sc_ah;
  750. struct ieee80211_channel *channel = hw->conf.channel;
  751. int r;
  752. ath9k_ps_wakeup(sc);
  753. spin_lock_bh(&sc->sc_pcu_lock);
  754. ieee80211_stop_queues(hw);
  755. /*
  756. * Keep the LED on when the radio is disabled
  757. * during idle unassociated state.
  758. */
  759. if (!sc->ps_idle) {
  760. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  761. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  762. }
  763. /* Disable interrupts */
  764. ath9k_hw_disable_interrupts(ah);
  765. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  766. ath_stoprecv(sc); /* turn off frame recv */
  767. ath_flushrecv(sc); /* flush recv queue */
  768. if (!ah->curchan)
  769. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  770. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  771. if (r) {
  772. ath_err(ath9k_hw_common(sc->sc_ah),
  773. "Unable to reset channel (%u MHz), reset status %d\n",
  774. channel->center_freq, r);
  775. }
  776. ath9k_hw_phy_disable(ah);
  777. ath9k_hw_configpcipowersave(ah, 1, 1);
  778. spin_unlock_bh(&sc->sc_pcu_lock);
  779. ath9k_ps_restore(sc);
  780. }
  781. int ath_reset(struct ath_softc *sc, bool retry_tx)
  782. {
  783. struct ath_hw *ah = sc->sc_ah;
  784. struct ath_common *common = ath9k_hw_common(ah);
  785. struct ieee80211_hw *hw = sc->hw;
  786. int r;
  787. sc->hw_busy_count = 0;
  788. /* Stop ANI */
  789. del_timer_sync(&common->ani.timer);
  790. ath9k_ps_wakeup(sc);
  791. spin_lock_bh(&sc->sc_pcu_lock);
  792. ieee80211_stop_queues(hw);
  793. ath9k_hw_disable_interrupts(ah);
  794. ath_drain_all_txq(sc, retry_tx);
  795. ath_stoprecv(sc);
  796. ath_flushrecv(sc);
  797. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
  798. if (r)
  799. ath_err(common,
  800. "Unable to reset hardware; reset status %d\n", r);
  801. if (ath_startrecv(sc) != 0)
  802. ath_err(common, "Unable to start recv logic\n");
  803. /*
  804. * We may be doing a reset in response to a request
  805. * that changes the channel so update any state that
  806. * might change as a result.
  807. */
  808. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  809. sc->config.txpowlimit, &sc->curtxpow);
  810. if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
  811. ath_beacon_config(sc, NULL); /* restart beacons */
  812. ath9k_hw_set_interrupts(ah, ah->imask);
  813. if (retry_tx) {
  814. int i;
  815. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  816. if (ATH_TXQ_SETUP(sc, i)) {
  817. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  818. ath_txq_schedule(sc, &sc->tx.txq[i]);
  819. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  820. }
  821. }
  822. }
  823. ieee80211_wake_queues(hw);
  824. spin_unlock_bh(&sc->sc_pcu_lock);
  825. /* Start ANI */
  826. ath_start_ani(common);
  827. ath9k_ps_restore(sc);
  828. return r;
  829. }
  830. /**********************/
  831. /* mac80211 callbacks */
  832. /**********************/
  833. static int ath9k_start(struct ieee80211_hw *hw)
  834. {
  835. struct ath_softc *sc = hw->priv;
  836. struct ath_hw *ah = sc->sc_ah;
  837. struct ath_common *common = ath9k_hw_common(ah);
  838. struct ieee80211_channel *curchan = hw->conf.channel;
  839. struct ath9k_channel *init_channel;
  840. int r;
  841. ath_dbg(common, ATH_DBG_CONFIG,
  842. "Starting driver with initial channel: %d MHz\n",
  843. curchan->center_freq);
  844. mutex_lock(&sc->mutex);
  845. /* setup initial channel */
  846. sc->chan_idx = curchan->hw_value;
  847. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  848. /* Reset SERDES registers */
  849. ath9k_hw_configpcipowersave(ah, 0, 0);
  850. /*
  851. * The basic interface to setting the hardware in a good
  852. * state is ``reset''. On return the hardware is known to
  853. * be powered up and with interrupts disabled. This must
  854. * be followed by initialization of the appropriate bits
  855. * and then setup of the interrupt mask.
  856. */
  857. spin_lock_bh(&sc->sc_pcu_lock);
  858. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  859. if (r) {
  860. ath_err(common,
  861. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  862. r, curchan->center_freq);
  863. spin_unlock_bh(&sc->sc_pcu_lock);
  864. goto mutex_unlock;
  865. }
  866. /*
  867. * This is needed only to setup initial state
  868. * but it's best done after a reset.
  869. */
  870. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  871. sc->config.txpowlimit, &sc->curtxpow);
  872. /*
  873. * Setup the hardware after reset:
  874. * The receive engine is set going.
  875. * Frame transmit is handled entirely
  876. * in the frame output path; there's nothing to do
  877. * here except setup the interrupt mask.
  878. */
  879. if (ath_startrecv(sc) != 0) {
  880. ath_err(common, "Unable to start recv logic\n");
  881. r = -EIO;
  882. spin_unlock_bh(&sc->sc_pcu_lock);
  883. goto mutex_unlock;
  884. }
  885. spin_unlock_bh(&sc->sc_pcu_lock);
  886. /* Setup our intr mask. */
  887. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  888. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  889. ATH9K_INT_GLOBAL;
  890. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  891. ah->imask |= ATH9K_INT_RXHP |
  892. ATH9K_INT_RXLP |
  893. ATH9K_INT_BB_WATCHDOG;
  894. else
  895. ah->imask |= ATH9K_INT_RX;
  896. ah->imask |= ATH9K_INT_GTT;
  897. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  898. ah->imask |= ATH9K_INT_CST;
  899. sc->sc_flags &= ~SC_OP_INVALID;
  900. sc->sc_ah->is_monitoring = false;
  901. /* Disable BMISS interrupt when we're not associated */
  902. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  903. ath9k_hw_set_interrupts(ah, ah->imask);
  904. ieee80211_wake_queues(hw);
  905. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  906. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  907. !ah->btcoex_hw.enabled) {
  908. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  909. AR_STOMP_LOW_WLAN_WGHT);
  910. ath9k_hw_btcoex_enable(ah);
  911. if (common->bus_ops->bt_coex_prep)
  912. common->bus_ops->bt_coex_prep(common);
  913. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  914. ath9k_btcoex_timer_resume(sc);
  915. }
  916. /* User has the option to provide pm-qos value as a module
  917. * parameter rather than using the default value of
  918. * 'ATH9K_PM_QOS_DEFAULT_VALUE'.
  919. */
  920. pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value);
  921. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  922. common->bus_ops->extn_synch_en(common);
  923. mutex_unlock:
  924. mutex_unlock(&sc->mutex);
  925. return r;
  926. }
  927. static int ath9k_tx(struct ieee80211_hw *hw,
  928. struct sk_buff *skb)
  929. {
  930. struct ath_softc *sc = hw->priv;
  931. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  932. struct ath_tx_control txctl;
  933. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  934. if (sc->ps_enabled) {
  935. /*
  936. * mac80211 does not set PM field for normal data frames, so we
  937. * need to update that based on the current PS mode.
  938. */
  939. if (ieee80211_is_data(hdr->frame_control) &&
  940. !ieee80211_is_nullfunc(hdr->frame_control) &&
  941. !ieee80211_has_pm(hdr->frame_control)) {
  942. ath_dbg(common, ATH_DBG_PS,
  943. "Add PM=1 for a TX frame while in PS mode\n");
  944. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  945. }
  946. }
  947. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  948. /*
  949. * We are using PS-Poll and mac80211 can request TX while in
  950. * power save mode. Need to wake up hardware for the TX to be
  951. * completed and if needed, also for RX of buffered frames.
  952. */
  953. ath9k_ps_wakeup(sc);
  954. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  955. ath9k_hw_setrxabort(sc->sc_ah, 0);
  956. if (ieee80211_is_pspoll(hdr->frame_control)) {
  957. ath_dbg(common, ATH_DBG_PS,
  958. "Sending PS-Poll to pick a buffered frame\n");
  959. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  960. } else {
  961. ath_dbg(common, ATH_DBG_PS,
  962. "Wake up to complete TX\n");
  963. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  964. }
  965. /*
  966. * The actual restore operation will happen only after
  967. * the sc_flags bit is cleared. We are just dropping
  968. * the ps_usecount here.
  969. */
  970. ath9k_ps_restore(sc);
  971. }
  972. memset(&txctl, 0, sizeof(struct ath_tx_control));
  973. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  974. ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  975. if (ath_tx_start(hw, skb, &txctl) != 0) {
  976. ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
  977. goto exit;
  978. }
  979. return 0;
  980. exit:
  981. dev_kfree_skb_any(skb);
  982. return 0;
  983. }
  984. static void ath9k_stop(struct ieee80211_hw *hw)
  985. {
  986. struct ath_softc *sc = hw->priv;
  987. struct ath_hw *ah = sc->sc_ah;
  988. struct ath_common *common = ath9k_hw_common(ah);
  989. mutex_lock(&sc->mutex);
  990. if (led_blink)
  991. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  992. cancel_delayed_work_sync(&sc->tx_complete_work);
  993. cancel_delayed_work_sync(&sc->hw_pll_work);
  994. cancel_work_sync(&sc->paprd_work);
  995. cancel_work_sync(&sc->hw_check_work);
  996. if (sc->sc_flags & SC_OP_INVALID) {
  997. ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
  998. mutex_unlock(&sc->mutex);
  999. return;
  1000. }
  1001. /* Ensure HW is awake when we try to shut it down. */
  1002. ath9k_ps_wakeup(sc);
  1003. if (ah->btcoex_hw.enabled) {
  1004. ath9k_hw_btcoex_disable(ah);
  1005. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1006. ath9k_btcoex_timer_pause(sc);
  1007. }
  1008. spin_lock_bh(&sc->sc_pcu_lock);
  1009. /* prevent tasklets to enable interrupts once we disable them */
  1010. ah->imask &= ~ATH9K_INT_GLOBAL;
  1011. /* make sure h/w will not generate any interrupt
  1012. * before setting the invalid flag. */
  1013. ath9k_hw_disable_interrupts(ah);
  1014. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1015. ath_drain_all_txq(sc, false);
  1016. ath_stoprecv(sc);
  1017. ath9k_hw_phy_disable(ah);
  1018. } else
  1019. sc->rx.rxlink = NULL;
  1020. if (sc->rx.frag) {
  1021. dev_kfree_skb_any(sc->rx.frag);
  1022. sc->rx.frag = NULL;
  1023. }
  1024. /* disable HAL and put h/w to sleep */
  1025. ath9k_hw_disable(ah);
  1026. ath9k_hw_configpcipowersave(ah, 1, 1);
  1027. spin_unlock_bh(&sc->sc_pcu_lock);
  1028. /* we can now sync irq and kill any running tasklets, since we already
  1029. * disabled interrupts and not holding a spin lock */
  1030. synchronize_irq(sc->irq);
  1031. tasklet_kill(&sc->intr_tq);
  1032. tasklet_kill(&sc->bcon_tasklet);
  1033. ath9k_ps_restore(sc);
  1034. sc->ps_idle = true;
  1035. ath_radio_disable(sc, hw);
  1036. sc->sc_flags |= SC_OP_INVALID;
  1037. pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE);
  1038. mutex_unlock(&sc->mutex);
  1039. ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
  1040. }
  1041. bool ath9k_uses_beacons(int type)
  1042. {
  1043. switch (type) {
  1044. case NL80211_IFTYPE_AP:
  1045. case NL80211_IFTYPE_ADHOC:
  1046. case NL80211_IFTYPE_MESH_POINT:
  1047. return true;
  1048. default:
  1049. return false;
  1050. }
  1051. }
  1052. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1053. struct ieee80211_vif *vif)
  1054. {
  1055. struct ath_vif *avp = (void *)vif->drv_priv;
  1056. /* Disable SWBA interrupt */
  1057. sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
  1058. ath9k_ps_wakeup(sc);
  1059. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
  1060. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1061. tasklet_kill(&sc->bcon_tasklet);
  1062. ath9k_ps_restore(sc);
  1063. ath_beacon_return(sc, avp);
  1064. sc->sc_flags &= ~SC_OP_BEACONS;
  1065. if (sc->nbcnvifs > 0) {
  1066. /* Re-enable beaconing */
  1067. sc->sc_ah->imask |= ATH9K_INT_SWBA;
  1068. ath9k_ps_wakeup(sc);
  1069. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
  1070. ath9k_ps_restore(sc);
  1071. }
  1072. }
  1073. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1074. {
  1075. struct ath9k_vif_iter_data *iter_data = data;
  1076. int i;
  1077. if (iter_data->hw_macaddr)
  1078. for (i = 0; i < ETH_ALEN; i++)
  1079. iter_data->mask[i] &=
  1080. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1081. switch (vif->type) {
  1082. case NL80211_IFTYPE_AP:
  1083. iter_data->naps++;
  1084. break;
  1085. case NL80211_IFTYPE_STATION:
  1086. iter_data->nstations++;
  1087. break;
  1088. case NL80211_IFTYPE_ADHOC:
  1089. iter_data->nadhocs++;
  1090. break;
  1091. case NL80211_IFTYPE_MESH_POINT:
  1092. iter_data->nmeshes++;
  1093. break;
  1094. case NL80211_IFTYPE_WDS:
  1095. iter_data->nwds++;
  1096. break;
  1097. default:
  1098. iter_data->nothers++;
  1099. break;
  1100. }
  1101. }
  1102. /* Called with sc->mutex held. */
  1103. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1104. struct ieee80211_vif *vif,
  1105. struct ath9k_vif_iter_data *iter_data)
  1106. {
  1107. struct ath_softc *sc = hw->priv;
  1108. struct ath_hw *ah = sc->sc_ah;
  1109. struct ath_common *common = ath9k_hw_common(ah);
  1110. /*
  1111. * Use the hardware MAC address as reference, the hardware uses it
  1112. * together with the BSSID mask when matching addresses.
  1113. */
  1114. memset(iter_data, 0, sizeof(*iter_data));
  1115. iter_data->hw_macaddr = common->macaddr;
  1116. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1117. if (vif)
  1118. ath9k_vif_iter(iter_data, vif->addr, vif);
  1119. /* Get list of all active MAC addresses */
  1120. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1121. iter_data);
  1122. }
  1123. /* Called with sc->mutex held. */
  1124. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1125. struct ieee80211_vif *vif)
  1126. {
  1127. struct ath_softc *sc = hw->priv;
  1128. struct ath_hw *ah = sc->sc_ah;
  1129. struct ath_common *common = ath9k_hw_common(ah);
  1130. struct ath9k_vif_iter_data iter_data;
  1131. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1132. ath9k_ps_wakeup(sc);
  1133. /* Set BSSID mask. */
  1134. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1135. ath_hw_setbssidmask(common);
  1136. /* Set op-mode & TSF */
  1137. if (iter_data.naps > 0) {
  1138. ath9k_hw_set_tsfadjust(ah, 1);
  1139. sc->sc_flags |= SC_OP_TSF_RESET;
  1140. ah->opmode = NL80211_IFTYPE_AP;
  1141. } else {
  1142. ath9k_hw_set_tsfadjust(ah, 0);
  1143. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1144. if (iter_data.nwds + iter_data.nmeshes)
  1145. ah->opmode = NL80211_IFTYPE_AP;
  1146. else if (iter_data.nadhocs)
  1147. ah->opmode = NL80211_IFTYPE_ADHOC;
  1148. else
  1149. ah->opmode = NL80211_IFTYPE_STATION;
  1150. }
  1151. /*
  1152. * Enable MIB interrupts when there are hardware phy counters.
  1153. */
  1154. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1155. if (ah->config.enable_ani)
  1156. ah->imask |= ATH9K_INT_MIB;
  1157. ah->imask |= ATH9K_INT_TSFOOR;
  1158. } else {
  1159. ah->imask &= ~ATH9K_INT_MIB;
  1160. ah->imask &= ~ATH9K_INT_TSFOOR;
  1161. }
  1162. ath9k_hw_set_interrupts(ah, ah->imask);
  1163. ath9k_ps_restore(sc);
  1164. /* Set up ANI */
  1165. if ((iter_data.naps + iter_data.nadhocs) > 0) {
  1166. sc->sc_flags |= SC_OP_ANI_RUN;
  1167. ath_start_ani(common);
  1168. } else {
  1169. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1170. del_timer_sync(&common->ani.timer);
  1171. }
  1172. }
  1173. /* Called with sc->mutex held, vif counts set up properly. */
  1174. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1175. struct ieee80211_vif *vif)
  1176. {
  1177. struct ath_softc *sc = hw->priv;
  1178. ath9k_calculate_summary_state(hw, vif);
  1179. if (ath9k_uses_beacons(vif->type)) {
  1180. int error;
  1181. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1182. /* This may fail because upper levels do not have beacons
  1183. * properly configured yet. That's OK, we assume it
  1184. * will be properly configured and then we will be notified
  1185. * in the info_changed method and set up beacons properly
  1186. * there.
  1187. */
  1188. error = ath_beacon_alloc(sc, vif);
  1189. if (!error)
  1190. ath_beacon_config(sc, vif);
  1191. }
  1192. }
  1193. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1194. struct ieee80211_vif *vif)
  1195. {
  1196. struct ath_softc *sc = hw->priv;
  1197. struct ath_hw *ah = sc->sc_ah;
  1198. struct ath_common *common = ath9k_hw_common(ah);
  1199. struct ath_vif *avp = (void *)vif->drv_priv;
  1200. int ret = 0;
  1201. mutex_lock(&sc->mutex);
  1202. switch (vif->type) {
  1203. case NL80211_IFTYPE_STATION:
  1204. case NL80211_IFTYPE_WDS:
  1205. case NL80211_IFTYPE_ADHOC:
  1206. case NL80211_IFTYPE_AP:
  1207. case NL80211_IFTYPE_MESH_POINT:
  1208. break;
  1209. default:
  1210. ath_err(common, "Interface type %d not yet supported\n",
  1211. vif->type);
  1212. ret = -EOPNOTSUPP;
  1213. goto out;
  1214. }
  1215. if (ath9k_uses_beacons(vif->type)) {
  1216. if (sc->nbcnvifs >= ATH_BCBUF) {
  1217. ath_err(common, "Not enough beacon buffers when adding"
  1218. " new interface of type: %i\n",
  1219. vif->type);
  1220. ret = -ENOBUFS;
  1221. goto out;
  1222. }
  1223. }
  1224. if ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1225. sc->nvifs > 0) {
  1226. ath_err(common, "Cannot create ADHOC interface when other"
  1227. " interfaces already exist.\n");
  1228. ret = -EINVAL;
  1229. goto out;
  1230. }
  1231. ath_dbg(common, ATH_DBG_CONFIG,
  1232. "Attach a VIF of type: %d\n", vif->type);
  1233. /* Set the VIF opmode */
  1234. avp->av_opmode = vif->type;
  1235. avp->av_bslot = -1;
  1236. sc->nvifs++;
  1237. ath9k_do_vif_add_setup(hw, vif);
  1238. out:
  1239. mutex_unlock(&sc->mutex);
  1240. return ret;
  1241. }
  1242. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1243. struct ieee80211_vif *vif,
  1244. enum nl80211_iftype new_type,
  1245. bool p2p)
  1246. {
  1247. struct ath_softc *sc = hw->priv;
  1248. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1249. int ret = 0;
  1250. ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
  1251. mutex_lock(&sc->mutex);
  1252. /* See if new interface type is valid. */
  1253. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1254. (sc->nvifs > 1)) {
  1255. ath_err(common, "When using ADHOC, it must be the only"
  1256. " interface.\n");
  1257. ret = -EINVAL;
  1258. goto out;
  1259. }
  1260. if (ath9k_uses_beacons(new_type) &&
  1261. !ath9k_uses_beacons(vif->type)) {
  1262. if (sc->nbcnvifs >= ATH_BCBUF) {
  1263. ath_err(common, "No beacon slot available\n");
  1264. ret = -ENOBUFS;
  1265. goto out;
  1266. }
  1267. }
  1268. /* Clean up old vif stuff */
  1269. if (ath9k_uses_beacons(vif->type))
  1270. ath9k_reclaim_beacon(sc, vif);
  1271. /* Add new settings */
  1272. vif->type = new_type;
  1273. vif->p2p = p2p;
  1274. ath9k_do_vif_add_setup(hw, vif);
  1275. out:
  1276. mutex_unlock(&sc->mutex);
  1277. return ret;
  1278. }
  1279. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1280. struct ieee80211_vif *vif)
  1281. {
  1282. struct ath_softc *sc = hw->priv;
  1283. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1284. ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1285. mutex_lock(&sc->mutex);
  1286. sc->nvifs--;
  1287. /* Reclaim beacon resources */
  1288. if (ath9k_uses_beacons(vif->type))
  1289. ath9k_reclaim_beacon(sc, vif);
  1290. ath9k_calculate_summary_state(hw, NULL);
  1291. mutex_unlock(&sc->mutex);
  1292. }
  1293. static void ath9k_enable_ps(struct ath_softc *sc)
  1294. {
  1295. struct ath_hw *ah = sc->sc_ah;
  1296. sc->ps_enabled = true;
  1297. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1298. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1299. ah->imask |= ATH9K_INT_TIM_TIMER;
  1300. ath9k_hw_set_interrupts(ah, ah->imask);
  1301. }
  1302. ath9k_hw_setrxabort(ah, 1);
  1303. }
  1304. }
  1305. static void ath9k_disable_ps(struct ath_softc *sc)
  1306. {
  1307. struct ath_hw *ah = sc->sc_ah;
  1308. sc->ps_enabled = false;
  1309. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1310. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1311. ath9k_hw_setrxabort(ah, 0);
  1312. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1313. PS_WAIT_FOR_CAB |
  1314. PS_WAIT_FOR_PSPOLL_DATA |
  1315. PS_WAIT_FOR_TX_ACK);
  1316. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1317. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1318. ath9k_hw_set_interrupts(ah, ah->imask);
  1319. }
  1320. }
  1321. }
  1322. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1323. {
  1324. struct ath_softc *sc = hw->priv;
  1325. struct ath_hw *ah = sc->sc_ah;
  1326. struct ath_common *common = ath9k_hw_common(ah);
  1327. struct ieee80211_conf *conf = &hw->conf;
  1328. bool disable_radio = false;
  1329. mutex_lock(&sc->mutex);
  1330. /*
  1331. * Leave this as the first check because we need to turn on the
  1332. * radio if it was disabled before prior to processing the rest
  1333. * of the changes. Likewise we must only disable the radio towards
  1334. * the end.
  1335. */
  1336. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1337. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1338. if (!sc->ps_idle) {
  1339. ath_radio_enable(sc, hw);
  1340. ath_dbg(common, ATH_DBG_CONFIG,
  1341. "not-idle: enabling radio\n");
  1342. } else {
  1343. disable_radio = true;
  1344. }
  1345. }
  1346. /*
  1347. * We just prepare to enable PS. We have to wait until our AP has
  1348. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1349. * those ACKs and end up retransmitting the same null data frames.
  1350. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1351. */
  1352. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1353. unsigned long flags;
  1354. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1355. if (conf->flags & IEEE80211_CONF_PS)
  1356. ath9k_enable_ps(sc);
  1357. else
  1358. ath9k_disable_ps(sc);
  1359. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1360. }
  1361. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1362. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1363. ath_dbg(common, ATH_DBG_CONFIG,
  1364. "Monitor mode is enabled\n");
  1365. sc->sc_ah->is_monitoring = true;
  1366. } else {
  1367. ath_dbg(common, ATH_DBG_CONFIG,
  1368. "Monitor mode is disabled\n");
  1369. sc->sc_ah->is_monitoring = false;
  1370. }
  1371. }
  1372. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1373. struct ieee80211_channel *curchan = hw->conf.channel;
  1374. int pos = curchan->hw_value;
  1375. int old_pos = -1;
  1376. unsigned long flags;
  1377. if (ah->curchan)
  1378. old_pos = ah->curchan - &ah->channels[0];
  1379. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1380. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1381. else
  1382. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1383. ath_dbg(common, ATH_DBG_CONFIG,
  1384. "Set channel: %d MHz type: %d\n",
  1385. curchan->center_freq, conf->channel_type);
  1386. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1387. curchan, conf->channel_type);
  1388. /* update survey stats for the old channel before switching */
  1389. spin_lock_irqsave(&common->cc_lock, flags);
  1390. ath_update_survey_stats(sc);
  1391. spin_unlock_irqrestore(&common->cc_lock, flags);
  1392. /*
  1393. * If the operating channel changes, change the survey in-use flags
  1394. * along with it.
  1395. * Reset the survey data for the new channel, unless we're switching
  1396. * back to the operating channel from an off-channel operation.
  1397. */
  1398. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1399. sc->cur_survey != &sc->survey[pos]) {
  1400. if (sc->cur_survey)
  1401. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1402. sc->cur_survey = &sc->survey[pos];
  1403. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1404. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1405. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1406. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1407. }
  1408. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1409. ath_err(common, "Unable to set channel\n");
  1410. mutex_unlock(&sc->mutex);
  1411. return -EINVAL;
  1412. }
  1413. /*
  1414. * The most recent snapshot of channel->noisefloor for the old
  1415. * channel is only available after the hardware reset. Copy it to
  1416. * the survey stats now.
  1417. */
  1418. if (old_pos >= 0)
  1419. ath_update_survey_nf(sc, old_pos);
  1420. }
  1421. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1422. ath_dbg(common, ATH_DBG_CONFIG,
  1423. "Set power: %d\n", conf->power_level);
  1424. sc->config.txpowlimit = 2 * conf->power_level;
  1425. ath9k_ps_wakeup(sc);
  1426. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1427. sc->config.txpowlimit, &sc->curtxpow);
  1428. ath9k_ps_restore(sc);
  1429. }
  1430. if (disable_radio) {
  1431. ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1432. ath_radio_disable(sc, hw);
  1433. }
  1434. mutex_unlock(&sc->mutex);
  1435. return 0;
  1436. }
  1437. #define SUPPORTED_FILTERS \
  1438. (FIF_PROMISC_IN_BSS | \
  1439. FIF_ALLMULTI | \
  1440. FIF_CONTROL | \
  1441. FIF_PSPOLL | \
  1442. FIF_OTHER_BSS | \
  1443. FIF_BCN_PRBRESP_PROMISC | \
  1444. FIF_PROBE_REQ | \
  1445. FIF_FCSFAIL)
  1446. /* FIXME: sc->sc_full_reset ? */
  1447. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1448. unsigned int changed_flags,
  1449. unsigned int *total_flags,
  1450. u64 multicast)
  1451. {
  1452. struct ath_softc *sc = hw->priv;
  1453. u32 rfilt;
  1454. changed_flags &= SUPPORTED_FILTERS;
  1455. *total_flags &= SUPPORTED_FILTERS;
  1456. sc->rx.rxfilter = *total_flags;
  1457. ath9k_ps_wakeup(sc);
  1458. rfilt = ath_calcrxfilter(sc);
  1459. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1460. ath9k_ps_restore(sc);
  1461. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1462. "Set HW RX filter: 0x%x\n", rfilt);
  1463. }
  1464. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1465. struct ieee80211_vif *vif,
  1466. struct ieee80211_sta *sta)
  1467. {
  1468. struct ath_softc *sc = hw->priv;
  1469. ath_node_attach(sc, sta);
  1470. return 0;
  1471. }
  1472. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1473. struct ieee80211_vif *vif,
  1474. struct ieee80211_sta *sta)
  1475. {
  1476. struct ath_softc *sc = hw->priv;
  1477. ath_node_detach(sc, sta);
  1478. return 0;
  1479. }
  1480. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1481. const struct ieee80211_tx_queue_params *params)
  1482. {
  1483. struct ath_softc *sc = hw->priv;
  1484. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1485. struct ath_txq *txq;
  1486. struct ath9k_tx_queue_info qi;
  1487. int ret = 0;
  1488. if (queue >= WME_NUM_AC)
  1489. return 0;
  1490. txq = sc->tx.txq_map[queue];
  1491. mutex_lock(&sc->mutex);
  1492. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1493. qi.tqi_aifs = params->aifs;
  1494. qi.tqi_cwmin = params->cw_min;
  1495. qi.tqi_cwmax = params->cw_max;
  1496. qi.tqi_burstTime = params->txop;
  1497. ath_dbg(common, ATH_DBG_CONFIG,
  1498. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1499. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1500. params->cw_max, params->txop);
  1501. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1502. if (ret)
  1503. ath_err(common, "TXQ Update failed\n");
  1504. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1505. if (queue == WME_AC_BE && !ret)
  1506. ath_beaconq_config(sc);
  1507. mutex_unlock(&sc->mutex);
  1508. return ret;
  1509. }
  1510. static int ath9k_set_key(struct ieee80211_hw *hw,
  1511. enum set_key_cmd cmd,
  1512. struct ieee80211_vif *vif,
  1513. struct ieee80211_sta *sta,
  1514. struct ieee80211_key_conf *key)
  1515. {
  1516. struct ath_softc *sc = hw->priv;
  1517. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1518. int ret = 0;
  1519. if (ath9k_modparam_nohwcrypt)
  1520. return -ENOSPC;
  1521. mutex_lock(&sc->mutex);
  1522. ath9k_ps_wakeup(sc);
  1523. ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1524. switch (cmd) {
  1525. case SET_KEY:
  1526. ret = ath_key_config(common, vif, sta, key);
  1527. if (ret >= 0) {
  1528. key->hw_key_idx = ret;
  1529. /* push IV and Michael MIC generation to stack */
  1530. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1531. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1532. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1533. if (sc->sc_ah->sw_mgmt_crypto &&
  1534. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1535. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1536. ret = 0;
  1537. }
  1538. break;
  1539. case DISABLE_KEY:
  1540. ath_key_delete(common, key);
  1541. break;
  1542. default:
  1543. ret = -EINVAL;
  1544. }
  1545. ath9k_ps_restore(sc);
  1546. mutex_unlock(&sc->mutex);
  1547. return ret;
  1548. }
  1549. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1550. struct ieee80211_vif *vif,
  1551. struct ieee80211_bss_conf *bss_conf,
  1552. u32 changed)
  1553. {
  1554. struct ath_softc *sc = hw->priv;
  1555. struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
  1556. struct ath_hw *ah = sc->sc_ah;
  1557. struct ath_common *common = ath9k_hw_common(ah);
  1558. struct ath_vif *avp = (void *)vif->drv_priv;
  1559. int slottime;
  1560. int error;
  1561. mutex_lock(&sc->mutex);
  1562. if (changed & BSS_CHANGED_BSSID) {
  1563. /* Set BSSID */
  1564. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1565. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1566. common->curaid = 0;
  1567. ath9k_hw_write_associd(ah);
  1568. /* Set aggregation protection mode parameters */
  1569. sc->config.ath_aggr_prot = 0;
  1570. ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
  1571. common->curbssid, common->curaid);
  1572. /* need to reconfigure the beacon */
  1573. sc->sc_flags &= ~SC_OP_BEACONS ;
  1574. }
  1575. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1576. if ((changed & BSS_CHANGED_BEACON) ||
  1577. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1578. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1579. error = ath_beacon_alloc(sc, vif);
  1580. if (!error)
  1581. ath_beacon_config(sc, vif);
  1582. }
  1583. if (changed & BSS_CHANGED_ERP_SLOT) {
  1584. if (bss_conf->use_short_slot)
  1585. slottime = 9;
  1586. else
  1587. slottime = 20;
  1588. if (vif->type == NL80211_IFTYPE_AP) {
  1589. /*
  1590. * Defer update, so that connected stations can adjust
  1591. * their settings at the same time.
  1592. * See beacon.c for more details
  1593. */
  1594. sc->beacon.slottime = slottime;
  1595. sc->beacon.updateslot = UPDATE;
  1596. } else {
  1597. ah->slottime = slottime;
  1598. ath9k_hw_init_global_settings(ah);
  1599. }
  1600. }
  1601. /* Disable transmission of beacons */
  1602. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1603. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1604. if (changed & BSS_CHANGED_BEACON_INT) {
  1605. cur_conf->beacon_interval = bss_conf->beacon_int;
  1606. /*
  1607. * In case of AP mode, the HW TSF has to be reset
  1608. * when the beacon interval changes.
  1609. */
  1610. if (vif->type == NL80211_IFTYPE_AP) {
  1611. sc->sc_flags |= SC_OP_TSF_RESET;
  1612. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1613. error = ath_beacon_alloc(sc, vif);
  1614. if (!error)
  1615. ath_beacon_config(sc, vif);
  1616. } else {
  1617. ath_beacon_config(sc, vif);
  1618. }
  1619. }
  1620. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1621. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1622. bss_conf->use_short_preamble);
  1623. if (bss_conf->use_short_preamble)
  1624. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1625. else
  1626. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1627. }
  1628. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1629. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1630. bss_conf->use_cts_prot);
  1631. if (bss_conf->use_cts_prot &&
  1632. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1633. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1634. else
  1635. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1636. }
  1637. if (changed & BSS_CHANGED_ASSOC) {
  1638. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1639. bss_conf->assoc);
  1640. ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
  1641. }
  1642. mutex_unlock(&sc->mutex);
  1643. }
  1644. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1645. {
  1646. struct ath_softc *sc = hw->priv;
  1647. u64 tsf;
  1648. mutex_lock(&sc->mutex);
  1649. ath9k_ps_wakeup(sc);
  1650. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1651. ath9k_ps_restore(sc);
  1652. mutex_unlock(&sc->mutex);
  1653. return tsf;
  1654. }
  1655. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1656. {
  1657. struct ath_softc *sc = hw->priv;
  1658. mutex_lock(&sc->mutex);
  1659. ath9k_ps_wakeup(sc);
  1660. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1661. ath9k_ps_restore(sc);
  1662. mutex_unlock(&sc->mutex);
  1663. }
  1664. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1665. {
  1666. struct ath_softc *sc = hw->priv;
  1667. mutex_lock(&sc->mutex);
  1668. ath9k_ps_wakeup(sc);
  1669. ath9k_hw_reset_tsf(sc->sc_ah);
  1670. ath9k_ps_restore(sc);
  1671. mutex_unlock(&sc->mutex);
  1672. }
  1673. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1674. struct ieee80211_vif *vif,
  1675. enum ieee80211_ampdu_mlme_action action,
  1676. struct ieee80211_sta *sta,
  1677. u16 tid, u16 *ssn, u8 buf_size)
  1678. {
  1679. struct ath_softc *sc = hw->priv;
  1680. int ret = 0;
  1681. local_bh_disable();
  1682. switch (action) {
  1683. case IEEE80211_AMPDU_RX_START:
  1684. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1685. ret = -ENOTSUPP;
  1686. break;
  1687. case IEEE80211_AMPDU_RX_STOP:
  1688. break;
  1689. case IEEE80211_AMPDU_TX_START:
  1690. if (!(sc->sc_flags & SC_OP_TXAGGR))
  1691. return -EOPNOTSUPP;
  1692. ath9k_ps_wakeup(sc);
  1693. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1694. if (!ret)
  1695. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1696. ath9k_ps_restore(sc);
  1697. break;
  1698. case IEEE80211_AMPDU_TX_STOP:
  1699. ath9k_ps_wakeup(sc);
  1700. ath_tx_aggr_stop(sc, sta, tid);
  1701. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1702. ath9k_ps_restore(sc);
  1703. break;
  1704. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1705. ath9k_ps_wakeup(sc);
  1706. ath_tx_aggr_resume(sc, sta, tid);
  1707. ath9k_ps_restore(sc);
  1708. break;
  1709. default:
  1710. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1711. }
  1712. local_bh_enable();
  1713. return ret;
  1714. }
  1715. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1716. struct survey_info *survey)
  1717. {
  1718. struct ath_softc *sc = hw->priv;
  1719. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1720. struct ieee80211_supported_band *sband;
  1721. struct ieee80211_channel *chan;
  1722. unsigned long flags;
  1723. int pos;
  1724. spin_lock_irqsave(&common->cc_lock, flags);
  1725. if (idx == 0)
  1726. ath_update_survey_stats(sc);
  1727. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1728. if (sband && idx >= sband->n_channels) {
  1729. idx -= sband->n_channels;
  1730. sband = NULL;
  1731. }
  1732. if (!sband)
  1733. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1734. if (!sband || idx >= sband->n_channels) {
  1735. spin_unlock_irqrestore(&common->cc_lock, flags);
  1736. return -ENOENT;
  1737. }
  1738. chan = &sband->channels[idx];
  1739. pos = chan->hw_value;
  1740. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1741. survey->channel = chan;
  1742. spin_unlock_irqrestore(&common->cc_lock, flags);
  1743. return 0;
  1744. }
  1745. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1746. {
  1747. struct ath_softc *sc = hw->priv;
  1748. struct ath_hw *ah = sc->sc_ah;
  1749. mutex_lock(&sc->mutex);
  1750. ah->coverage_class = coverage_class;
  1751. ath9k_hw_init_global_settings(ah);
  1752. mutex_unlock(&sc->mutex);
  1753. }
  1754. struct ieee80211_ops ath9k_ops = {
  1755. .tx = ath9k_tx,
  1756. .start = ath9k_start,
  1757. .stop = ath9k_stop,
  1758. .add_interface = ath9k_add_interface,
  1759. .change_interface = ath9k_change_interface,
  1760. .remove_interface = ath9k_remove_interface,
  1761. .config = ath9k_config,
  1762. .configure_filter = ath9k_configure_filter,
  1763. .sta_add = ath9k_sta_add,
  1764. .sta_remove = ath9k_sta_remove,
  1765. .conf_tx = ath9k_conf_tx,
  1766. .bss_info_changed = ath9k_bss_info_changed,
  1767. .set_key = ath9k_set_key,
  1768. .get_tsf = ath9k_get_tsf,
  1769. .set_tsf = ath9k_set_tsf,
  1770. .reset_tsf = ath9k_reset_tsf,
  1771. .ampdu_action = ath9k_ampdu_action,
  1772. .get_survey = ath9k_get_survey,
  1773. .rfkill_poll = ath9k_rfkill_poll_state,
  1774. .set_coverage_class = ath9k_set_coverage_class,
  1775. };