iwl-4965.c 101 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-eeprom.h"
  40. #include "iwl-dev.h"
  41. #include "iwl-core.h"
  42. #include "iwl-io.h"
  43. #include "iwl-helpers.h"
  44. #include "iwl-calib.h"
  45. #include "iwl-sta.h"
  46. /* module parameters */
  47. static struct iwl_mod_params iwl4965_mod_params = {
  48. .num_of_queues = IWL49_NUM_QUEUES,
  49. .enable_qos = 1,
  50. .amsdu_size_8K = 1,
  51. .restart_fw = 1,
  52. /* the rest are 0 by default */
  53. };
  54. /* check contents of special bootstrap uCode SRAM */
  55. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  56. {
  57. __le32 *image = priv->ucode_boot.v_addr;
  58. u32 len = priv->ucode_boot.len;
  59. u32 reg;
  60. u32 val;
  61. IWL_DEBUG_INFO("Begin verify bsm\n");
  62. /* verify BSM SRAM contents */
  63. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  64. for (reg = BSM_SRAM_LOWER_BOUND;
  65. reg < BSM_SRAM_LOWER_BOUND + len;
  66. reg += sizeof(u32), image++) {
  67. val = iwl_read_prph(priv, reg);
  68. if (val != le32_to_cpu(*image)) {
  69. IWL_ERROR("BSM uCode verification failed at "
  70. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  71. BSM_SRAM_LOWER_BOUND,
  72. reg - BSM_SRAM_LOWER_BOUND, len,
  73. val, le32_to_cpu(*image));
  74. return -EIO;
  75. }
  76. }
  77. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  78. return 0;
  79. }
  80. /**
  81. * iwl4965_load_bsm - Load bootstrap instructions
  82. *
  83. * BSM operation:
  84. *
  85. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  86. * in special SRAM that does not power down during RFKILL. When powering back
  87. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  88. * the bootstrap program into the on-board processor, and starts it.
  89. *
  90. * The bootstrap program loads (via DMA) instructions and data for a new
  91. * program from host DRAM locations indicated by the host driver in the
  92. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  93. * automatically.
  94. *
  95. * When initializing the NIC, the host driver points the BSM to the
  96. * "initialize" uCode image. This uCode sets up some internal data, then
  97. * notifies host via "initialize alive" that it is complete.
  98. *
  99. * The host then replaces the BSM_DRAM_* pointer values to point to the
  100. * normal runtime uCode instructions and a backup uCode data cache buffer
  101. * (filled initially with starting data values for the on-board processor),
  102. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  103. * which begins normal operation.
  104. *
  105. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  106. * the backup data cache in DRAM before SRAM is powered down.
  107. *
  108. * When powering back up, the BSM loads the bootstrap program. This reloads
  109. * the runtime uCode instructions and the backup data cache into SRAM,
  110. * and re-launches the runtime uCode from where it left off.
  111. */
  112. static int iwl4965_load_bsm(struct iwl_priv *priv)
  113. {
  114. __le32 *image = priv->ucode_boot.v_addr;
  115. u32 len = priv->ucode_boot.len;
  116. dma_addr_t pinst;
  117. dma_addr_t pdata;
  118. u32 inst_len;
  119. u32 data_len;
  120. int i;
  121. u32 done;
  122. u32 reg_offset;
  123. int ret;
  124. IWL_DEBUG_INFO("Begin load bsm\n");
  125. priv->ucode_type = UCODE_RT;
  126. /* make sure bootstrap program is no larger than BSM's SRAM size */
  127. if (len > IWL_MAX_BSM_SIZE)
  128. return -EINVAL;
  129. /* Tell bootstrap uCode where to find the "Initialize" uCode
  130. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  131. * NOTE: iwl_init_alive_start() will replace these values,
  132. * after the "initialize" uCode has run, to point to
  133. * runtime/protocol instructions and backup data cache.
  134. */
  135. pinst = priv->ucode_init.p_addr >> 4;
  136. pdata = priv->ucode_init_data.p_addr >> 4;
  137. inst_len = priv->ucode_init.len;
  138. data_len = priv->ucode_init_data.len;
  139. ret = iwl_grab_nic_access(priv);
  140. if (ret)
  141. return ret;
  142. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  143. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  144. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  145. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  146. /* Fill BSM memory with bootstrap instructions */
  147. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  148. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  149. reg_offset += sizeof(u32), image++)
  150. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  151. ret = iwl4965_verify_bsm(priv);
  152. if (ret) {
  153. iwl_release_nic_access(priv);
  154. return ret;
  155. }
  156. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  157. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  158. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
  159. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  160. /* Load bootstrap code into instruction SRAM now,
  161. * to prepare to load "initialize" uCode */
  162. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  163. /* Wait for load of bootstrap uCode to finish */
  164. for (i = 0; i < 100; i++) {
  165. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  166. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  167. break;
  168. udelay(10);
  169. }
  170. if (i < 100)
  171. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  172. else {
  173. IWL_ERROR("BSM write did not complete!\n");
  174. return -EIO;
  175. }
  176. /* Enable future boot loads whenever power management unit triggers it
  177. * (e.g. when powering back up after power-save shutdown) */
  178. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  179. iwl_release_nic_access(priv);
  180. return 0;
  181. }
  182. /**
  183. * iwl4965_set_ucode_ptrs - Set uCode address location
  184. *
  185. * Tell initialization uCode where to find runtime uCode.
  186. *
  187. * BSM registers initially contain pointers to initialization uCode.
  188. * We need to replace them to load runtime uCode inst and data,
  189. * and to save runtime data when powering down.
  190. */
  191. static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
  192. {
  193. dma_addr_t pinst;
  194. dma_addr_t pdata;
  195. unsigned long flags;
  196. int ret = 0;
  197. /* bits 35:4 for 4965 */
  198. pinst = priv->ucode_code.p_addr >> 4;
  199. pdata = priv->ucode_data_backup.p_addr >> 4;
  200. spin_lock_irqsave(&priv->lock, flags);
  201. ret = iwl_grab_nic_access(priv);
  202. if (ret) {
  203. spin_unlock_irqrestore(&priv->lock, flags);
  204. return ret;
  205. }
  206. /* Tell bootstrap uCode where to find image to load */
  207. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  208. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  209. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  210. priv->ucode_data.len);
  211. /* Inst bytecount must be last to set up, bit 31 signals uCode
  212. * that all new ptr/size info is in place */
  213. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  214. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  215. iwl_release_nic_access(priv);
  216. spin_unlock_irqrestore(&priv->lock, flags);
  217. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  218. return ret;
  219. }
  220. /**
  221. * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
  222. *
  223. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  224. *
  225. * The 4965 "initialize" ALIVE reply contains calibration data for:
  226. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  227. * (3945 does not contain this data).
  228. *
  229. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  230. */
  231. static void iwl4965_init_alive_start(struct iwl_priv *priv)
  232. {
  233. /* Check alive response for "valid" sign from uCode */
  234. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  235. /* We had an error bringing up the hardware, so take it
  236. * all the way back down so we can try again */
  237. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  238. goto restart;
  239. }
  240. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  241. * This is a paranoid check, because we would not have gotten the
  242. * "initialize" alive if code weren't properly loaded. */
  243. if (iwl_verify_ucode(priv)) {
  244. /* Runtime instruction load was bad;
  245. * take it all the way back down so we can try again */
  246. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  247. goto restart;
  248. }
  249. /* Calculate temperature */
  250. priv->temperature = iwl4965_get_temperature(priv);
  251. /* Send pointers to protocol/runtime uCode image ... init code will
  252. * load and launch runtime uCode, which will send us another "Alive"
  253. * notification. */
  254. IWL_DEBUG_INFO("Initialization Alive received.\n");
  255. if (iwl4965_set_ucode_ptrs(priv)) {
  256. /* Runtime instruction load won't happen;
  257. * take it all the way back down so we can try again */
  258. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  259. goto restart;
  260. }
  261. return;
  262. restart:
  263. queue_work(priv->workqueue, &priv->restart);
  264. }
  265. static int is_fat_channel(__le32 rxon_flags)
  266. {
  267. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  268. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  269. }
  270. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  271. {
  272. int idx = 0;
  273. /* 4965 HT rate format */
  274. if (rate_n_flags & RATE_MCS_HT_MSK) {
  275. idx = (rate_n_flags & 0xff);
  276. if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  277. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  278. idx += IWL_FIRST_OFDM_RATE;
  279. /* skip 9M not supported in ht*/
  280. if (idx >= IWL_RATE_9M_INDEX)
  281. idx += 1;
  282. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  283. return idx;
  284. /* 4965 legacy rate format, search for match in table */
  285. } else {
  286. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  287. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  288. return idx;
  289. }
  290. return -1;
  291. }
  292. /**
  293. * translate ucode response to mac80211 tx status control values
  294. */
  295. void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  296. struct ieee80211_tx_info *control)
  297. {
  298. int rate_index;
  299. control->antenna_sel_tx =
  300. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  301. if (rate_n_flags & RATE_MCS_HT_MSK)
  302. control->flags |= IEEE80211_TX_CTL_OFDM_HT;
  303. if (rate_n_flags & RATE_MCS_GF_MSK)
  304. control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
  305. if (rate_n_flags & RATE_MCS_FAT_MSK)
  306. control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
  307. if (rate_n_flags & RATE_MCS_DUP_MSK)
  308. control->flags |= IEEE80211_TX_CTL_DUP_DATA;
  309. if (rate_n_flags & RATE_MCS_SGI_MSK)
  310. control->flags |= IEEE80211_TX_CTL_SHORT_GI;
  311. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  312. if (control->band == IEEE80211_BAND_5GHZ)
  313. rate_index -= IWL_FIRST_OFDM_RATE;
  314. control->tx_rate_idx = rate_index;
  315. }
  316. /*
  317. * EEPROM handlers
  318. */
  319. static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
  320. {
  321. u16 eeprom_ver;
  322. u16 calib_ver;
  323. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  324. calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
  325. if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
  326. calib_ver < EEPROM_4965_TX_POWER_VERSION)
  327. goto err;
  328. return 0;
  329. err:
  330. IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
  331. eeprom_ver, EEPROM_4965_EEPROM_VERSION,
  332. calib_ver, EEPROM_4965_TX_POWER_VERSION);
  333. return -EINVAL;
  334. }
  335. int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  336. {
  337. int ret;
  338. unsigned long flags;
  339. spin_lock_irqsave(&priv->lock, flags);
  340. ret = iwl_grab_nic_access(priv);
  341. if (ret) {
  342. spin_unlock_irqrestore(&priv->lock, flags);
  343. return ret;
  344. }
  345. if (src == IWL_PWR_SRC_VAUX) {
  346. u32 val;
  347. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  348. &val);
  349. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
  350. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  351. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  352. ~APMG_PS_CTRL_MSK_PWR_SRC);
  353. }
  354. } else {
  355. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  356. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  357. ~APMG_PS_CTRL_MSK_PWR_SRC);
  358. }
  359. iwl_release_nic_access(priv);
  360. spin_unlock_irqrestore(&priv->lock, flags);
  361. return ret;
  362. }
  363. /*
  364. * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
  365. * must be called under priv->lock and mac access
  366. */
  367. static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
  368. {
  369. iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
  370. }
  371. static int iwl4965_apm_init(struct iwl_priv *priv)
  372. {
  373. int ret = 0;
  374. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  375. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  376. /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  377. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  378. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  379. /* set "initialization complete" bit to move adapter
  380. * D0U* --> D0A* state */
  381. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  382. /* wait for clock stabilization */
  383. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  384. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  385. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  386. if (ret < 0) {
  387. IWL_DEBUG_INFO("Failed to init the card\n");
  388. goto out;
  389. }
  390. ret = iwl_grab_nic_access(priv);
  391. if (ret)
  392. goto out;
  393. /* enable DMA */
  394. iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
  395. APMG_CLK_VAL_BSM_CLK_RQT);
  396. udelay(20);
  397. /* disable L1-Active */
  398. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  399. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  400. iwl_release_nic_access(priv);
  401. out:
  402. return ret;
  403. }
  404. static void iwl4965_nic_config(struct iwl_priv *priv)
  405. {
  406. unsigned long flags;
  407. u32 val;
  408. u16 radio_cfg;
  409. u8 val_link;
  410. spin_lock_irqsave(&priv->lock, flags);
  411. if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
  412. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  413. /* Enable No Snoop field */
  414. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  415. val & ~(1 << 11));
  416. }
  417. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  418. /* L1 is enabled by BIOS */
  419. if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
  420. /* diable L0S disabled L1A enabled */
  421. iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  422. else
  423. /* L0S enabled L1A disabled */
  424. iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  425. radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  426. /* write radio config values to register */
  427. if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
  428. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  429. EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  430. EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  431. EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  432. /* set CSR_HW_CONFIG_REG for uCode use */
  433. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  434. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  435. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  436. priv->calib_info = (struct iwl_eeprom_calib_info *)
  437. iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
  438. spin_unlock_irqrestore(&priv->lock, flags);
  439. }
  440. static int iwl4965_apm_stop_master(struct iwl_priv *priv)
  441. {
  442. int ret = 0;
  443. unsigned long flags;
  444. spin_lock_irqsave(&priv->lock, flags);
  445. /* set stop master bit */
  446. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  447. ret = iwl_poll_bit(priv, CSR_RESET,
  448. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  449. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  450. if (ret < 0)
  451. goto out;
  452. out:
  453. spin_unlock_irqrestore(&priv->lock, flags);
  454. IWL_DEBUG_INFO("stop master\n");
  455. return ret;
  456. }
  457. static void iwl4965_apm_stop(struct iwl_priv *priv)
  458. {
  459. unsigned long flags;
  460. iwl4965_apm_stop_master(priv);
  461. spin_lock_irqsave(&priv->lock, flags);
  462. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  463. udelay(10);
  464. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  465. spin_unlock_irqrestore(&priv->lock, flags);
  466. }
  467. static int iwl4965_apm_reset(struct iwl_priv *priv)
  468. {
  469. int ret = 0;
  470. unsigned long flags;
  471. iwl4965_apm_stop_master(priv);
  472. spin_lock_irqsave(&priv->lock, flags);
  473. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  474. udelay(10);
  475. /* FIXME: put here L1A -L0S w/a */
  476. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  477. ret = iwl_poll_bit(priv, CSR_RESET,
  478. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  479. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  480. if (ret)
  481. goto out;
  482. udelay(10);
  483. ret = iwl_grab_nic_access(priv);
  484. if (ret)
  485. goto out;
  486. /* Enable DMA and BSM Clock */
  487. iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
  488. APMG_CLK_VAL_BSM_CLK_RQT);
  489. udelay(10);
  490. /* disable L1A */
  491. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  492. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  493. iwl_release_nic_access(priv);
  494. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  495. wake_up_interruptible(&priv->wait_command_queue);
  496. out:
  497. spin_unlock_irqrestore(&priv->lock, flags);
  498. return ret;
  499. }
  500. #define REG_RECALIB_PERIOD (60)
  501. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  502. {
  503. struct iwl4965_ct_kill_config cmd;
  504. unsigned long flags;
  505. int ret = 0;
  506. spin_lock_irqsave(&priv->lock, flags);
  507. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  508. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  509. spin_unlock_irqrestore(&priv->lock, flags);
  510. cmd.critical_temperature_R =
  511. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  512. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  513. sizeof(cmd), &cmd);
  514. if (ret)
  515. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  516. else
  517. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
  518. "critical temperature is %d\n",
  519. cmd.critical_temperature_R);
  520. }
  521. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  522. * Called after every association, but this runs only once!
  523. * ... once chain noise is calibrated the first time, it's good forever. */
  524. static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  525. {
  526. struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
  527. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  528. struct iwl4965_calibration_cmd cmd;
  529. memset(&cmd, 0, sizeof(cmd));
  530. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  531. cmd.diff_gain_a = 0;
  532. cmd.diff_gain_b = 0;
  533. cmd.diff_gain_c = 0;
  534. if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  535. sizeof(cmd), &cmd))
  536. IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
  537. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  538. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  539. }
  540. }
  541. static void iwl4965_gain_computation(struct iwl_priv *priv,
  542. u32 *average_noise,
  543. u16 min_average_noise_antenna_i,
  544. u32 min_average_noise)
  545. {
  546. int i, ret;
  547. struct iwl_chain_noise_data *data = &priv->chain_noise_data;
  548. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  549. for (i = 0; i < NUM_RX_CHAINS; i++) {
  550. s32 delta_g = 0;
  551. if (!(data->disconn_array[i]) &&
  552. (data->delta_gain_code[i] ==
  553. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  554. delta_g = average_noise[i] - min_average_noise;
  555. data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
  556. data->delta_gain_code[i] =
  557. min(data->delta_gain_code[i],
  558. (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
  559. data->delta_gain_code[i] =
  560. (data->delta_gain_code[i] | (1 << 2));
  561. } else {
  562. data->delta_gain_code[i] = 0;
  563. }
  564. }
  565. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  566. data->delta_gain_code[0],
  567. data->delta_gain_code[1],
  568. data->delta_gain_code[2]);
  569. /* Differential gain gets sent to uCode only once */
  570. if (!data->radio_write) {
  571. struct iwl4965_calibration_cmd cmd;
  572. data->radio_write = 1;
  573. memset(&cmd, 0, sizeof(cmd));
  574. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  575. cmd.diff_gain_a = data->delta_gain_code[0];
  576. cmd.diff_gain_b = data->delta_gain_code[1];
  577. cmd.diff_gain_c = data->delta_gain_code[2];
  578. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  579. sizeof(cmd), &cmd);
  580. if (ret)
  581. IWL_DEBUG_CALIB("fail sending cmd "
  582. "REPLY_PHY_CALIBRATION_CMD \n");
  583. /* TODO we might want recalculate
  584. * rx_chain in rxon cmd */
  585. /* Mark so we run this algo only once! */
  586. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  587. }
  588. data->chain_noise_a = 0;
  589. data->chain_noise_b = 0;
  590. data->chain_noise_c = 0;
  591. data->chain_signal_a = 0;
  592. data->chain_signal_b = 0;
  593. data->chain_signal_c = 0;
  594. data->beacon_count = 0;
  595. }
  596. static void iwl4965_bg_txpower_work(struct work_struct *work)
  597. {
  598. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  599. txpower_work);
  600. /* If a scan happened to start before we got here
  601. * then just return; the statistics notification will
  602. * kick off another scheduled work to compensate for
  603. * any temperature delta we missed here. */
  604. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  605. test_bit(STATUS_SCANNING, &priv->status))
  606. return;
  607. mutex_lock(&priv->mutex);
  608. /* Regardless of if we are assocaited, we must reconfigure the
  609. * TX power since frames can be sent on non-radar channels while
  610. * not associated */
  611. iwl4965_hw_reg_send_txpower(priv);
  612. /* Update last_temperature to keep is_calib_needed from running
  613. * when it isn't needed... */
  614. priv->last_temperature = priv->temperature;
  615. mutex_unlock(&priv->mutex);
  616. }
  617. /*
  618. * Acquire priv->lock before calling this function !
  619. */
  620. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  621. {
  622. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  623. (index & 0xff) | (txq_id << 8));
  624. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  625. }
  626. /**
  627. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  628. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  629. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  630. *
  631. * NOTE: Acquire priv->lock before calling this function !
  632. */
  633. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  634. struct iwl_tx_queue *txq,
  635. int tx_fifo_id, int scd_retry)
  636. {
  637. int txq_id = txq->q.id;
  638. /* Find out whether to activate Tx queue */
  639. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  640. /* Set up and activate */
  641. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  642. (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  643. (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  644. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  645. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  646. IWL49_SCD_QUEUE_STTS_REG_MSK);
  647. txq->sched_retry = scd_retry;
  648. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  649. active ? "Activate" : "Deactivate",
  650. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  651. }
  652. static const u16 default_queue_to_tx_fifo[] = {
  653. IWL_TX_FIFO_AC3,
  654. IWL_TX_FIFO_AC2,
  655. IWL_TX_FIFO_AC1,
  656. IWL_TX_FIFO_AC0,
  657. IWL49_CMD_FIFO_NUM,
  658. IWL_TX_FIFO_HCCA_1,
  659. IWL_TX_FIFO_HCCA_2
  660. };
  661. int iwl4965_alive_notify(struct iwl_priv *priv)
  662. {
  663. u32 a;
  664. int i = 0;
  665. unsigned long flags;
  666. int ret;
  667. spin_lock_irqsave(&priv->lock, flags);
  668. ret = iwl_grab_nic_access(priv);
  669. if (ret) {
  670. spin_unlock_irqrestore(&priv->lock, flags);
  671. return ret;
  672. }
  673. /* Clear 4965's internal Tx Scheduler data base */
  674. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  675. a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
  676. for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  677. iwl_write_targ_mem(priv, a, 0);
  678. for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  679. iwl_write_targ_mem(priv, a, 0);
  680. for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
  681. iwl_write_targ_mem(priv, a, 0);
  682. /* Tel 4965 where to find Tx byte count tables */
  683. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  684. (priv->shared_phys +
  685. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  686. /* Disable chain mode for all queues */
  687. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  688. /* Initialize each Tx queue (including the command queue) */
  689. for (i = 0; i < priv->hw_params.max_txq_num; i++) {
  690. /* TFD circular buffer read/write indexes */
  691. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  692. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  693. /* Max Tx Window size for Scheduler-ACK mode */
  694. iwl_write_targ_mem(priv, priv->scd_base_addr +
  695. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  696. (SCD_WIN_SIZE <<
  697. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  698. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  699. /* Frame limit */
  700. iwl_write_targ_mem(priv, priv->scd_base_addr +
  701. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  702. sizeof(u32),
  703. (SCD_FRAME_LIMIT <<
  704. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  705. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  706. }
  707. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  708. (1 << priv->hw_params.max_txq_num) - 1);
  709. /* Activate all Tx DMA/FIFO channels */
  710. priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
  711. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  712. /* Map each Tx/cmd queue to its corresponding fifo */
  713. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  714. int ac = default_queue_to_tx_fifo[i];
  715. iwl_txq_ctx_activate(priv, i);
  716. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  717. }
  718. iwl_release_nic_access(priv);
  719. spin_unlock_irqrestore(&priv->lock, flags);
  720. return ret;
  721. }
  722. static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
  723. .min_nrg_cck = 97,
  724. .max_nrg_cck = 0,
  725. .auto_corr_min_ofdm = 85,
  726. .auto_corr_min_ofdm_mrc = 170,
  727. .auto_corr_min_ofdm_x1 = 105,
  728. .auto_corr_min_ofdm_mrc_x1 = 220,
  729. .auto_corr_max_ofdm = 120,
  730. .auto_corr_max_ofdm_mrc = 210,
  731. .auto_corr_max_ofdm_x1 = 140,
  732. .auto_corr_max_ofdm_mrc_x1 = 270,
  733. .auto_corr_min_cck = 125,
  734. .auto_corr_max_cck = 200,
  735. .auto_corr_min_cck_mrc = 200,
  736. .auto_corr_max_cck_mrc = 400,
  737. .nrg_th_cck = 100,
  738. .nrg_th_ofdm = 100,
  739. };
  740. /**
  741. * iwl4965_hw_set_hw_params
  742. *
  743. * Called when initializing driver
  744. */
  745. int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
  746. {
  747. if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
  748. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  749. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  750. IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
  751. return -EINVAL;
  752. }
  753. priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
  754. priv->hw_params.first_ampdu_q = IWL49_FIRST_AMPDU_QUEUE;
  755. priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
  756. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  757. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  758. if (priv->cfg->mod_params->amsdu_size_8K)
  759. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  760. else
  761. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  762. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  763. priv->hw_params.max_stations = IWL4965_STATION_COUNT;
  764. priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
  765. priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
  766. priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
  767. priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
  768. priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
  769. priv->hw_params.tx_chains_num = 2;
  770. priv->hw_params.rx_chains_num = 2;
  771. priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
  772. priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
  773. priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
  774. priv->hw_params.sens = &iwl4965_sensitivity;
  775. return 0;
  776. }
  777. /* set card power command */
  778. static int iwl4965_set_power(struct iwl_priv *priv,
  779. void *cmd)
  780. {
  781. int ret = 0;
  782. ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
  783. sizeof(struct iwl4965_powertable_cmd),
  784. cmd, NULL);
  785. return ret;
  786. }
  787. int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  788. {
  789. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  790. return -EINVAL;
  791. }
  792. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  793. {
  794. s32 sign = 1;
  795. if (num < 0) {
  796. sign = -sign;
  797. num = -num;
  798. }
  799. if (denom < 0) {
  800. sign = -sign;
  801. denom = -denom;
  802. }
  803. *res = 1;
  804. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  805. return 1;
  806. }
  807. /**
  808. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  809. *
  810. * Determines power supply voltage compensation for txpower calculations.
  811. * Returns number of 1/2-dB steps to subtract from gain table index,
  812. * to compensate for difference between power supply voltage during
  813. * factory measurements, vs. current power supply voltage.
  814. *
  815. * Voltage indication is higher for lower voltage.
  816. * Lower voltage requires more gain (lower gain table index).
  817. */
  818. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  819. s32 current_voltage)
  820. {
  821. s32 comp = 0;
  822. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  823. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  824. return 0;
  825. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  826. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  827. if (current_voltage > eeprom_voltage)
  828. comp *= 2;
  829. if ((comp < -2) || (comp > 2))
  830. comp = 0;
  831. return comp;
  832. }
  833. static const struct iwl_channel_info *
  834. iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
  835. enum ieee80211_band band, u16 channel)
  836. {
  837. const struct iwl_channel_info *ch_info;
  838. ch_info = iwl_get_channel_info(priv, band, channel);
  839. if (!is_channel_valid(ch_info))
  840. return NULL;
  841. return ch_info;
  842. }
  843. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  844. {
  845. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  846. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  847. return CALIB_CH_GROUP_5;
  848. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  849. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  850. return CALIB_CH_GROUP_1;
  851. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  852. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  853. return CALIB_CH_GROUP_2;
  854. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  855. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  856. return CALIB_CH_GROUP_3;
  857. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  858. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  859. return CALIB_CH_GROUP_4;
  860. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  861. return -1;
  862. }
  863. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  864. {
  865. s32 b = -1;
  866. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  867. if (priv->calib_info->band_info[b].ch_from == 0)
  868. continue;
  869. if ((channel >= priv->calib_info->band_info[b].ch_from)
  870. && (channel <= priv->calib_info->band_info[b].ch_to))
  871. break;
  872. }
  873. return b;
  874. }
  875. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  876. {
  877. s32 val;
  878. if (x2 == x1)
  879. return y1;
  880. else {
  881. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  882. return val + y2;
  883. }
  884. }
  885. /**
  886. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  887. *
  888. * Interpolates factory measurements from the two sample channels within a
  889. * sub-band, to apply to channel of interest. Interpolation is proportional to
  890. * differences in channel frequencies, which is proportional to differences
  891. * in channel number.
  892. */
  893. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  894. struct iwl_eeprom_calib_ch_info *chan_info)
  895. {
  896. s32 s = -1;
  897. u32 c;
  898. u32 m;
  899. const struct iwl_eeprom_calib_measure *m1;
  900. const struct iwl_eeprom_calib_measure *m2;
  901. struct iwl_eeprom_calib_measure *omeas;
  902. u32 ch_i1;
  903. u32 ch_i2;
  904. s = iwl4965_get_sub_band(priv, channel);
  905. if (s >= EEPROM_TX_POWER_BANDS) {
  906. IWL_ERROR("Tx Power can not find channel %d ", channel);
  907. return -1;
  908. }
  909. ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
  910. ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
  911. chan_info->ch_num = (u8) channel;
  912. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  913. channel, s, ch_i1, ch_i2);
  914. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  915. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  916. m1 = &(priv->calib_info->band_info[s].ch1.
  917. measurements[c][m]);
  918. m2 = &(priv->calib_info->band_info[s].ch2.
  919. measurements[c][m]);
  920. omeas = &(chan_info->measurements[c][m]);
  921. omeas->actual_pow =
  922. (u8) iwl4965_interpolate_value(channel, ch_i1,
  923. m1->actual_pow,
  924. ch_i2,
  925. m2->actual_pow);
  926. omeas->gain_idx =
  927. (u8) iwl4965_interpolate_value(channel, ch_i1,
  928. m1->gain_idx, ch_i2,
  929. m2->gain_idx);
  930. omeas->temperature =
  931. (u8) iwl4965_interpolate_value(channel, ch_i1,
  932. m1->temperature,
  933. ch_i2,
  934. m2->temperature);
  935. omeas->pa_det =
  936. (s8) iwl4965_interpolate_value(channel, ch_i1,
  937. m1->pa_det, ch_i2,
  938. m2->pa_det);
  939. IWL_DEBUG_TXPOWER
  940. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  941. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  942. IWL_DEBUG_TXPOWER
  943. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  944. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  945. IWL_DEBUG_TXPOWER
  946. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  947. m1->pa_det, m2->pa_det, omeas->pa_det);
  948. IWL_DEBUG_TXPOWER
  949. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  950. m1->temperature, m2->temperature,
  951. omeas->temperature);
  952. }
  953. }
  954. return 0;
  955. }
  956. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  957. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  958. static s32 back_off_table[] = {
  959. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  960. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  961. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  962. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  963. 10 /* CCK */
  964. };
  965. /* Thermal compensation values for txpower for various frequency ranges ...
  966. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  967. static struct iwl4965_txpower_comp_entry {
  968. s32 degrees_per_05db_a;
  969. s32 degrees_per_05db_a_denom;
  970. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  971. {9, 2}, /* group 0 5.2, ch 34-43 */
  972. {4, 1}, /* group 1 5.2, ch 44-70 */
  973. {4, 1}, /* group 2 5.2, ch 71-124 */
  974. {4, 1}, /* group 3 5.2, ch 125-200 */
  975. {3, 1} /* group 4 2.4, ch all */
  976. };
  977. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  978. {
  979. if (!band) {
  980. if ((rate_power_index & 7) <= 4)
  981. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  982. }
  983. return MIN_TX_GAIN_INDEX;
  984. }
  985. struct gain_entry {
  986. u8 dsp;
  987. u8 radio;
  988. };
  989. static const struct gain_entry gain_table[2][108] = {
  990. /* 5.2GHz power gain index table */
  991. {
  992. {123, 0x3F}, /* highest txpower */
  993. {117, 0x3F},
  994. {110, 0x3F},
  995. {104, 0x3F},
  996. {98, 0x3F},
  997. {110, 0x3E},
  998. {104, 0x3E},
  999. {98, 0x3E},
  1000. {110, 0x3D},
  1001. {104, 0x3D},
  1002. {98, 0x3D},
  1003. {110, 0x3C},
  1004. {104, 0x3C},
  1005. {98, 0x3C},
  1006. {110, 0x3B},
  1007. {104, 0x3B},
  1008. {98, 0x3B},
  1009. {110, 0x3A},
  1010. {104, 0x3A},
  1011. {98, 0x3A},
  1012. {110, 0x39},
  1013. {104, 0x39},
  1014. {98, 0x39},
  1015. {110, 0x38},
  1016. {104, 0x38},
  1017. {98, 0x38},
  1018. {110, 0x37},
  1019. {104, 0x37},
  1020. {98, 0x37},
  1021. {110, 0x36},
  1022. {104, 0x36},
  1023. {98, 0x36},
  1024. {110, 0x35},
  1025. {104, 0x35},
  1026. {98, 0x35},
  1027. {110, 0x34},
  1028. {104, 0x34},
  1029. {98, 0x34},
  1030. {110, 0x33},
  1031. {104, 0x33},
  1032. {98, 0x33},
  1033. {110, 0x32},
  1034. {104, 0x32},
  1035. {98, 0x32},
  1036. {110, 0x31},
  1037. {104, 0x31},
  1038. {98, 0x31},
  1039. {110, 0x30},
  1040. {104, 0x30},
  1041. {98, 0x30},
  1042. {110, 0x25},
  1043. {104, 0x25},
  1044. {98, 0x25},
  1045. {110, 0x24},
  1046. {104, 0x24},
  1047. {98, 0x24},
  1048. {110, 0x23},
  1049. {104, 0x23},
  1050. {98, 0x23},
  1051. {110, 0x22},
  1052. {104, 0x18},
  1053. {98, 0x18},
  1054. {110, 0x17},
  1055. {104, 0x17},
  1056. {98, 0x17},
  1057. {110, 0x16},
  1058. {104, 0x16},
  1059. {98, 0x16},
  1060. {110, 0x15},
  1061. {104, 0x15},
  1062. {98, 0x15},
  1063. {110, 0x14},
  1064. {104, 0x14},
  1065. {98, 0x14},
  1066. {110, 0x13},
  1067. {104, 0x13},
  1068. {98, 0x13},
  1069. {110, 0x12},
  1070. {104, 0x08},
  1071. {98, 0x08},
  1072. {110, 0x07},
  1073. {104, 0x07},
  1074. {98, 0x07},
  1075. {110, 0x06},
  1076. {104, 0x06},
  1077. {98, 0x06},
  1078. {110, 0x05},
  1079. {104, 0x05},
  1080. {98, 0x05},
  1081. {110, 0x04},
  1082. {104, 0x04},
  1083. {98, 0x04},
  1084. {110, 0x03},
  1085. {104, 0x03},
  1086. {98, 0x03},
  1087. {110, 0x02},
  1088. {104, 0x02},
  1089. {98, 0x02},
  1090. {110, 0x01},
  1091. {104, 0x01},
  1092. {98, 0x01},
  1093. {110, 0x00},
  1094. {104, 0x00},
  1095. {98, 0x00},
  1096. {93, 0x00},
  1097. {88, 0x00},
  1098. {83, 0x00},
  1099. {78, 0x00},
  1100. },
  1101. /* 2.4GHz power gain index table */
  1102. {
  1103. {110, 0x3f}, /* highest txpower */
  1104. {104, 0x3f},
  1105. {98, 0x3f},
  1106. {110, 0x3e},
  1107. {104, 0x3e},
  1108. {98, 0x3e},
  1109. {110, 0x3d},
  1110. {104, 0x3d},
  1111. {98, 0x3d},
  1112. {110, 0x3c},
  1113. {104, 0x3c},
  1114. {98, 0x3c},
  1115. {110, 0x3b},
  1116. {104, 0x3b},
  1117. {98, 0x3b},
  1118. {110, 0x3a},
  1119. {104, 0x3a},
  1120. {98, 0x3a},
  1121. {110, 0x39},
  1122. {104, 0x39},
  1123. {98, 0x39},
  1124. {110, 0x38},
  1125. {104, 0x38},
  1126. {98, 0x38},
  1127. {110, 0x37},
  1128. {104, 0x37},
  1129. {98, 0x37},
  1130. {110, 0x36},
  1131. {104, 0x36},
  1132. {98, 0x36},
  1133. {110, 0x35},
  1134. {104, 0x35},
  1135. {98, 0x35},
  1136. {110, 0x34},
  1137. {104, 0x34},
  1138. {98, 0x34},
  1139. {110, 0x33},
  1140. {104, 0x33},
  1141. {98, 0x33},
  1142. {110, 0x32},
  1143. {104, 0x32},
  1144. {98, 0x32},
  1145. {110, 0x31},
  1146. {104, 0x31},
  1147. {98, 0x31},
  1148. {110, 0x30},
  1149. {104, 0x30},
  1150. {98, 0x30},
  1151. {110, 0x6},
  1152. {104, 0x6},
  1153. {98, 0x6},
  1154. {110, 0x5},
  1155. {104, 0x5},
  1156. {98, 0x5},
  1157. {110, 0x4},
  1158. {104, 0x4},
  1159. {98, 0x4},
  1160. {110, 0x3},
  1161. {104, 0x3},
  1162. {98, 0x3},
  1163. {110, 0x2},
  1164. {104, 0x2},
  1165. {98, 0x2},
  1166. {110, 0x1},
  1167. {104, 0x1},
  1168. {98, 0x1},
  1169. {110, 0x0},
  1170. {104, 0x0},
  1171. {98, 0x0},
  1172. {97, 0},
  1173. {96, 0},
  1174. {95, 0},
  1175. {94, 0},
  1176. {93, 0},
  1177. {92, 0},
  1178. {91, 0},
  1179. {90, 0},
  1180. {89, 0},
  1181. {88, 0},
  1182. {87, 0},
  1183. {86, 0},
  1184. {85, 0},
  1185. {84, 0},
  1186. {83, 0},
  1187. {82, 0},
  1188. {81, 0},
  1189. {80, 0},
  1190. {79, 0},
  1191. {78, 0},
  1192. {77, 0},
  1193. {76, 0},
  1194. {75, 0},
  1195. {74, 0},
  1196. {73, 0},
  1197. {72, 0},
  1198. {71, 0},
  1199. {70, 0},
  1200. {69, 0},
  1201. {68, 0},
  1202. {67, 0},
  1203. {66, 0},
  1204. {65, 0},
  1205. {64, 0},
  1206. {63, 0},
  1207. {62, 0},
  1208. {61, 0},
  1209. {60, 0},
  1210. {59, 0},
  1211. }
  1212. };
  1213. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1214. u8 is_fat, u8 ctrl_chan_high,
  1215. struct iwl4965_tx_power_db *tx_power_tbl)
  1216. {
  1217. u8 saturation_power;
  1218. s32 target_power;
  1219. s32 user_target_power;
  1220. s32 power_limit;
  1221. s32 current_temp;
  1222. s32 reg_limit;
  1223. s32 current_regulatory;
  1224. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1225. int i;
  1226. int c;
  1227. const struct iwl_channel_info *ch_info = NULL;
  1228. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1229. const struct iwl_eeprom_calib_measure *measurement;
  1230. s16 voltage;
  1231. s32 init_voltage;
  1232. s32 voltage_compensation;
  1233. s32 degrees_per_05db_num;
  1234. s32 degrees_per_05db_denom;
  1235. s32 factory_temp;
  1236. s32 temperature_comp[2];
  1237. s32 factory_gain_index[2];
  1238. s32 factory_actual_pwr[2];
  1239. s32 power_index;
  1240. /* Sanity check requested level (dBm) */
  1241. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  1242. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  1243. priv->user_txpower_limit);
  1244. return -EINVAL;
  1245. }
  1246. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  1247. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  1248. priv->user_txpower_limit);
  1249. return -EINVAL;
  1250. }
  1251. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  1252. * are used for indexing into txpower table) */
  1253. user_target_power = 2 * priv->user_txpower_limit;
  1254. /* Get current (RXON) channel, band, width */
  1255. ch_info =
  1256. iwl4965_get_channel_txpower_info(priv, priv->band, channel);
  1257. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  1258. is_fat);
  1259. if (!ch_info)
  1260. return -EINVAL;
  1261. /* get txatten group, used to select 1) thermal txpower adjustment
  1262. * and 2) mimo txpower balance between Tx chains. */
  1263. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1264. if (txatten_grp < 0)
  1265. return -EINVAL;
  1266. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  1267. channel, txatten_grp);
  1268. if (is_fat) {
  1269. if (ctrl_chan_high)
  1270. channel -= 2;
  1271. else
  1272. channel += 2;
  1273. }
  1274. /* hardware txpower limits ...
  1275. * saturation (clipping distortion) txpowers are in half-dBm */
  1276. if (band)
  1277. saturation_power = priv->calib_info->saturation_power24;
  1278. else
  1279. saturation_power = priv->calib_info->saturation_power52;
  1280. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1281. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1282. if (band)
  1283. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1284. else
  1285. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1286. }
  1287. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1288. * max_power_avg values are in dBm, convert * 2 */
  1289. if (is_fat)
  1290. reg_limit = ch_info->fat_max_power_avg * 2;
  1291. else
  1292. reg_limit = ch_info->max_power_avg * 2;
  1293. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1294. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1295. if (band)
  1296. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1297. else
  1298. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1299. }
  1300. /* Interpolate txpower calibration values for this channel,
  1301. * based on factory calibration tests on spaced channels. */
  1302. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1303. /* calculate tx gain adjustment based on power supply voltage */
  1304. voltage = priv->calib_info->voltage;
  1305. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1306. voltage_compensation =
  1307. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1308. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  1309. init_voltage,
  1310. voltage, voltage_compensation);
  1311. /* get current temperature (Celsius) */
  1312. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1313. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1314. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1315. /* select thermal txpower adjustment params, based on channel group
  1316. * (same frequency group used for mimo txatten adjustment) */
  1317. degrees_per_05db_num =
  1318. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1319. degrees_per_05db_denom =
  1320. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  1321. /* get per-chain txpower values from factory measurements */
  1322. for (c = 0; c < 2; c++) {
  1323. measurement = &ch_eeprom_info.measurements[c][1];
  1324. /* txgain adjustment (in half-dB steps) based on difference
  1325. * between factory and current temperature */
  1326. factory_temp = measurement->temperature;
  1327. iwl4965_math_div_round((current_temp - factory_temp) *
  1328. degrees_per_05db_denom,
  1329. degrees_per_05db_num,
  1330. &temperature_comp[c]);
  1331. factory_gain_index[c] = measurement->gain_idx;
  1332. factory_actual_pwr[c] = measurement->actual_pow;
  1333. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  1334. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  1335. "curr tmp %d, comp %d steps\n",
  1336. factory_temp, current_temp,
  1337. temperature_comp[c]);
  1338. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  1339. factory_gain_index[c],
  1340. factory_actual_pwr[c]);
  1341. }
  1342. /* for each of 33 bit-rates (including 1 for CCK) */
  1343. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  1344. u8 is_mimo_rate;
  1345. union iwl4965_tx_power_dual_stream tx_power;
  1346. /* for mimo, reduce each chain's txpower by half
  1347. * (3dB, 6 steps), so total output power is regulatory
  1348. * compliant. */
  1349. if (i & 0x8) {
  1350. current_regulatory = reg_limit -
  1351. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  1352. is_mimo_rate = 1;
  1353. } else {
  1354. current_regulatory = reg_limit;
  1355. is_mimo_rate = 0;
  1356. }
  1357. /* find txpower limit, either hardware or regulatory */
  1358. power_limit = saturation_power - back_off_table[i];
  1359. if (power_limit > current_regulatory)
  1360. power_limit = current_regulatory;
  1361. /* reduce user's txpower request if necessary
  1362. * for this rate on this channel */
  1363. target_power = user_target_power;
  1364. if (target_power > power_limit)
  1365. target_power = power_limit;
  1366. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  1367. i, saturation_power - back_off_table[i],
  1368. current_regulatory, user_target_power,
  1369. target_power);
  1370. /* for each of 2 Tx chains (radio transmitters) */
  1371. for (c = 0; c < 2; c++) {
  1372. s32 atten_value;
  1373. if (is_mimo_rate)
  1374. atten_value =
  1375. (s32)le32_to_cpu(priv->card_alive_init.
  1376. tx_atten[txatten_grp][c]);
  1377. else
  1378. atten_value = 0;
  1379. /* calculate index; higher index means lower txpower */
  1380. power_index = (u8) (factory_gain_index[c] -
  1381. (target_power -
  1382. factory_actual_pwr[c]) -
  1383. temperature_comp[c] -
  1384. voltage_compensation +
  1385. atten_value);
  1386. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  1387. power_index); */
  1388. if (power_index < get_min_power_index(i, band))
  1389. power_index = get_min_power_index(i, band);
  1390. /* adjust 5 GHz index to support negative indexes */
  1391. if (!band)
  1392. power_index += 9;
  1393. /* CCK, rate 32, reduce txpower for CCK */
  1394. if (i == POWER_TABLE_CCK_ENTRY)
  1395. power_index +=
  1396. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  1397. /* stay within the table! */
  1398. if (power_index > 107) {
  1399. IWL_WARNING("txpower index %d > 107\n",
  1400. power_index);
  1401. power_index = 107;
  1402. }
  1403. if (power_index < 0) {
  1404. IWL_WARNING("txpower index %d < 0\n",
  1405. power_index);
  1406. power_index = 0;
  1407. }
  1408. /* fill txpower command for this rate/chain */
  1409. tx_power.s.radio_tx_gain[c] =
  1410. gain_table[band][power_index].radio;
  1411. tx_power.s.dsp_predis_atten[c] =
  1412. gain_table[band][power_index].dsp;
  1413. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  1414. "gain 0x%02x dsp %d\n",
  1415. c, atten_value, power_index,
  1416. tx_power.s.radio_tx_gain[c],
  1417. tx_power.s.dsp_predis_atten[c]);
  1418. }/* for each chain */
  1419. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  1420. }/* for each rate */
  1421. return 0;
  1422. }
  1423. /**
  1424. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  1425. *
  1426. * Uses the active RXON for channel, band, and characteristics (fat, high)
  1427. * The power limit is taken from priv->user_txpower_limit.
  1428. */
  1429. int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
  1430. {
  1431. struct iwl4965_txpowertable_cmd cmd = { 0 };
  1432. int ret;
  1433. u8 band = 0;
  1434. u8 is_fat = 0;
  1435. u8 ctrl_chan_high = 0;
  1436. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1437. /* If this gets hit a lot, switch it to a BUG() and catch
  1438. * the stack trace to find out who is calling this during
  1439. * a scan. */
  1440. IWL_WARNING("TX Power requested while scanning!\n");
  1441. return -EAGAIN;
  1442. }
  1443. band = priv->band == IEEE80211_BAND_2GHZ;
  1444. is_fat = is_fat_channel(priv->active_rxon.flags);
  1445. if (is_fat &&
  1446. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1447. ctrl_chan_high = 1;
  1448. cmd.band = band;
  1449. cmd.channel = priv->active_rxon.channel;
  1450. ret = iwl4965_fill_txpower_tbl(priv, band,
  1451. le16_to_cpu(priv->active_rxon.channel),
  1452. is_fat, ctrl_chan_high, &cmd.tx_power);
  1453. if (ret)
  1454. goto out;
  1455. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  1456. out:
  1457. return ret;
  1458. }
  1459. static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
  1460. {
  1461. int ret = 0;
  1462. struct iwl4965_rxon_assoc_cmd rxon_assoc;
  1463. const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
  1464. const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
  1465. if ((rxon1->flags == rxon2->flags) &&
  1466. (rxon1->filter_flags == rxon2->filter_flags) &&
  1467. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  1468. (rxon1->ofdm_ht_single_stream_basic_rates ==
  1469. rxon2->ofdm_ht_single_stream_basic_rates) &&
  1470. (rxon1->ofdm_ht_dual_stream_basic_rates ==
  1471. rxon2->ofdm_ht_dual_stream_basic_rates) &&
  1472. (rxon1->rx_chain == rxon2->rx_chain) &&
  1473. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  1474. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  1475. return 0;
  1476. }
  1477. rxon_assoc.flags = priv->staging_rxon.flags;
  1478. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  1479. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  1480. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  1481. rxon_assoc.reserved = 0;
  1482. rxon_assoc.ofdm_ht_single_stream_basic_rates =
  1483. priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
  1484. rxon_assoc.ofdm_ht_dual_stream_basic_rates =
  1485. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
  1486. rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
  1487. ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
  1488. sizeof(rxon_assoc), &rxon_assoc, NULL);
  1489. if (ret)
  1490. return ret;
  1491. return ret;
  1492. }
  1493. int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  1494. {
  1495. int rc;
  1496. u8 band = 0;
  1497. u8 is_fat = 0;
  1498. u8 ctrl_chan_high = 0;
  1499. struct iwl4965_channel_switch_cmd cmd = { 0 };
  1500. const struct iwl_channel_info *ch_info;
  1501. band = priv->band == IEEE80211_BAND_2GHZ;
  1502. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1503. is_fat = is_fat_channel(priv->staging_rxon.flags);
  1504. if (is_fat &&
  1505. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1506. ctrl_chan_high = 1;
  1507. cmd.band = band;
  1508. cmd.expect_beacon = 0;
  1509. cmd.channel = cpu_to_le16(channel);
  1510. cmd.rxon_flags = priv->active_rxon.flags;
  1511. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  1512. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  1513. if (ch_info)
  1514. cmd.expect_beacon = is_channel_radar(ch_info);
  1515. else
  1516. cmd.expect_beacon = 1;
  1517. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  1518. ctrl_chan_high, &cmd.tx_power);
  1519. if (rc) {
  1520. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  1521. return rc;
  1522. }
  1523. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  1524. return rc;
  1525. }
  1526. static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
  1527. {
  1528. struct iwl4965_shared *s = priv->shared_virt;
  1529. return le32_to_cpu(s->rb_closed) & 0xFFF;
  1530. }
  1531. int iwl4965_hw_get_temperature(struct iwl_priv *priv)
  1532. {
  1533. return priv->temperature;
  1534. }
  1535. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  1536. struct iwl_frame *frame, u8 rate)
  1537. {
  1538. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  1539. unsigned int frame_size;
  1540. tx_beacon_cmd = &frame->u.beacon;
  1541. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  1542. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  1543. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1544. frame_size = iwl4965_fill_beacon_frame(priv,
  1545. tx_beacon_cmd->frame,
  1546. iwl_bcast_addr,
  1547. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  1548. BUG_ON(frame_size > MAX_MPDU_SIZE);
  1549. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  1550. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  1551. tx_beacon_cmd->tx.rate_n_flags =
  1552. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  1553. else
  1554. tx_beacon_cmd->tx.rate_n_flags =
  1555. iwl4965_hw_set_rate_n_flags(rate, 0);
  1556. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  1557. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  1558. return (sizeof(*tx_beacon_cmd) + frame_size);
  1559. }
  1560. static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
  1561. {
  1562. priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
  1563. sizeof(struct iwl4965_shared),
  1564. &priv->shared_phys);
  1565. if (!priv->shared_virt)
  1566. return -ENOMEM;
  1567. memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
  1568. priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
  1569. return 0;
  1570. }
  1571. static void iwl4965_free_shared_mem(struct iwl_priv *priv)
  1572. {
  1573. if (priv->shared_virt)
  1574. pci_free_consistent(priv->pci_dev,
  1575. sizeof(struct iwl4965_shared),
  1576. priv->shared_virt,
  1577. priv->shared_phys);
  1578. }
  1579. /**
  1580. * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  1581. */
  1582. static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
  1583. struct iwl_tx_queue *txq,
  1584. u16 byte_cnt)
  1585. {
  1586. int len;
  1587. int txq_id = txq->q.id;
  1588. struct iwl4965_shared *shared_data = priv->shared_virt;
  1589. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  1590. /* Set up byte count within first 256 entries */
  1591. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1592. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  1593. /* If within first 64 entries, duplicate at end */
  1594. if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
  1595. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1596. tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
  1597. byte_cnt, len);
  1598. }
  1599. /**
  1600. * sign_extend - Sign extend a value using specified bit as sign-bit
  1601. *
  1602. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  1603. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  1604. *
  1605. * @param oper value to sign extend
  1606. * @param index 0 based bit index (0<=index<32) to sign bit
  1607. */
  1608. static s32 sign_extend(u32 oper, int index)
  1609. {
  1610. u8 shift = 31 - index;
  1611. return (s32)(oper << shift) >> shift;
  1612. }
  1613. /**
  1614. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  1615. * @statistics: Provides the temperature reading from the uCode
  1616. *
  1617. * A return of <0 indicates bogus data in the statistics
  1618. */
  1619. int iwl4965_get_temperature(const struct iwl_priv *priv)
  1620. {
  1621. s32 temperature;
  1622. s32 vt;
  1623. s32 R1, R2, R3;
  1624. u32 R4;
  1625. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  1626. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  1627. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  1628. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  1629. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  1630. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  1631. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  1632. } else {
  1633. IWL_DEBUG_TEMP("Running temperature calibration\n");
  1634. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  1635. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  1636. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  1637. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  1638. }
  1639. /*
  1640. * Temperature is only 23 bits, so sign extend out to 32.
  1641. *
  1642. * NOTE If we haven't received a statistics notification yet
  1643. * with an updated temperature, use R4 provided to us in the
  1644. * "initialize" ALIVE response.
  1645. */
  1646. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  1647. vt = sign_extend(R4, 23);
  1648. else
  1649. vt = sign_extend(
  1650. le32_to_cpu(priv->statistics.general.temperature), 23);
  1651. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  1652. R1, R2, R3, vt);
  1653. if (R3 == R1) {
  1654. IWL_ERROR("Calibration conflict R1 == R3\n");
  1655. return -1;
  1656. }
  1657. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  1658. * Add offset to center the adjustment around 0 degrees Centigrade. */
  1659. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  1660. temperature /= (R3 - R1);
  1661. temperature = (temperature * 97) / 100 +
  1662. TEMPERATURE_CALIB_KELVIN_OFFSET;
  1663. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  1664. KELVIN_TO_CELSIUS(temperature));
  1665. return temperature;
  1666. }
  1667. /* Adjust Txpower only if temperature variance is greater than threshold. */
  1668. #define IWL_TEMPERATURE_THRESHOLD 3
  1669. /**
  1670. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  1671. *
  1672. * If the temperature changed has changed sufficiently, then a recalibration
  1673. * is needed.
  1674. *
  1675. * Assumes caller will replace priv->last_temperature once calibration
  1676. * executed.
  1677. */
  1678. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  1679. {
  1680. int temp_diff;
  1681. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  1682. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  1683. return 0;
  1684. }
  1685. temp_diff = priv->temperature - priv->last_temperature;
  1686. /* get absolute value */
  1687. if (temp_diff < 0) {
  1688. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  1689. temp_diff = -temp_diff;
  1690. } else if (temp_diff == 0)
  1691. IWL_DEBUG_POWER("Same temp, \n");
  1692. else
  1693. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  1694. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  1695. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  1696. return 0;
  1697. }
  1698. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  1699. return 1;
  1700. }
  1701. /* Calculate noise level, based on measurements during network silence just
  1702. * before arriving beacon. This measurement can be done only if we know
  1703. * exactly when to expect beacons, therefore only when we're associated. */
  1704. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  1705. {
  1706. struct statistics_rx_non_phy *rx_info
  1707. = &(priv->statistics.rx.general);
  1708. int num_active_rx = 0;
  1709. int total_silence = 0;
  1710. int bcn_silence_a =
  1711. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  1712. int bcn_silence_b =
  1713. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  1714. int bcn_silence_c =
  1715. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  1716. if (bcn_silence_a) {
  1717. total_silence += bcn_silence_a;
  1718. num_active_rx++;
  1719. }
  1720. if (bcn_silence_b) {
  1721. total_silence += bcn_silence_b;
  1722. num_active_rx++;
  1723. }
  1724. if (bcn_silence_c) {
  1725. total_silence += bcn_silence_c;
  1726. num_active_rx++;
  1727. }
  1728. /* Average among active antennas */
  1729. if (num_active_rx)
  1730. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  1731. else
  1732. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1733. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  1734. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  1735. priv->last_rx_noise);
  1736. }
  1737. void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
  1738. struct iwl_rx_mem_buffer *rxb)
  1739. {
  1740. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1741. int change;
  1742. s32 temp;
  1743. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  1744. (int)sizeof(priv->statistics), pkt->len);
  1745. change = ((priv->statistics.general.temperature !=
  1746. pkt->u.stats.general.temperature) ||
  1747. ((priv->statistics.flag &
  1748. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  1749. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  1750. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  1751. set_bit(STATUS_STATISTICS, &priv->status);
  1752. /* Reschedule the statistics timer to occur in
  1753. * REG_RECALIB_PERIOD seconds to ensure we get a
  1754. * thermal update even if the uCode doesn't give
  1755. * us one */
  1756. mod_timer(&priv->statistics_periodic, jiffies +
  1757. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  1758. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1759. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  1760. iwl4965_rx_calc_noise(priv);
  1761. queue_work(priv->workqueue, &priv->run_time_calib_work);
  1762. }
  1763. iwl_leds_background(priv);
  1764. /* If the hardware hasn't reported a change in
  1765. * temperature then don't bother computing a
  1766. * calibrated temperature value */
  1767. if (!change)
  1768. return;
  1769. temp = iwl4965_get_temperature(priv);
  1770. if (temp < 0)
  1771. return;
  1772. if (priv->temperature != temp) {
  1773. if (priv->temperature)
  1774. IWL_DEBUG_TEMP("Temperature changed "
  1775. "from %dC to %dC\n",
  1776. KELVIN_TO_CELSIUS(priv->temperature),
  1777. KELVIN_TO_CELSIUS(temp));
  1778. else
  1779. IWL_DEBUG_TEMP("Temperature "
  1780. "initialized to %dC\n",
  1781. KELVIN_TO_CELSIUS(temp));
  1782. }
  1783. priv->temperature = temp;
  1784. set_bit(STATUS_TEMPERATURE, &priv->status);
  1785. if (!priv->disable_tx_power_cal &&
  1786. unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1787. iwl4965_is_temp_calib_needed(priv))
  1788. queue_work(priv->workqueue, &priv->txpower_work);
  1789. }
  1790. static void iwl4965_add_radiotap(struct iwl_priv *priv,
  1791. struct sk_buff *skb,
  1792. struct iwl4965_rx_phy_res *rx_start,
  1793. struct ieee80211_rx_status *stats,
  1794. u32 ampdu_status)
  1795. {
  1796. s8 signal = stats->signal;
  1797. s8 noise = 0;
  1798. int rate = stats->rate_idx;
  1799. u64 tsf = stats->mactime;
  1800. __le16 antenna;
  1801. __le16 phy_flags_hw = rx_start->phy_flags;
  1802. struct iwl4965_rt_rx_hdr {
  1803. struct ieee80211_radiotap_header rt_hdr;
  1804. __le64 rt_tsf; /* TSF */
  1805. u8 rt_flags; /* radiotap packet flags */
  1806. u8 rt_rate; /* rate in 500kb/s */
  1807. __le16 rt_channelMHz; /* channel in MHz */
  1808. __le16 rt_chbitmask; /* channel bitfield */
  1809. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  1810. s8 rt_dbmnoise;
  1811. u8 rt_antenna; /* antenna number */
  1812. } __attribute__ ((packed)) *iwl4965_rt;
  1813. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  1814. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  1815. if (net_ratelimit())
  1816. printk(KERN_ERR "not enough headroom [%d] for "
  1817. "radiotap head [%zd]\n",
  1818. skb_headroom(skb), sizeof(*iwl4965_rt));
  1819. return;
  1820. }
  1821. /* put radiotap header in front of 802.11 header and data */
  1822. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  1823. /* initialise radiotap header */
  1824. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  1825. iwl4965_rt->rt_hdr.it_pad = 0;
  1826. /* total header + data */
  1827. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  1828. &iwl4965_rt->rt_hdr.it_len);
  1829. /* Indicate all the fields we add to the radiotap header */
  1830. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  1831. (1 << IEEE80211_RADIOTAP_FLAGS) |
  1832. (1 << IEEE80211_RADIOTAP_RATE) |
  1833. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  1834. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  1835. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  1836. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  1837. &iwl4965_rt->rt_hdr.it_present);
  1838. /* Zero the flags, we'll add to them as we go */
  1839. iwl4965_rt->rt_flags = 0;
  1840. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  1841. iwl4965_rt->rt_dbmsignal = signal;
  1842. iwl4965_rt->rt_dbmnoise = noise;
  1843. /* Convert the channel frequency and set the flags */
  1844. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  1845. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  1846. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1847. IEEE80211_CHAN_5GHZ),
  1848. &iwl4965_rt->rt_chbitmask);
  1849. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  1850. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  1851. IEEE80211_CHAN_2GHZ),
  1852. &iwl4965_rt->rt_chbitmask);
  1853. else /* 802.11g */
  1854. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1855. IEEE80211_CHAN_2GHZ),
  1856. &iwl4965_rt->rt_chbitmask);
  1857. if (rate == -1)
  1858. iwl4965_rt->rt_rate = 0;
  1859. else
  1860. iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
  1861. /*
  1862. * "antenna number"
  1863. *
  1864. * It seems that the antenna field in the phy flags value
  1865. * is actually a bitfield. This is undefined by radiotap,
  1866. * it wants an actual antenna number but I always get "7"
  1867. * for most legacy frames I receive indicating that the
  1868. * same frame was received on all three RX chains.
  1869. *
  1870. * I think this field should be removed in favour of a
  1871. * new 802.11n radiotap field "RX chains" that is defined
  1872. * as a bitmask.
  1873. */
  1874. antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
  1875. iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
  1876. /* set the preamble flag if appropriate */
  1877. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1878. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  1879. stats->flag |= RX_FLAG_RADIOTAP;
  1880. }
  1881. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  1882. {
  1883. /* 0 - mgmt, 1 - cnt, 2 - data */
  1884. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  1885. priv->rx_stats[idx].cnt++;
  1886. priv->rx_stats[idx].bytes += len;
  1887. }
  1888. /*
  1889. * returns non-zero if packet should be dropped
  1890. */
  1891. static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
  1892. struct ieee80211_hdr *hdr,
  1893. u32 decrypt_res,
  1894. struct ieee80211_rx_status *stats)
  1895. {
  1896. u16 fc = le16_to_cpu(hdr->frame_control);
  1897. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  1898. return 0;
  1899. if (!(fc & IEEE80211_FCTL_PROTECTED))
  1900. return 0;
  1901. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  1902. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  1903. case RX_RES_STATUS_SEC_TYPE_TKIP:
  1904. /* The uCode has got a bad phase 1 Key, pushes the packet.
  1905. * Decryption will be done in SW. */
  1906. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1907. RX_RES_STATUS_BAD_KEY_TTAK)
  1908. break;
  1909. case RX_RES_STATUS_SEC_TYPE_WEP:
  1910. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1911. RX_RES_STATUS_BAD_ICV_MIC) {
  1912. /* bad ICV, the packet is destroyed since the
  1913. * decryption is inplace, drop it */
  1914. IWL_DEBUG_RX("Packet destroyed\n");
  1915. return -1;
  1916. }
  1917. case RX_RES_STATUS_SEC_TYPE_CCMP:
  1918. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1919. RX_RES_STATUS_DECRYPT_OK) {
  1920. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  1921. stats->flag |= RX_FLAG_DECRYPTED;
  1922. }
  1923. break;
  1924. default:
  1925. break;
  1926. }
  1927. return 0;
  1928. }
  1929. static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  1930. {
  1931. u32 decrypt_out = 0;
  1932. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  1933. RX_RES_STATUS_STATION_FOUND)
  1934. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  1935. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  1936. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  1937. /* packet was not encrypted */
  1938. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  1939. RX_RES_STATUS_SEC_TYPE_NONE)
  1940. return decrypt_out;
  1941. /* packet was encrypted with unknown alg */
  1942. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  1943. RX_RES_STATUS_SEC_TYPE_ERR)
  1944. return decrypt_out;
  1945. /* decryption was not done in HW */
  1946. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  1947. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  1948. return decrypt_out;
  1949. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  1950. case RX_RES_STATUS_SEC_TYPE_CCMP:
  1951. /* alg is CCM: check MIC only */
  1952. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  1953. /* Bad MIC */
  1954. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  1955. else
  1956. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  1957. break;
  1958. case RX_RES_STATUS_SEC_TYPE_TKIP:
  1959. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  1960. /* Bad TTAK */
  1961. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  1962. break;
  1963. }
  1964. /* fall through if TTAK OK */
  1965. default:
  1966. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  1967. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  1968. else
  1969. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  1970. break;
  1971. };
  1972. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  1973. decrypt_in, decrypt_out);
  1974. return decrypt_out;
  1975. }
  1976. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  1977. int include_phy,
  1978. struct iwl_rx_mem_buffer *rxb,
  1979. struct ieee80211_rx_status *stats)
  1980. {
  1981. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1982. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  1983. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  1984. struct ieee80211_hdr *hdr;
  1985. u16 len;
  1986. __le32 *rx_end;
  1987. unsigned int skblen;
  1988. u32 ampdu_status;
  1989. u32 ampdu_status_legacy;
  1990. if (!include_phy && priv->last_phy_res[0])
  1991. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  1992. if (!rx_start) {
  1993. IWL_ERROR("MPDU frame without a PHY data\n");
  1994. return;
  1995. }
  1996. if (include_phy) {
  1997. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  1998. rx_start->cfg_phy_cnt);
  1999. len = le16_to_cpu(rx_start->byte_count);
  2000. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  2001. sizeof(struct iwl4965_rx_phy_res) +
  2002. rx_start->cfg_phy_cnt + len);
  2003. } else {
  2004. struct iwl4965_rx_mpdu_res_start *amsdu =
  2005. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2006. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  2007. sizeof(struct iwl4965_rx_mpdu_res_start));
  2008. len = le16_to_cpu(amsdu->byte_count);
  2009. rx_start->byte_count = amsdu->byte_count;
  2010. rx_end = (__le32 *) (((u8 *) hdr) + len);
  2011. }
  2012. /* In monitor mode allow 802.11 ACk frames (10 bytes) */
  2013. if (len > priv->hw_params.max_pkt_size ||
  2014. len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
  2015. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  2016. return;
  2017. }
  2018. ampdu_status = le32_to_cpu(*rx_end);
  2019. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  2020. if (!include_phy) {
  2021. /* New status scheme, need to translate */
  2022. ampdu_status_legacy = ampdu_status;
  2023. ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
  2024. }
  2025. /* start from MAC */
  2026. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2027. skb_put(rxb->skb, len); /* end where data ends */
  2028. /* We only process data packets if the interface is open */
  2029. if (unlikely(!priv->is_open)) {
  2030. IWL_DEBUG_DROP_LIMIT
  2031. ("Dropping packet while interface is not open.\n");
  2032. return;
  2033. }
  2034. stats->flag = 0;
  2035. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2036. /* in case of HW accelerated crypto and bad decryption, drop */
  2037. if (!priv->hw_params.sw_crypto &&
  2038. iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  2039. return;
  2040. if (priv->add_radiotap)
  2041. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  2042. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  2043. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2044. priv->alloc_rxb_skb--;
  2045. rxb->skb = NULL;
  2046. }
  2047. /* Calc max signal level (dBm) among 3 possible receivers */
  2048. static int iwl4965_calc_rssi(struct iwl_priv *priv,
  2049. struct iwl4965_rx_phy_res *rx_resp)
  2050. {
  2051. /* data from PHY/DSP regarding signal strength, etc.,
  2052. * contents are always there, not configurable by host. */
  2053. struct iwl4965_rx_non_cfg_phy *ncphy =
  2054. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2055. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  2056. >> IWL_AGC_DB_POS;
  2057. u32 valid_antennae =
  2058. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  2059. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  2060. u8 max_rssi = 0;
  2061. u32 i;
  2062. /* Find max rssi among 3 possible receivers.
  2063. * These values are measured by the digital signal processor (DSP).
  2064. * They should stay fairly constant even as the signal strength varies,
  2065. * if the radio's automatic gain control (AGC) is working right.
  2066. * AGC value (see below) will provide the "interesting" info. */
  2067. for (i = 0; i < 3; i++)
  2068. if (valid_antennae & (1 << i))
  2069. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  2070. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  2071. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  2072. max_rssi, agc);
  2073. /* dBm = max_rssi dB - agc dB - constant.
  2074. * Higher AGC (higher radio gain) means lower signal. */
  2075. return (max_rssi - agc - IWL_RSSI_OFFSET);
  2076. }
  2077. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  2078. {
  2079. unsigned long flags;
  2080. spin_lock_irqsave(&priv->sta_lock, flags);
  2081. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  2082. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  2083. priv->stations[sta_id].sta.sta.modify_mask = 0;
  2084. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2085. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2086. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2087. }
  2088. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  2089. {
  2090. /* FIXME: need locking over ps_status ??? */
  2091. u8 sta_id = iwl_find_station(priv, addr);
  2092. if (sta_id != IWL_INVALID_STATION) {
  2093. u8 sta_awake = priv->stations[sta_id].
  2094. ps_status == STA_PS_STATUS_WAKE;
  2095. if (sta_awake && ps_bit)
  2096. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  2097. else if (!sta_awake && !ps_bit) {
  2098. iwl4965_sta_modify_ps_wake(priv, sta_id);
  2099. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  2100. }
  2101. }
  2102. }
  2103. #ifdef CONFIG_IWLWIFI_DEBUG
  2104. /**
  2105. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  2106. *
  2107. * You may hack this function to show different aspects of received frames,
  2108. * including selective frame dumps.
  2109. * group100 parameter selects whether to show 1 out of 100 good frames.
  2110. *
  2111. * TODO: This was originally written for 3945, need to audit for
  2112. * proper operation with 4965.
  2113. */
  2114. static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2115. struct iwl_rx_packet *pkt,
  2116. struct ieee80211_hdr *header, int group100)
  2117. {
  2118. u32 to_us;
  2119. u32 print_summary = 0;
  2120. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  2121. u32 hundred = 0;
  2122. u32 dataframe = 0;
  2123. u16 fc;
  2124. u16 seq_ctl;
  2125. u16 channel;
  2126. u16 phy_flags;
  2127. int rate_sym;
  2128. u16 length;
  2129. u16 status;
  2130. u16 bcn_tmr;
  2131. u32 tsf_low;
  2132. u64 tsf;
  2133. u8 rssi;
  2134. u8 agc;
  2135. u16 sig_avg;
  2136. u16 noise_diff;
  2137. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  2138. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  2139. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  2140. u8 *data = IWL_RX_DATA(pkt);
  2141. if (likely(!(priv->debug_level & IWL_DL_RX)))
  2142. return;
  2143. /* MAC header */
  2144. fc = le16_to_cpu(header->frame_control);
  2145. seq_ctl = le16_to_cpu(header->seq_ctrl);
  2146. /* metadata */
  2147. channel = le16_to_cpu(rx_hdr->channel);
  2148. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  2149. rate_sym = rx_hdr->rate;
  2150. length = le16_to_cpu(rx_hdr->len);
  2151. /* end-of-frame status and timestamp */
  2152. status = le32_to_cpu(rx_end->status);
  2153. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  2154. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  2155. tsf = le64_to_cpu(rx_end->timestamp);
  2156. /* signal statistics */
  2157. rssi = rx_stats->rssi;
  2158. agc = rx_stats->agc;
  2159. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  2160. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  2161. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  2162. /* if data frame is to us and all is good,
  2163. * (optionally) print summary for only 1 out of every 100 */
  2164. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  2165. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  2166. dataframe = 1;
  2167. if (!group100)
  2168. print_summary = 1; /* print each frame */
  2169. else if (priv->framecnt_to_us < 100) {
  2170. priv->framecnt_to_us++;
  2171. print_summary = 0;
  2172. } else {
  2173. priv->framecnt_to_us = 0;
  2174. print_summary = 1;
  2175. hundred = 1;
  2176. }
  2177. } else {
  2178. /* print summary for all other frames */
  2179. print_summary = 1;
  2180. }
  2181. if (print_summary) {
  2182. char *title;
  2183. int rate_idx;
  2184. u32 bitrate;
  2185. if (hundred)
  2186. title = "100Frames";
  2187. else if (fc & IEEE80211_FCTL_RETRY)
  2188. title = "Retry";
  2189. else if (ieee80211_is_assoc_response(fc))
  2190. title = "AscRsp";
  2191. else if (ieee80211_is_reassoc_response(fc))
  2192. title = "RasRsp";
  2193. else if (ieee80211_is_probe_response(fc)) {
  2194. title = "PrbRsp";
  2195. print_dump = 1; /* dump frame contents */
  2196. } else if (ieee80211_is_beacon(fc)) {
  2197. title = "Beacon";
  2198. print_dump = 1; /* dump frame contents */
  2199. } else if (ieee80211_is_atim(fc))
  2200. title = "ATIM";
  2201. else if (ieee80211_is_auth(fc))
  2202. title = "Auth";
  2203. else if (ieee80211_is_deauth(fc))
  2204. title = "DeAuth";
  2205. else if (ieee80211_is_disassoc(fc))
  2206. title = "DisAssoc";
  2207. else
  2208. title = "Frame";
  2209. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  2210. if (unlikely(rate_idx == -1))
  2211. bitrate = 0;
  2212. else
  2213. bitrate = iwl_rates[rate_idx].ieee / 2;
  2214. /* print frame summary.
  2215. * MAC addresses show just the last byte (for brevity),
  2216. * but you can hack it to show more, if you'd like to. */
  2217. if (dataframe)
  2218. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  2219. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  2220. title, fc, header->addr1[5],
  2221. length, rssi, channel, bitrate);
  2222. else {
  2223. /* src/dst addresses assume managed mode */
  2224. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  2225. "src=0x%02x, rssi=%u, tim=%lu usec, "
  2226. "phy=0x%02x, chnl=%d\n",
  2227. title, fc, header->addr1[5],
  2228. header->addr3[5], rssi,
  2229. tsf_low - priv->scan_start_tsf,
  2230. phy_flags, channel);
  2231. }
  2232. }
  2233. if (print_dump)
  2234. iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
  2235. }
  2236. #else
  2237. static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2238. struct iwl_rx_packet *pkt,
  2239. struct ieee80211_hdr *header,
  2240. int group100)
  2241. {
  2242. }
  2243. #endif
  2244. /* Called for REPLY_RX (legacy ABG frames), or
  2245. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  2246. void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  2247. struct iwl_rx_mem_buffer *rxb)
  2248. {
  2249. struct ieee80211_hdr *header;
  2250. struct ieee80211_rx_status rx_status;
  2251. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2252. /* Use phy data (Rx signal strength, etc.) contained within
  2253. * this rx packet for legacy frames,
  2254. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  2255. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  2256. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2257. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  2258. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2259. __le32 *rx_end;
  2260. unsigned int len = 0;
  2261. u16 fc;
  2262. u8 network_packet;
  2263. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  2264. rx_status.freq =
  2265. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  2266. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  2267. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  2268. rx_status.rate_idx =
  2269. iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  2270. if (rx_status.band == IEEE80211_BAND_5GHZ)
  2271. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  2272. rx_status.antenna = 0;
  2273. rx_status.flag = 0;
  2274. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  2275. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  2276. rx_start->cfg_phy_cnt);
  2277. return;
  2278. }
  2279. if (!include_phy) {
  2280. if (priv->last_phy_res[0])
  2281. rx_start = (struct iwl4965_rx_phy_res *)
  2282. &priv->last_phy_res[1];
  2283. else
  2284. rx_start = NULL;
  2285. }
  2286. if (!rx_start) {
  2287. IWL_ERROR("MPDU frame without a PHY data\n");
  2288. return;
  2289. }
  2290. if (include_phy) {
  2291. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  2292. + rx_start->cfg_phy_cnt);
  2293. len = le16_to_cpu(rx_start->byte_count);
  2294. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  2295. sizeof(struct iwl4965_rx_phy_res) + len);
  2296. } else {
  2297. struct iwl4965_rx_mpdu_res_start *amsdu =
  2298. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2299. header = (void *)(pkt->u.raw +
  2300. sizeof(struct iwl4965_rx_mpdu_res_start));
  2301. len = le16_to_cpu(amsdu->byte_count);
  2302. rx_end = (__le32 *) (pkt->u.raw +
  2303. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  2304. }
  2305. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  2306. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  2307. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  2308. le32_to_cpu(*rx_end));
  2309. return;
  2310. }
  2311. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  2312. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  2313. rx_status.signal = iwl4965_calc_rssi(priv, rx_start);
  2314. /* Meaningful noise values are available only from beacon statistics,
  2315. * which are gathered only when associated, and indicate noise
  2316. * only for the associated network channel ...
  2317. * Ignore these noise values while scanning (other channels) */
  2318. if (iwl_is_associated(priv) &&
  2319. !test_bit(STATUS_SCANNING, &priv->status)) {
  2320. rx_status.noise = priv->last_rx_noise;
  2321. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal,
  2322. rx_status.noise);
  2323. } else {
  2324. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2325. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal, 0);
  2326. }
  2327. /* Reset beacon noise level if not associated. */
  2328. if (!iwl_is_associated(priv))
  2329. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2330. /* Set "1" to report good data frames in groups of 100 */
  2331. /* FIXME: need to optimze the call: */
  2332. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  2333. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  2334. rx_status.signal, rx_status.noise, rx_status.signal,
  2335. (unsigned long long)rx_status.mactime);
  2336. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  2337. iwl4965_handle_data_packet(priv, 1, include_phy,
  2338. rxb, &rx_status);
  2339. return;
  2340. }
  2341. network_packet = iwl4965_is_network_packet(priv, header);
  2342. if (network_packet) {
  2343. priv->last_rx_rssi = rx_status.signal;
  2344. priv->last_beacon_time = priv->ucode_beacon_time;
  2345. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  2346. }
  2347. fc = le16_to_cpu(header->frame_control);
  2348. switch (fc & IEEE80211_FCTL_FTYPE) {
  2349. case IEEE80211_FTYPE_MGMT:
  2350. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2351. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2352. header->addr2);
  2353. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  2354. break;
  2355. case IEEE80211_FTYPE_CTL:
  2356. switch (fc & IEEE80211_FCTL_STYPE) {
  2357. case IEEE80211_STYPE_BACK_REQ:
  2358. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  2359. iwl4965_handle_data_packet(priv, 0, include_phy,
  2360. rxb, &rx_status);
  2361. break;
  2362. default:
  2363. break;
  2364. }
  2365. break;
  2366. case IEEE80211_FTYPE_DATA: {
  2367. DECLARE_MAC_BUF(mac1);
  2368. DECLARE_MAC_BUF(mac2);
  2369. DECLARE_MAC_BUF(mac3);
  2370. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2371. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2372. header->addr2);
  2373. if (unlikely(!network_packet))
  2374. IWL_DEBUG_DROP("Dropping (non network): "
  2375. "%s, %s, %s\n",
  2376. print_mac(mac1, header->addr1),
  2377. print_mac(mac2, header->addr2),
  2378. print_mac(mac3, header->addr3));
  2379. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  2380. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  2381. print_mac(mac1, header->addr1),
  2382. print_mac(mac2, header->addr2),
  2383. print_mac(mac3, header->addr3));
  2384. else
  2385. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  2386. &rx_status);
  2387. break;
  2388. }
  2389. default:
  2390. break;
  2391. }
  2392. }
  2393. /**
  2394. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  2395. *
  2396. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  2397. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  2398. */
  2399. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  2400. struct iwl_ht_agg *agg,
  2401. struct iwl4965_compressed_ba_resp*
  2402. ba_resp)
  2403. {
  2404. int i, sh, ack;
  2405. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  2406. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2407. u64 bitmap;
  2408. int successes = 0;
  2409. struct ieee80211_tx_info *info;
  2410. if (unlikely(!agg->wait_for_ba)) {
  2411. IWL_ERROR("Received BA when not expected\n");
  2412. return -EINVAL;
  2413. }
  2414. /* Mark that the expected block-ack response arrived */
  2415. agg->wait_for_ba = 0;
  2416. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  2417. /* Calculate shift to align block-ack bits with our Tx window bits */
  2418. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  2419. if (sh < 0) /* tbw something is wrong with indices */
  2420. sh += 0x100;
  2421. /* don't use 64-bit values for now */
  2422. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  2423. if (agg->frame_count > (64 - sh)) {
  2424. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  2425. return -1;
  2426. }
  2427. /* check for success or failure according to the
  2428. * transmitted bitmap and block-ack bitmap */
  2429. bitmap &= agg->bitmap;
  2430. /* For each frame attempted in aggregation,
  2431. * update driver's record of tx frame's status. */
  2432. for (i = 0; i < agg->frame_count ; i++) {
  2433. ack = bitmap & (1 << i);
  2434. successes += !!ack;
  2435. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  2436. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  2437. agg->start_idx + i);
  2438. }
  2439. info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
  2440. memset(&info->status, 0, sizeof(info->status));
  2441. info->flags = IEEE80211_TX_STAT_ACK;
  2442. info->flags |= IEEE80211_TX_STAT_AMPDU;
  2443. info->status.ampdu_ack_map = successes;
  2444. info->status.ampdu_ack_len = agg->frame_count;
  2445. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
  2446. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
  2447. return 0;
  2448. }
  2449. /**
  2450. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  2451. */
  2452. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  2453. u16 txq_id)
  2454. {
  2455. /* Simply stop the queue, but don't change any configuration;
  2456. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  2457. iwl_write_prph(priv,
  2458. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  2459. (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  2460. (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  2461. }
  2462. /**
  2463. * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
  2464. * priv->lock must be held by the caller
  2465. */
  2466. static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
  2467. u16 ssn_idx, u8 tx_fifo)
  2468. {
  2469. int ret = 0;
  2470. if (IWL49_FIRST_AMPDU_QUEUE > txq_id) {
  2471. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2472. txq_id, IWL49_FIRST_AMPDU_QUEUE);
  2473. return -EINVAL;
  2474. }
  2475. ret = iwl_grab_nic_access(priv);
  2476. if (ret)
  2477. return ret;
  2478. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2479. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2480. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2481. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2482. /* supposes that ssn_idx is valid (!= 0xFFF) */
  2483. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2484. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2485. iwl_txq_ctx_deactivate(priv, txq_id);
  2486. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  2487. iwl_release_nic_access(priv);
  2488. return 0;
  2489. }
  2490. /**
  2491. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  2492. *
  2493. * Handles block-acknowledge notification from device, which reports success
  2494. * of frames sent via aggregation.
  2495. */
  2496. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  2497. struct iwl_rx_mem_buffer *rxb)
  2498. {
  2499. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2500. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  2501. int index;
  2502. struct iwl_tx_queue *txq = NULL;
  2503. struct iwl_ht_agg *agg;
  2504. DECLARE_MAC_BUF(mac);
  2505. /* "flow" corresponds to Tx queue */
  2506. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2507. /* "ssn" is start of block-ack Tx window, corresponds to index
  2508. * (in Tx queue's circular buffer) of first TFD/frame in window */
  2509. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  2510. if (scd_flow >= priv->hw_params.max_txq_num) {
  2511. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  2512. return;
  2513. }
  2514. txq = &priv->txq[scd_flow];
  2515. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  2516. /* Find index just before block-ack window */
  2517. index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  2518. /* TODO: Need to get this copy more safely - now good for debug */
  2519. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  2520. "sta_id = %d\n",
  2521. agg->wait_for_ba,
  2522. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  2523. ba_resp->sta_id);
  2524. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  2525. "%d, scd_ssn = %d\n",
  2526. ba_resp->tid,
  2527. ba_resp->seq_ctl,
  2528. (unsigned long long)le64_to_cpu(ba_resp->bitmap),
  2529. ba_resp->scd_flow,
  2530. ba_resp->scd_ssn);
  2531. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  2532. agg->start_idx,
  2533. (unsigned long long)agg->bitmap);
  2534. /* Update driver's record of ACK vs. not for each frame in window */
  2535. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  2536. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  2537. * block-ack window (we assume that they've been successfully
  2538. * transmitted ... if not, it's too late anyway). */
  2539. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  2540. /* calculate mac80211 ampdu sw queue to wake */
  2541. int ampdu_q =
  2542. scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
  2543. int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
  2544. priv->stations[ba_resp->sta_id].
  2545. tid[ba_resp->tid].tfds_in_queue -= freed;
  2546. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2547. priv->mac80211_registered &&
  2548. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  2549. ieee80211_wake_queue(priv->hw, ampdu_q);
  2550. iwl_txq_check_empty(priv, ba_resp->sta_id,
  2551. ba_resp->tid, scd_flow);
  2552. }
  2553. }
  2554. /**
  2555. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  2556. */
  2557. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  2558. u16 txq_id)
  2559. {
  2560. u32 tbl_dw_addr;
  2561. u32 tbl_dw;
  2562. u16 scd_q2ratid;
  2563. scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  2564. tbl_dw_addr = priv->scd_base_addr +
  2565. IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  2566. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  2567. if (txq_id & 0x1)
  2568. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  2569. else
  2570. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  2571. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  2572. return 0;
  2573. }
  2574. /**
  2575. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  2576. *
  2577. * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
  2578. * i.e. it must be one of the higher queues used for aggregation
  2579. */
  2580. static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
  2581. int tx_fifo, int sta_id, int tid, u16 ssn_idx)
  2582. {
  2583. unsigned long flags;
  2584. int ret;
  2585. u16 ra_tid;
  2586. if (IWL49_FIRST_AMPDU_QUEUE > txq_id)
  2587. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2588. txq_id, IWL49_FIRST_AMPDU_QUEUE);
  2589. ra_tid = BUILD_RAxTID(sta_id, tid);
  2590. /* Modify device's station table to Tx this TID */
  2591. iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
  2592. spin_lock_irqsave(&priv->lock, flags);
  2593. ret = iwl_grab_nic_access(priv);
  2594. if (ret) {
  2595. spin_unlock_irqrestore(&priv->lock, flags);
  2596. return ret;
  2597. }
  2598. /* Stop this Tx queue before configuring it */
  2599. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2600. /* Map receiver-address / traffic-ID to this queue */
  2601. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  2602. /* Set this queue as a chain-building queue */
  2603. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2604. /* Place first TFD at index corresponding to start sequence number.
  2605. * Assumes that ssn_idx is valid (!= 0xFFF) */
  2606. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2607. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2608. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2609. /* Set up Tx window size and frame limit for this queue */
  2610. iwl_write_targ_mem(priv,
  2611. priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  2612. (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  2613. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  2614. iwl_write_targ_mem(priv, priv->scd_base_addr +
  2615. IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  2616. (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  2617. & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  2618. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2619. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  2620. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  2621. iwl_release_nic_access(priv);
  2622. spin_unlock_irqrestore(&priv->lock, flags);
  2623. return 0;
  2624. }
  2625. static int iwl4965_rx_agg_start(struct iwl_priv *priv,
  2626. const u8 *addr, int tid, u16 ssn)
  2627. {
  2628. unsigned long flags;
  2629. int sta_id;
  2630. sta_id = iwl_find_station(priv, addr);
  2631. if (sta_id == IWL_INVALID_STATION)
  2632. return -ENXIO;
  2633. spin_lock_irqsave(&priv->sta_lock, flags);
  2634. priv->stations[sta_id].sta.station_flags_msk = 0;
  2635. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  2636. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  2637. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  2638. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2639. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2640. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2641. CMD_ASYNC);
  2642. }
  2643. static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
  2644. const u8 *addr, int tid)
  2645. {
  2646. unsigned long flags;
  2647. int sta_id;
  2648. sta_id = iwl_find_station(priv, addr);
  2649. if (sta_id == IWL_INVALID_STATION)
  2650. return -ENXIO;
  2651. spin_lock_irqsave(&priv->sta_lock, flags);
  2652. priv->stations[sta_id].sta.station_flags_msk = 0;
  2653. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  2654. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  2655. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2656. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2657. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2658. CMD_ASYNC);
  2659. }
  2660. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  2661. enum ieee80211_ampdu_mlme_action action,
  2662. const u8 *addr, u16 tid, u16 *ssn)
  2663. {
  2664. struct iwl_priv *priv = hw->priv;
  2665. DECLARE_MAC_BUF(mac);
  2666. IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
  2667. print_mac(mac, addr), tid);
  2668. switch (action) {
  2669. case IEEE80211_AMPDU_RX_START:
  2670. IWL_DEBUG_HT("start Rx\n");
  2671. return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
  2672. case IEEE80211_AMPDU_RX_STOP:
  2673. IWL_DEBUG_HT("stop Rx\n");
  2674. return iwl4965_rx_agg_stop(priv, addr, tid);
  2675. case IEEE80211_AMPDU_TX_START:
  2676. IWL_DEBUG_HT("start Tx\n");
  2677. return iwl_tx_agg_start(priv, addr, tid, ssn);
  2678. case IEEE80211_AMPDU_TX_STOP:
  2679. IWL_DEBUG_HT("stop Tx\n");
  2680. return iwl_tx_agg_stop(priv, addr, tid);
  2681. default:
  2682. IWL_DEBUG_HT("unknown\n");
  2683. return -EINVAL;
  2684. break;
  2685. }
  2686. return 0;
  2687. }
  2688. static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
  2689. {
  2690. switch (cmd_id) {
  2691. case REPLY_RXON:
  2692. return (u16) sizeof(struct iwl4965_rxon_cmd);
  2693. default:
  2694. return len;
  2695. }
  2696. }
  2697. static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
  2698. {
  2699. struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
  2700. addsta->mode = cmd->mode;
  2701. memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
  2702. memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
  2703. addsta->station_flags = cmd->station_flags;
  2704. addsta->station_flags_msk = cmd->station_flags_msk;
  2705. addsta->tid_disable_tx = cmd->tid_disable_tx;
  2706. addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
  2707. addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
  2708. addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
  2709. addsta->reserved1 = __constant_cpu_to_le16(0);
  2710. addsta->reserved2 = __constant_cpu_to_le32(0);
  2711. return (u16)sizeof(struct iwl4965_addsta_cmd);
  2712. }
  2713. static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
  2714. {
  2715. return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
  2716. }
  2717. /**
  2718. * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
  2719. */
  2720. static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
  2721. struct iwl_ht_agg *agg,
  2722. struct iwl4965_tx_resp *tx_resp,
  2723. int txq_id, u16 start_idx)
  2724. {
  2725. u16 status;
  2726. struct agg_tx_status *frame_status = tx_resp->u.agg_status;
  2727. struct ieee80211_tx_info *info = NULL;
  2728. struct ieee80211_hdr *hdr = NULL;
  2729. int i, sh, idx;
  2730. u16 seq;
  2731. if (agg->wait_for_ba)
  2732. IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
  2733. agg->frame_count = tx_resp->frame_count;
  2734. agg->start_idx = start_idx;
  2735. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  2736. agg->bitmap = 0;
  2737. /* # frames attempted by Tx command */
  2738. if (agg->frame_count == 1) {
  2739. /* Only one frame was attempted; no block-ack will arrive */
  2740. status = le16_to_cpu(frame_status[0].status);
  2741. idx = start_idx;
  2742. /* FIXME: code repetition */
  2743. IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
  2744. agg->frame_count, agg->start_idx, idx);
  2745. info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
  2746. info->status.retry_count = tx_resp->failure_frame;
  2747. info->flags &= ~IEEE80211_TX_CTL_AMPDU;
  2748. info->flags |= iwl_is_tx_success(status)?
  2749. IEEE80211_TX_STAT_ACK : 0;
  2750. iwl4965_hwrate_to_tx_control(priv,
  2751. le32_to_cpu(tx_resp->rate_n_flags),
  2752. info);
  2753. /* FIXME: code repetition end */
  2754. IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
  2755. status & 0xff, tx_resp->failure_frame);
  2756. IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
  2757. iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
  2758. agg->wait_for_ba = 0;
  2759. } else {
  2760. /* Two or more frames were attempted; expect block-ack */
  2761. u64 bitmap = 0;
  2762. int start = agg->start_idx;
  2763. /* Construct bit-map of pending frames within Tx window */
  2764. for (i = 0; i < agg->frame_count; i++) {
  2765. u16 sc;
  2766. status = le16_to_cpu(frame_status[i].status);
  2767. seq = le16_to_cpu(frame_status[i].sequence);
  2768. idx = SEQ_TO_INDEX(seq);
  2769. txq_id = SEQ_TO_QUEUE(seq);
  2770. if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
  2771. AGG_TX_STATE_ABORT_MSK))
  2772. continue;
  2773. IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
  2774. agg->frame_count, txq_id, idx);
  2775. hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
  2776. sc = le16_to_cpu(hdr->seq_ctrl);
  2777. if (idx != (SEQ_TO_SN(sc) & 0xff)) {
  2778. IWL_ERROR("BUG_ON idx doesn't match seq control"
  2779. " idx=%d, seq_idx=%d, seq=%d\n",
  2780. idx, SEQ_TO_SN(sc),
  2781. hdr->seq_ctrl);
  2782. return -1;
  2783. }
  2784. IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
  2785. i, idx, SEQ_TO_SN(sc));
  2786. sh = idx - start;
  2787. if (sh > 64) {
  2788. sh = (start - idx) + 0xff;
  2789. bitmap = bitmap << sh;
  2790. sh = 0;
  2791. start = idx;
  2792. } else if (sh < -64)
  2793. sh = 0xff - (start - idx);
  2794. else if (sh < 0) {
  2795. sh = start - idx;
  2796. start = idx;
  2797. bitmap = bitmap << sh;
  2798. sh = 0;
  2799. }
  2800. bitmap |= (1 << sh);
  2801. IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
  2802. start, (u32)(bitmap & 0xFFFFFFFF));
  2803. }
  2804. agg->bitmap = bitmap;
  2805. agg->start_idx = start;
  2806. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  2807. IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
  2808. agg->frame_count, agg->start_idx,
  2809. (unsigned long long)agg->bitmap);
  2810. if (bitmap)
  2811. agg->wait_for_ba = 1;
  2812. }
  2813. return 0;
  2814. }
  2815. /**
  2816. * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
  2817. */
  2818. static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
  2819. struct iwl_rx_mem_buffer *rxb)
  2820. {
  2821. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2822. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2823. int txq_id = SEQ_TO_QUEUE(sequence);
  2824. int index = SEQ_TO_INDEX(sequence);
  2825. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  2826. struct ieee80211_tx_info *info;
  2827. struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2828. u32 status = le32_to_cpu(tx_resp->u.status);
  2829. int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
  2830. u16 fc;
  2831. struct ieee80211_hdr *hdr;
  2832. u8 *qc = NULL;
  2833. if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
  2834. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2835. "is out of range [0-%d] %d %d\n", txq_id,
  2836. index, txq->q.n_bd, txq->q.write_ptr,
  2837. txq->q.read_ptr);
  2838. return;
  2839. }
  2840. info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
  2841. memset(&info->status, 0, sizeof(info->status));
  2842. hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
  2843. fc = le16_to_cpu(hdr->frame_control);
  2844. if (ieee80211_is_qos_data(fc)) {
  2845. qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
  2846. tid = qc[0] & 0xf;
  2847. }
  2848. sta_id = iwl_get_ra_sta_id(priv, hdr);
  2849. if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
  2850. IWL_ERROR("Station not known\n");
  2851. return;
  2852. }
  2853. if (txq->sched_retry) {
  2854. const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
  2855. struct iwl_ht_agg *agg = NULL;
  2856. if (!qc)
  2857. return;
  2858. agg = &priv->stations[sta_id].tid[tid].agg;
  2859. iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
  2860. if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
  2861. /* TODO: send BAR */
  2862. }
  2863. if (txq->q.read_ptr != (scd_ssn & 0xff)) {
  2864. int freed, ampdu_q;
  2865. index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
  2866. IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
  2867. "%d index %d\n", scd_ssn , index);
  2868. freed = iwl_tx_queue_reclaim(priv, txq_id, index);
  2869. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  2870. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2871. txq_id >= 0 && priv->mac80211_registered &&
  2872. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
  2873. /* calculate mac80211 ampdu sw queue to wake */
  2874. ampdu_q = txq_id - IWL49_FIRST_AMPDU_QUEUE +
  2875. priv->hw->queues;
  2876. if (agg->state == IWL_AGG_OFF)
  2877. ieee80211_wake_queue(priv->hw, txq_id);
  2878. else
  2879. ieee80211_wake_queue(priv->hw, ampdu_q);
  2880. }
  2881. iwl_txq_check_empty(priv, sta_id, tid, txq_id);
  2882. }
  2883. } else {
  2884. info->status.retry_count = tx_resp->failure_frame;
  2885. info->flags |=
  2886. iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
  2887. iwl4965_hwrate_to_tx_control(priv,
  2888. le32_to_cpu(tx_resp->rate_n_flags),
  2889. info);
  2890. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
  2891. "0x%x retries %d\n", txq_id,
  2892. iwl_get_tx_fail_reason(status),
  2893. status, le32_to_cpu(tx_resp->rate_n_flags),
  2894. tx_resp->failure_frame);
  2895. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2896. if (index != -1) {
  2897. int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
  2898. if (tid != MAX_TID_COUNT)
  2899. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  2900. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2901. (txq_id >= 0) && priv->mac80211_registered)
  2902. ieee80211_wake_queue(priv->hw, txq_id);
  2903. if (tid != MAX_TID_COUNT)
  2904. iwl_txq_check_empty(priv, sta_id, tid, txq_id);
  2905. }
  2906. }
  2907. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2908. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2909. }
  2910. /* Set up 4965-specific Rx frame reply handlers */
  2911. static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
  2912. {
  2913. /* Legacy Rx frames */
  2914. priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
  2915. /* Tx response */
  2916. priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
  2917. /* block ack */
  2918. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  2919. }
  2920. static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
  2921. {
  2922. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  2923. }
  2924. static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
  2925. {
  2926. cancel_work_sync(&priv->txpower_work);
  2927. }
  2928. static struct iwl_hcmd_ops iwl4965_hcmd = {
  2929. .rxon_assoc = iwl4965_send_rxon_assoc,
  2930. };
  2931. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  2932. .get_hcmd_size = iwl4965_get_hcmd_size,
  2933. .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
  2934. .chain_noise_reset = iwl4965_chain_noise_reset,
  2935. .gain_computation = iwl4965_gain_computation,
  2936. };
  2937. static struct iwl_lib_ops iwl4965_lib = {
  2938. .set_hw_params = iwl4965_hw_set_hw_params,
  2939. .alloc_shared_mem = iwl4965_alloc_shared_mem,
  2940. .free_shared_mem = iwl4965_free_shared_mem,
  2941. .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
  2942. .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
  2943. .txq_set_sched = iwl4965_txq_set_sched,
  2944. .txq_agg_enable = iwl4965_txq_agg_enable,
  2945. .txq_agg_disable = iwl4965_txq_agg_disable,
  2946. .rx_handler_setup = iwl4965_rx_handler_setup,
  2947. .setup_deferred_work = iwl4965_setup_deferred_work,
  2948. .cancel_deferred_work = iwl4965_cancel_deferred_work,
  2949. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  2950. .alive_notify = iwl4965_alive_notify,
  2951. .init_alive_start = iwl4965_init_alive_start,
  2952. .load_ucode = iwl4965_load_bsm,
  2953. .apm_ops = {
  2954. .init = iwl4965_apm_init,
  2955. .reset = iwl4965_apm_reset,
  2956. .stop = iwl4965_apm_stop,
  2957. .config = iwl4965_nic_config,
  2958. .set_pwr_src = iwl4965_set_pwr_src,
  2959. },
  2960. .eeprom_ops = {
  2961. .regulatory_bands = {
  2962. EEPROM_REGULATORY_BAND_1_CHANNELS,
  2963. EEPROM_REGULATORY_BAND_2_CHANNELS,
  2964. EEPROM_REGULATORY_BAND_3_CHANNELS,
  2965. EEPROM_REGULATORY_BAND_4_CHANNELS,
  2966. EEPROM_REGULATORY_BAND_5_CHANNELS,
  2967. EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
  2968. EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
  2969. },
  2970. .verify_signature = iwlcore_eeprom_verify_signature,
  2971. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  2972. .release_semaphore = iwlcore_eeprom_release_semaphore,
  2973. .check_version = iwl4965_eeprom_check_version,
  2974. .query_addr = iwlcore_eeprom_query_addr,
  2975. },
  2976. .radio_kill_sw = iwl4965_radio_kill_sw,
  2977. .set_power = iwl4965_set_power,
  2978. .update_chain_flags = iwl4965_update_chain_flags,
  2979. };
  2980. static struct iwl_ops iwl4965_ops = {
  2981. .lib = &iwl4965_lib,
  2982. .hcmd = &iwl4965_hcmd,
  2983. .utils = &iwl4965_hcmd_utils,
  2984. };
  2985. struct iwl_cfg iwl4965_agn_cfg = {
  2986. .name = "4965AGN",
  2987. .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
  2988. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  2989. .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
  2990. .ops = &iwl4965_ops,
  2991. .mod_params = &iwl4965_mod_params,
  2992. };
  2993. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  2994. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  2995. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  2996. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  2997. module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
  2998. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
  2999. module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
  3000. MODULE_PARM_DESC(debug, "debug output mask");
  3001. module_param_named(
  3002. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  3003. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3004. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  3005. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3006. /* QoS */
  3007. module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
  3008. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  3009. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  3010. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3011. module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
  3012. MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");