bf5xx-ad73311.c 6.3 KB

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  1. /*
  2. * File: sound/soc/blackfin/bf5xx-ad73311.c
  3. * Author: Cliff Cai <Cliff.Cai@analog.com>
  4. *
  5. * Created: Thur Sep 25 2008
  6. * Description: Board driver for ad73311 sound chip
  7. *
  8. * Modified:
  9. * Copyright 2008 Analog Devices Inc.
  10. *
  11. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, see the file COPYING, or write
  25. * to the Free Software Foundation, Inc.,
  26. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  27. */
  28. #include <linux/module.h>
  29. #include <linux/moduleparam.h>
  30. #include <linux/device.h>
  31. #include <linux/delay.h>
  32. #include <linux/gpio.h>
  33. #include <sound/core.h>
  34. #include <sound/pcm.h>
  35. #include <sound/soc.h>
  36. #include <sound/soc-dapm.h>
  37. #include <sound/pcm_params.h>
  38. #include <asm/blackfin.h>
  39. #include <asm/cacheflush.h>
  40. #include <asm/irq.h>
  41. #include <asm/dma.h>
  42. #include <asm/portmux.h>
  43. #include "../codecs/ad73311.h"
  44. #include "bf5xx-sport.h"
  45. #include "bf5xx-i2s-pcm.h"
  46. #include "bf5xx-i2s.h"
  47. #if CONFIG_SND_BF5XX_SPORT_NUM == 0
  48. #define bfin_write_SPORT_TCR1 bfin_write_SPORT0_TCR1
  49. #define bfin_read_SPORT_TCR1 bfin_read_SPORT0_TCR1
  50. #define bfin_write_SPORT_TCR2 bfin_write_SPORT0_TCR2
  51. #define bfin_write_SPORT_TX16 bfin_write_SPORT0_TX16
  52. #define bfin_read_SPORT_STAT bfin_read_SPORT0_STAT
  53. #else
  54. #define bfin_write_SPORT_TCR1 bfin_write_SPORT1_TCR1
  55. #define bfin_read_SPORT_TCR1 bfin_read_SPORT1_TCR1
  56. #define bfin_write_SPORT_TCR2 bfin_write_SPORT1_TCR2
  57. #define bfin_write_SPORT_TX16 bfin_write_SPORT1_TX16
  58. #define bfin_read_SPORT_STAT bfin_read_SPORT1_STAT
  59. #endif
  60. #define GPIO_SE CONFIG_SND_BFIN_AD73311_SE
  61. static struct snd_soc_card bf5xx_ad73311;
  62. static int snd_ad73311_startup(void)
  63. {
  64. pr_debug("%s enter\n", __func__);
  65. /* Pull up SE pin on AD73311L */
  66. gpio_set_value(GPIO_SE, 1);
  67. return 0;
  68. }
  69. static int snd_ad73311_configure(void)
  70. {
  71. unsigned short ctrl_regs[6];
  72. unsigned short status = 0;
  73. int count = 0;
  74. /* DMCLK = MCLK = 16.384 MHz
  75. * SCLK = DMCLK/8 = 2.048 MHz
  76. * Sample Rate = DMCLK/2048 = 8 KHz
  77. */
  78. ctrl_regs[0] = AD_CONTROL | AD_WRITE | CTRL_REG_B | REGB_MCDIV(0) | \
  79. REGB_SCDIV(0) | REGB_DIRATE(0);
  80. ctrl_regs[1] = AD_CONTROL | AD_WRITE | CTRL_REG_C | REGC_PUDEV | \
  81. REGC_PUADC | REGC_PUDAC | REGC_PUREF | REGC_REFUSE ;
  82. ctrl_regs[2] = AD_CONTROL | AD_WRITE | CTRL_REG_D | REGD_OGS(2) | \
  83. REGD_IGS(2);
  84. ctrl_regs[3] = AD_CONTROL | AD_WRITE | CTRL_REG_E | REGE_DA(0x1f);
  85. ctrl_regs[4] = AD_CONTROL | AD_WRITE | CTRL_REG_F | REGF_SEEN ;
  86. ctrl_regs[5] = AD_CONTROL | AD_WRITE | CTRL_REG_A | REGA_MODE_DATA;
  87. local_irq_disable();
  88. snd_ad73311_startup();
  89. udelay(1);
  90. bfin_write_SPORT_TCR1(TFSR);
  91. bfin_write_SPORT_TCR2(0xF);
  92. SSYNC();
  93. /* SPORT Tx Register is a 8 x 16 FIFO, all the data can be put to
  94. * FIFO before enable SPORT to transfer the data
  95. */
  96. for (count = 0; count < 6; count++)
  97. bfin_write_SPORT_TX16(ctrl_regs[count]);
  98. SSYNC();
  99. bfin_write_SPORT_TCR1(bfin_read_SPORT_TCR1() | TSPEN);
  100. SSYNC();
  101. /* When TUVF is set, the data is already send out */
  102. while (!(status & TUVF) && ++count < 10000) {
  103. udelay(1);
  104. status = bfin_read_SPORT_STAT();
  105. SSYNC();
  106. }
  107. bfin_write_SPORT_TCR1(bfin_read_SPORT_TCR1() & ~TSPEN);
  108. SSYNC();
  109. local_irq_enable();
  110. if (count >= 10000) {
  111. printk(KERN_ERR "ad73311: failed to configure codec\n");
  112. return -1;
  113. }
  114. return 0;
  115. }
  116. static int bf5xx_probe(struct platform_device *pdev)
  117. {
  118. int err;
  119. if (gpio_request(GPIO_SE, "AD73311_SE")) {
  120. printk(KERN_ERR "%s: Failed ro request GPIO_%d\n", __func__, GPIO_SE);
  121. return -EBUSY;
  122. }
  123. gpio_direction_output(GPIO_SE, 0);
  124. err = snd_ad73311_configure();
  125. if (err < 0)
  126. return -EFAULT;
  127. return 0;
  128. }
  129. static int bf5xx_ad73311_startup(struct snd_pcm_substream *substream)
  130. {
  131. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  132. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  133. pr_debug("%s enter\n", __func__);
  134. cpu_dai->private_data = sport_handle;
  135. return 0;
  136. }
  137. static int bf5xx_ad73311_hw_params(struct snd_pcm_substream *substream,
  138. struct snd_pcm_hw_params *params)
  139. {
  140. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  141. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  142. int ret = 0;
  143. pr_debug("%s rate %d format %x\n", __func__, params_rate(params),
  144. params_format(params));
  145. /* set cpu DAI configuration */
  146. ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A |
  147. SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
  148. if (ret < 0)
  149. return ret;
  150. return 0;
  151. }
  152. static struct snd_soc_ops bf5xx_ad73311_ops = {
  153. .startup = bf5xx_ad73311_startup,
  154. .hw_params = bf5xx_ad73311_hw_params,
  155. };
  156. static struct snd_soc_dai_link bf5xx_ad73311_dai = {
  157. .name = "ad73311",
  158. .stream_name = "AD73311",
  159. .cpu_dai = &bf5xx_i2s_dai,
  160. .codec_dai = &ad73311_dai,
  161. .ops = &bf5xx_ad73311_ops,
  162. };
  163. static struct snd_soc_card bf5xx_ad73311 = {
  164. .name = "bf5xx_ad73311",
  165. .platform = &bf5xx_i2s_soc_platform,
  166. .probe = bf5xx_probe,
  167. .dai_link = &bf5xx_ad73311_dai,
  168. .num_links = 1,
  169. };
  170. static struct snd_soc_device bf5xx_ad73311_snd_devdata = {
  171. .card = &bf5xx_ad73311,
  172. .codec_dev = &soc_codec_dev_ad73311,
  173. };
  174. static struct platform_device *bf5xx_ad73311_snd_device;
  175. static int __init bf5xx_ad73311_init(void)
  176. {
  177. int ret;
  178. pr_debug("%s enter\n", __func__);
  179. bf5xx_ad73311_snd_device = platform_device_alloc("soc-audio", -1);
  180. if (!bf5xx_ad73311_snd_device)
  181. return -ENOMEM;
  182. platform_set_drvdata(bf5xx_ad73311_snd_device, &bf5xx_ad73311_snd_devdata);
  183. bf5xx_ad73311_snd_devdata.dev = &bf5xx_ad73311_snd_device->dev;
  184. ret = platform_device_add(bf5xx_ad73311_snd_device);
  185. if (ret)
  186. platform_device_put(bf5xx_ad73311_snd_device);
  187. return ret;
  188. }
  189. static void __exit bf5xx_ad73311_exit(void)
  190. {
  191. pr_debug("%s enter\n", __func__);
  192. platform_device_unregister(bf5xx_ad73311_snd_device);
  193. }
  194. module_init(bf5xx_ad73311_init);
  195. module_exit(bf5xx_ad73311_exit);
  196. /* Module information */
  197. MODULE_AUTHOR("Cliff Cai");
  198. MODULE_DESCRIPTION("ALSA SoC AD73311 Blackfin");
  199. MODULE_LICENSE("GPL");