aaci.c 26 KB

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  1. /*
  2. * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Documentation: ARM DDI 0173B
  11. */
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/ioport.h>
  16. #include <linux/device.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/err.h>
  20. #include <linux/amba/bus.h>
  21. #include <linux/io.h>
  22. #include <sound/core.h>
  23. #include <sound/initval.h>
  24. #include <sound/ac97_codec.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include "aaci.h"
  28. #define DRIVER_NAME "aaci-pl041"
  29. /*
  30. * PM support is not complete. Turn it off.
  31. */
  32. #undef CONFIG_PM
  33. static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
  34. {
  35. u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
  36. /*
  37. * Ensure that the slot 1/2 RX registers are empty.
  38. */
  39. v = readl(aaci->base + AACI_SLFR);
  40. if (v & SLFR_2RXV)
  41. readl(aaci->base + AACI_SL2RX);
  42. if (v & SLFR_1RXV)
  43. readl(aaci->base + AACI_SL1RX);
  44. writel(maincr, aaci->base + AACI_MAINCR);
  45. }
  46. /*
  47. * P29:
  48. * The recommended use of programming the external codec through slot 1
  49. * and slot 2 data is to use the channels during setup routines and the
  50. * slot register at any other time. The data written into slot 1, slot 2
  51. * and slot 12 registers is transmitted only when their corresponding
  52. * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
  53. * register.
  54. */
  55. static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  56. unsigned short val)
  57. {
  58. struct aaci *aaci = ac97->private_data;
  59. u32 v;
  60. int timeout = 5000;
  61. if (ac97->num >= 4)
  62. return;
  63. mutex_lock(&aaci->ac97_sem);
  64. aaci_ac97_select_codec(aaci, ac97);
  65. /*
  66. * P54: You must ensure that AACI_SL2TX is always written
  67. * to, if required, before data is written to AACI_SL1TX.
  68. */
  69. writel(val << 4, aaci->base + AACI_SL2TX);
  70. writel(reg << 12, aaci->base + AACI_SL1TX);
  71. /*
  72. * Wait for the transmission of both slots to complete.
  73. */
  74. do {
  75. v = readl(aaci->base + AACI_SLFR);
  76. } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
  77. if (!timeout)
  78. dev_err(&aaci->dev->dev,
  79. "timeout waiting for write to complete\n");
  80. mutex_unlock(&aaci->ac97_sem);
  81. }
  82. /*
  83. * Read an AC'97 register.
  84. */
  85. static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  86. {
  87. struct aaci *aaci = ac97->private_data;
  88. u32 v;
  89. int timeout = 5000;
  90. int retries = 10;
  91. if (ac97->num >= 4)
  92. return ~0;
  93. mutex_lock(&aaci->ac97_sem);
  94. aaci_ac97_select_codec(aaci, ac97);
  95. /*
  96. * Write the register address to slot 1.
  97. */
  98. writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
  99. /*
  100. * Wait for the transmission to complete.
  101. */
  102. do {
  103. v = readl(aaci->base + AACI_SLFR);
  104. } while ((v & SLFR_1TXB) && --timeout);
  105. if (!timeout) {
  106. dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
  107. v = ~0;
  108. goto out;
  109. }
  110. /*
  111. * Give the AC'97 codec more than enough time
  112. * to respond. (42us = ~2 frames at 48kHz.)
  113. */
  114. udelay(42);
  115. /*
  116. * Wait for slot 2 to indicate data.
  117. */
  118. timeout = 5000;
  119. do {
  120. cond_resched();
  121. v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
  122. } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
  123. if (!timeout) {
  124. dev_err(&aaci->dev->dev, "timeout on RX valid\n");
  125. v = ~0;
  126. goto out;
  127. }
  128. do {
  129. v = readl(aaci->base + AACI_SL1RX) >> 12;
  130. if (v == reg) {
  131. v = readl(aaci->base + AACI_SL2RX) >> 4;
  132. break;
  133. } else if (--retries) {
  134. dev_warn(&aaci->dev->dev,
  135. "ac97 read back fail. retry\n");
  136. continue;
  137. } else {
  138. dev_warn(&aaci->dev->dev,
  139. "wrong ac97 register read back (%x != %x)\n",
  140. v, reg);
  141. v = ~0;
  142. }
  143. } while (retries);
  144. out:
  145. mutex_unlock(&aaci->ac97_sem);
  146. return v;
  147. }
  148. static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
  149. {
  150. u32 val;
  151. int timeout = 5000;
  152. do {
  153. val = readl(aacirun->base + AACI_SR);
  154. } while (val & (SR_TXB|SR_RXB) && timeout--);
  155. }
  156. /*
  157. * Interrupt support.
  158. */
  159. static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
  160. {
  161. if (mask & ISR_ORINTR) {
  162. dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
  163. writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
  164. }
  165. if (mask & ISR_RXTOINTR) {
  166. dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
  167. writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
  168. }
  169. if (mask & ISR_RXINTR) {
  170. struct aaci_runtime *aacirun = &aaci->capture;
  171. void *ptr;
  172. if (!aacirun->substream || !aacirun->start) {
  173. dev_warn(&aaci->dev->dev, "RX interrupt???\n");
  174. writel(0, aacirun->base + AACI_IE);
  175. return;
  176. }
  177. ptr = aacirun->ptr;
  178. do {
  179. unsigned int len = aacirun->fifosz;
  180. u32 val;
  181. if (aacirun->bytes <= 0) {
  182. aacirun->bytes += aacirun->period;
  183. aacirun->ptr = ptr;
  184. spin_unlock(&aaci->lock);
  185. snd_pcm_period_elapsed(aacirun->substream);
  186. spin_lock(&aaci->lock);
  187. }
  188. if (!(aacirun->cr & CR_EN))
  189. break;
  190. val = readl(aacirun->base + AACI_SR);
  191. if (!(val & SR_RXHF))
  192. break;
  193. if (!(val & SR_RXFF))
  194. len >>= 1;
  195. aacirun->bytes -= len;
  196. /* reading 16 bytes at a time */
  197. for( ; len > 0; len -= 16) {
  198. asm(
  199. "ldmia %1, {r0, r1, r2, r3}\n\t"
  200. "stmia %0!, {r0, r1, r2, r3}"
  201. : "+r" (ptr)
  202. : "r" (aacirun->fifo)
  203. : "r0", "r1", "r2", "r3", "cc");
  204. if (ptr >= aacirun->end)
  205. ptr = aacirun->start;
  206. }
  207. } while(1);
  208. aacirun->ptr = ptr;
  209. }
  210. if (mask & ISR_URINTR) {
  211. dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
  212. writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
  213. }
  214. if (mask & ISR_TXINTR) {
  215. struct aaci_runtime *aacirun = &aaci->playback;
  216. void *ptr;
  217. if (!aacirun->substream || !aacirun->start) {
  218. dev_warn(&aaci->dev->dev, "TX interrupt???\n");
  219. writel(0, aacirun->base + AACI_IE);
  220. return;
  221. }
  222. ptr = aacirun->ptr;
  223. do {
  224. unsigned int len = aacirun->fifosz;
  225. u32 val;
  226. if (aacirun->bytes <= 0) {
  227. aacirun->bytes += aacirun->period;
  228. aacirun->ptr = ptr;
  229. spin_unlock(&aaci->lock);
  230. snd_pcm_period_elapsed(aacirun->substream);
  231. spin_lock(&aaci->lock);
  232. }
  233. if (!(aacirun->cr & CR_EN))
  234. break;
  235. val = readl(aacirun->base + AACI_SR);
  236. if (!(val & SR_TXHE))
  237. break;
  238. if (!(val & SR_TXFE))
  239. len >>= 1;
  240. aacirun->bytes -= len;
  241. /* writing 16 bytes at a time */
  242. for ( ; len > 0; len -= 16) {
  243. asm(
  244. "ldmia %0!, {r0, r1, r2, r3}\n\t"
  245. "stmia %1, {r0, r1, r2, r3}"
  246. : "+r" (ptr)
  247. : "r" (aacirun->fifo)
  248. : "r0", "r1", "r2", "r3", "cc");
  249. if (ptr >= aacirun->end)
  250. ptr = aacirun->start;
  251. }
  252. } while (1);
  253. aacirun->ptr = ptr;
  254. }
  255. }
  256. static irqreturn_t aaci_irq(int irq, void *devid)
  257. {
  258. struct aaci *aaci = devid;
  259. u32 mask;
  260. int i;
  261. spin_lock(&aaci->lock);
  262. mask = readl(aaci->base + AACI_ALLINTS);
  263. if (mask) {
  264. u32 m = mask;
  265. for (i = 0; i < 4; i++, m >>= 7) {
  266. if (m & 0x7f) {
  267. aaci_fifo_irq(aaci, i, m);
  268. }
  269. }
  270. }
  271. spin_unlock(&aaci->lock);
  272. return mask ? IRQ_HANDLED : IRQ_NONE;
  273. }
  274. /*
  275. * ALSA support.
  276. */
  277. struct aaci_stream {
  278. unsigned char codec_idx;
  279. unsigned char rate_idx;
  280. };
  281. static struct aaci_stream aaci_streams[] = {
  282. [ACSTREAM_FRONT] = {
  283. .codec_idx = 0,
  284. .rate_idx = AC97_RATES_FRONT_DAC,
  285. },
  286. [ACSTREAM_SURROUND] = {
  287. .codec_idx = 0,
  288. .rate_idx = AC97_RATES_SURR_DAC,
  289. },
  290. [ACSTREAM_LFE] = {
  291. .codec_idx = 0,
  292. .rate_idx = AC97_RATES_LFE_DAC,
  293. },
  294. };
  295. static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
  296. {
  297. struct aaci_stream *s = aaci_streams + streamid;
  298. return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
  299. }
  300. static unsigned int rate_list[] = {
  301. 5512, 8000, 11025, 16000, 22050, 32000, 44100,
  302. 48000, 64000, 88200, 96000, 176400, 192000
  303. };
  304. /*
  305. * Double-rate rule: we can support double rate iff channels == 2
  306. * (unimplemented)
  307. */
  308. static int
  309. aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  310. {
  311. struct aaci *aaci = rule->private;
  312. unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
  313. struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
  314. switch (c->max) {
  315. case 6:
  316. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
  317. case 4:
  318. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
  319. case 2:
  320. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
  321. }
  322. return snd_interval_list(hw_param_interval(p, rule->var),
  323. ARRAY_SIZE(rate_list), rate_list,
  324. rate_mask);
  325. }
  326. static struct snd_pcm_hardware aaci_hw_info = {
  327. .info = SNDRV_PCM_INFO_MMAP |
  328. SNDRV_PCM_INFO_MMAP_VALID |
  329. SNDRV_PCM_INFO_INTERLEAVED |
  330. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  331. SNDRV_PCM_INFO_RESUME,
  332. /*
  333. * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
  334. * words. It also doesn't support 12-bit at all.
  335. */
  336. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  337. /* should this be continuous or knot? */
  338. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  339. .rate_max = 48000,
  340. .rate_min = 4000,
  341. .channels_min = 2,
  342. .channels_max = 6,
  343. .buffer_bytes_max = 64 * 1024,
  344. .period_bytes_min = 256,
  345. .period_bytes_max = PAGE_SIZE,
  346. .periods_min = 4,
  347. .periods_max = PAGE_SIZE / 16,
  348. };
  349. static int __aaci_pcm_open(struct aaci *aaci,
  350. struct snd_pcm_substream *substream,
  351. struct aaci_runtime *aacirun)
  352. {
  353. struct snd_pcm_runtime *runtime = substream->runtime;
  354. int ret;
  355. aacirun->substream = substream;
  356. runtime->private_data = aacirun;
  357. runtime->hw = aaci_hw_info;
  358. /*
  359. * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
  360. * mode, each 32-bit word contains one sample. If we're in
  361. * compact mode, each 32-bit word contains two samples, effectively
  362. * halving the FIFO size. However, we don't know for sure which
  363. * we'll be using at this point. We set this to the lower limit.
  364. */
  365. runtime->hw.fifo_size = aaci->fifosize * 2;
  366. /*
  367. * Add rule describing hardware rate dependency
  368. * on the number of channels.
  369. */
  370. ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  371. aaci_rule_rate_by_channels, aaci,
  372. SNDRV_PCM_HW_PARAM_CHANNELS,
  373. SNDRV_PCM_HW_PARAM_RATE, -1);
  374. if (ret)
  375. goto out;
  376. ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
  377. DRIVER_NAME, aaci);
  378. if (ret)
  379. goto out;
  380. return 0;
  381. out:
  382. return ret;
  383. }
  384. /*
  385. * Common ALSA stuff
  386. */
  387. static int aaci_pcm_close(struct snd_pcm_substream *substream)
  388. {
  389. struct aaci *aaci = substream->private_data;
  390. struct aaci_runtime *aacirun = substream->runtime->private_data;
  391. WARN_ON(aacirun->cr & CR_EN);
  392. aacirun->substream = NULL;
  393. free_irq(aaci->dev->irq[0], aaci);
  394. return 0;
  395. }
  396. static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
  397. {
  398. struct aaci_runtime *aacirun = substream->runtime->private_data;
  399. /*
  400. * This must not be called with the device enabled.
  401. */
  402. WARN_ON(aacirun->cr & CR_EN);
  403. if (aacirun->pcm_open)
  404. snd_ac97_pcm_close(aacirun->pcm);
  405. aacirun->pcm_open = 0;
  406. /*
  407. * Clear out the DMA and any allocated buffers.
  408. */
  409. snd_pcm_lib_free_pages(substream);
  410. return 0;
  411. }
  412. static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
  413. struct aaci_runtime *aacirun,
  414. struct snd_pcm_hw_params *params)
  415. {
  416. int err;
  417. aaci_pcm_hw_free(substream);
  418. if (aacirun->pcm_open) {
  419. snd_ac97_pcm_close(aacirun->pcm);
  420. aacirun->pcm_open = 0;
  421. }
  422. err = snd_pcm_lib_malloc_pages(substream,
  423. params_buffer_bytes(params));
  424. if (err < 0)
  425. goto out;
  426. err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
  427. params_channels(params),
  428. aacirun->pcm->r[0].slots);
  429. if (err)
  430. goto out;
  431. aacirun->pcm_open = 1;
  432. out:
  433. return err;
  434. }
  435. static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
  436. {
  437. struct snd_pcm_runtime *runtime = substream->runtime;
  438. struct aaci_runtime *aacirun = runtime->private_data;
  439. aacirun->start = (void *)runtime->dma_area;
  440. aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream);
  441. aacirun->ptr = aacirun->start;
  442. aacirun->period =
  443. aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
  444. return 0;
  445. }
  446. static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
  447. {
  448. struct snd_pcm_runtime *runtime = substream->runtime;
  449. struct aaci_runtime *aacirun = runtime->private_data;
  450. ssize_t bytes = aacirun->ptr - aacirun->start;
  451. return bytes_to_frames(runtime, bytes);
  452. }
  453. /*
  454. * Playback specific ALSA stuff
  455. */
  456. static const u32 channels_to_txmask[] = {
  457. [2] = CR_SL3 | CR_SL4,
  458. [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
  459. [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
  460. };
  461. /*
  462. * We can support two and four channel audio. Unfortunately
  463. * six channel audio requires a non-standard channel ordering:
  464. * 2 -> FL(3), FR(4)
  465. * 4 -> FL(3), FR(4), SL(7), SR(8)
  466. * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
  467. * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
  468. * This requires an ALSA configuration file to correct.
  469. */
  470. static unsigned int channel_list[] = { 2, 4, 6 };
  471. static int
  472. aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  473. {
  474. struct aaci *aaci = rule->private;
  475. unsigned int chan_mask = 1 << 0, slots;
  476. /*
  477. * pcms[0] is the our 5.1 PCM instance.
  478. */
  479. slots = aaci->ac97_bus->pcms[0].r[0].slots;
  480. if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  481. chan_mask |= 1 << 1;
  482. if (slots & (1 << AC97_SLOT_LFE))
  483. chan_mask |= 1 << 2;
  484. }
  485. return snd_interval_list(hw_param_interval(p, rule->var),
  486. ARRAY_SIZE(channel_list), channel_list,
  487. chan_mask);
  488. }
  489. static int aaci_pcm_open(struct snd_pcm_substream *substream)
  490. {
  491. struct aaci *aaci = substream->private_data;
  492. int ret;
  493. /*
  494. * Add rule describing channel dependency.
  495. */
  496. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  497. SNDRV_PCM_HW_PARAM_CHANNELS,
  498. aaci_rule_channels, aaci,
  499. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  500. if (ret)
  501. return ret;
  502. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  503. ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
  504. } else {
  505. ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
  506. }
  507. return ret;
  508. }
  509. static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
  510. struct snd_pcm_hw_params *params)
  511. {
  512. struct aaci *aaci = substream->private_data;
  513. struct aaci_runtime *aacirun = substream->runtime->private_data;
  514. unsigned int channels = params_channels(params);
  515. int ret;
  516. WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
  517. !channels_to_txmask[channels]);
  518. ret = aaci_pcm_hw_params(substream, aacirun, params);
  519. /*
  520. * Enable FIFO, compact mode, 16 bits per sample.
  521. * FIXME: double rate slots?
  522. */
  523. if (ret >= 0) {
  524. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  525. aacirun->cr |= channels_to_txmask[channels];
  526. aacirun->fifosz = aaci->fifosize * 4;
  527. if (aacirun->cr & CR_COMPACT)
  528. aacirun->fifosz >>= 1;
  529. }
  530. return ret;
  531. }
  532. static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
  533. {
  534. u32 ie;
  535. ie = readl(aacirun->base + AACI_IE);
  536. ie &= ~(IE_URIE|IE_TXIE);
  537. writel(ie, aacirun->base + AACI_IE);
  538. aacirun->cr &= ~CR_EN;
  539. aaci_chan_wait_ready(aacirun);
  540. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  541. }
  542. static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
  543. {
  544. u32 ie;
  545. aaci_chan_wait_ready(aacirun);
  546. aacirun->cr |= CR_EN;
  547. ie = readl(aacirun->base + AACI_IE);
  548. ie |= IE_URIE | IE_TXIE;
  549. writel(ie, aacirun->base + AACI_IE);
  550. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  551. }
  552. static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  553. {
  554. struct aaci *aaci = substream->private_data;
  555. struct aaci_runtime *aacirun = substream->runtime->private_data;
  556. unsigned long flags;
  557. int ret = 0;
  558. spin_lock_irqsave(&aaci->lock, flags);
  559. switch (cmd) {
  560. case SNDRV_PCM_TRIGGER_START:
  561. aaci_pcm_playback_start(aacirun);
  562. break;
  563. case SNDRV_PCM_TRIGGER_RESUME:
  564. aaci_pcm_playback_start(aacirun);
  565. break;
  566. case SNDRV_PCM_TRIGGER_STOP:
  567. aaci_pcm_playback_stop(aacirun);
  568. break;
  569. case SNDRV_PCM_TRIGGER_SUSPEND:
  570. aaci_pcm_playback_stop(aacirun);
  571. break;
  572. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  573. break;
  574. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  575. break;
  576. default:
  577. ret = -EINVAL;
  578. }
  579. spin_unlock_irqrestore(&aaci->lock, flags);
  580. return ret;
  581. }
  582. static struct snd_pcm_ops aaci_playback_ops = {
  583. .open = aaci_pcm_open,
  584. .close = aaci_pcm_close,
  585. .ioctl = snd_pcm_lib_ioctl,
  586. .hw_params = aaci_pcm_playback_hw_params,
  587. .hw_free = aaci_pcm_hw_free,
  588. .prepare = aaci_pcm_prepare,
  589. .trigger = aaci_pcm_playback_trigger,
  590. .pointer = aaci_pcm_pointer,
  591. };
  592. static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
  593. struct snd_pcm_hw_params *params)
  594. {
  595. struct aaci *aaci = substream->private_data;
  596. struct aaci_runtime *aacirun = substream->runtime->private_data;
  597. int ret;
  598. ret = aaci_pcm_hw_params(substream, aacirun, params);
  599. if (ret >= 0) {
  600. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  601. /* Line in record: slot 3 and 4 */
  602. aacirun->cr |= CR_SL3 | CR_SL4;
  603. aacirun->fifosz = aaci->fifosize * 4;
  604. if (aacirun->cr & CR_COMPACT)
  605. aacirun->fifosz >>= 1;
  606. }
  607. return ret;
  608. }
  609. static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
  610. {
  611. u32 ie;
  612. aaci_chan_wait_ready(aacirun);
  613. ie = readl(aacirun->base + AACI_IE);
  614. ie &= ~(IE_ORIE | IE_RXIE);
  615. writel(ie, aacirun->base+AACI_IE);
  616. aacirun->cr &= ~CR_EN;
  617. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  618. }
  619. static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
  620. {
  621. u32 ie;
  622. aaci_chan_wait_ready(aacirun);
  623. #ifdef DEBUG
  624. /* RX Timeout value: bits 28:17 in RXCR */
  625. aacirun->cr |= 0xf << 17;
  626. #endif
  627. aacirun->cr |= CR_EN;
  628. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  629. ie = readl(aacirun->base + AACI_IE);
  630. ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
  631. writel(ie, aacirun->base + AACI_IE);
  632. }
  633. static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  634. {
  635. struct aaci *aaci = substream->private_data;
  636. struct aaci_runtime *aacirun = substream->runtime->private_data;
  637. unsigned long flags;
  638. int ret = 0;
  639. spin_lock_irqsave(&aaci->lock, flags);
  640. switch (cmd) {
  641. case SNDRV_PCM_TRIGGER_START:
  642. aaci_pcm_capture_start(aacirun);
  643. break;
  644. case SNDRV_PCM_TRIGGER_RESUME:
  645. aaci_pcm_capture_start(aacirun);
  646. break;
  647. case SNDRV_PCM_TRIGGER_STOP:
  648. aaci_pcm_capture_stop(aacirun);
  649. break;
  650. case SNDRV_PCM_TRIGGER_SUSPEND:
  651. aaci_pcm_capture_stop(aacirun);
  652. break;
  653. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  654. break;
  655. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  656. break;
  657. default:
  658. ret = -EINVAL;
  659. }
  660. spin_unlock_irqrestore(&aaci->lock, flags);
  661. return ret;
  662. }
  663. static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
  664. {
  665. struct snd_pcm_runtime *runtime = substream->runtime;
  666. struct aaci *aaci = substream->private_data;
  667. aaci_pcm_prepare(substream);
  668. /* allow changing of sample rate */
  669. aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
  670. aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  671. aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
  672. /* Record select: Mic: 0, Aux: 3, Line: 4 */
  673. aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
  674. return 0;
  675. }
  676. static struct snd_pcm_ops aaci_capture_ops = {
  677. .open = aaci_pcm_open,
  678. .close = aaci_pcm_close,
  679. .ioctl = snd_pcm_lib_ioctl,
  680. .hw_params = aaci_pcm_capture_hw_params,
  681. .hw_free = aaci_pcm_hw_free,
  682. .prepare = aaci_pcm_capture_prepare,
  683. .trigger = aaci_pcm_capture_trigger,
  684. .pointer = aaci_pcm_pointer,
  685. };
  686. /*
  687. * Power Management.
  688. */
  689. #ifdef CONFIG_PM
  690. static int aaci_do_suspend(struct snd_card *card, unsigned int state)
  691. {
  692. struct aaci *aaci = card->private_data;
  693. snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
  694. snd_pcm_suspend_all(aaci->pcm);
  695. return 0;
  696. }
  697. static int aaci_do_resume(struct snd_card *card, unsigned int state)
  698. {
  699. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  700. return 0;
  701. }
  702. static int aaci_suspend(struct amba_device *dev, pm_message_t state)
  703. {
  704. struct snd_card *card = amba_get_drvdata(dev);
  705. return card ? aaci_do_suspend(card) : 0;
  706. }
  707. static int aaci_resume(struct amba_device *dev)
  708. {
  709. struct snd_card *card = amba_get_drvdata(dev);
  710. return card ? aaci_do_resume(card) : 0;
  711. }
  712. #else
  713. #define aaci_do_suspend NULL
  714. #define aaci_do_resume NULL
  715. #define aaci_suspend NULL
  716. #define aaci_resume NULL
  717. #endif
  718. static struct ac97_pcm ac97_defs[] __devinitdata = {
  719. [0] = { /* Front PCM */
  720. .exclusive = 1,
  721. .r = {
  722. [0] = {
  723. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  724. (1 << AC97_SLOT_PCM_RIGHT) |
  725. (1 << AC97_SLOT_PCM_CENTER) |
  726. (1 << AC97_SLOT_PCM_SLEFT) |
  727. (1 << AC97_SLOT_PCM_SRIGHT) |
  728. (1 << AC97_SLOT_LFE),
  729. },
  730. },
  731. },
  732. [1] = { /* PCM in */
  733. .stream = 1,
  734. .exclusive = 1,
  735. .r = {
  736. [0] = {
  737. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  738. (1 << AC97_SLOT_PCM_RIGHT),
  739. },
  740. },
  741. },
  742. [2] = { /* Mic in */
  743. .stream = 1,
  744. .exclusive = 1,
  745. .r = {
  746. [0] = {
  747. .slots = (1 << AC97_SLOT_MIC),
  748. },
  749. },
  750. }
  751. };
  752. static struct snd_ac97_bus_ops aaci_bus_ops = {
  753. .write = aaci_ac97_write,
  754. .read = aaci_ac97_read,
  755. };
  756. static int __devinit aaci_probe_ac97(struct aaci *aaci)
  757. {
  758. struct snd_ac97_template ac97_template;
  759. struct snd_ac97_bus *ac97_bus;
  760. struct snd_ac97 *ac97;
  761. int ret;
  762. writel(0, aaci->base + AC97_POWERDOWN);
  763. /*
  764. * Assert AACIRESET for 2us
  765. */
  766. writel(0, aaci->base + AACI_RESET);
  767. udelay(2);
  768. writel(RESET_NRST, aaci->base + AACI_RESET);
  769. /*
  770. * Give the AC'97 codec more than enough time
  771. * to wake up. (42us = ~2 frames at 48kHz.)
  772. */
  773. udelay(42);
  774. ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
  775. if (ret)
  776. goto out;
  777. ac97_bus->clock = 48000;
  778. aaci->ac97_bus = ac97_bus;
  779. memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
  780. ac97_template.private_data = aaci;
  781. ac97_template.num = 0;
  782. ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
  783. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
  784. if (ret)
  785. goto out;
  786. aaci->ac97 = ac97;
  787. /*
  788. * Disable AC97 PC Beep input on audio codecs.
  789. */
  790. if (ac97_is_audio(ac97))
  791. snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
  792. ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
  793. if (ret)
  794. goto out;
  795. aaci->playback.pcm = &ac97_bus->pcms[0];
  796. aaci->capture.pcm = &ac97_bus->pcms[1];
  797. out:
  798. return ret;
  799. }
  800. static void aaci_free_card(struct snd_card *card)
  801. {
  802. struct aaci *aaci = card->private_data;
  803. if (aaci->base)
  804. iounmap(aaci->base);
  805. }
  806. static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
  807. {
  808. struct aaci *aaci;
  809. struct snd_card *card;
  810. int err;
  811. err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  812. THIS_MODULE, sizeof(struct aaci), &card);
  813. if (err < 0)
  814. return NULL;
  815. card->private_free = aaci_free_card;
  816. strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
  817. strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
  818. snprintf(card->longname, sizeof(card->longname),
  819. "%s at 0x%016llx, irq %d",
  820. card->shortname, (unsigned long long)dev->res.start,
  821. dev->irq[0]);
  822. aaci = card->private_data;
  823. mutex_init(&aaci->ac97_sem);
  824. spin_lock_init(&aaci->lock);
  825. aaci->card = card;
  826. aaci->dev = dev;
  827. /* Set MAINCR to allow slot 1 and 2 data IO */
  828. aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
  829. MAINCR_SL2RXEN | MAINCR_SL2TXEN;
  830. return aaci;
  831. }
  832. static int __devinit aaci_init_pcm(struct aaci *aaci)
  833. {
  834. struct snd_pcm *pcm;
  835. int ret;
  836. ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
  837. if (ret == 0) {
  838. aaci->pcm = pcm;
  839. pcm->private_data = aaci;
  840. pcm->info_flags = 0;
  841. strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
  842. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
  843. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
  844. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  845. NULL, 0, 64 * 104);
  846. }
  847. return ret;
  848. }
  849. static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
  850. {
  851. struct aaci_runtime *aacirun = &aaci->playback;
  852. int i;
  853. writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
  854. for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
  855. writel(0, aacirun->fifo);
  856. writel(0, aacirun->base + AACI_TXCR);
  857. /*
  858. * Re-initialise the AACI after the FIFO depth test, to
  859. * ensure that the FIFOs are empty. Unfortunately, merely
  860. * disabling the channel doesn't clear the FIFO.
  861. */
  862. writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
  863. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  864. /*
  865. * If we hit 4096, we failed. Go back to the specified
  866. * fifo depth.
  867. */
  868. if (i == 4096)
  869. i = 8;
  870. return i;
  871. }
  872. static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id)
  873. {
  874. struct aaci *aaci;
  875. int ret, i;
  876. ret = amba_request_regions(dev, NULL);
  877. if (ret)
  878. return ret;
  879. aaci = aaci_init_card(dev);
  880. if (!aaci) {
  881. ret = -ENOMEM;
  882. goto out;
  883. }
  884. aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
  885. if (!aaci->base) {
  886. ret = -ENOMEM;
  887. goto out;
  888. }
  889. /*
  890. * Playback uses AACI channel 0
  891. */
  892. aaci->playback.base = aaci->base + AACI_CSCH1;
  893. aaci->playback.fifo = aaci->base + AACI_DR1;
  894. /*
  895. * Capture uses AACI channel 0
  896. */
  897. aaci->capture.base = aaci->base + AACI_CSCH1;
  898. aaci->capture.fifo = aaci->base + AACI_DR1;
  899. for (i = 0; i < 4; i++) {
  900. void __iomem *base = aaci->base + i * 0x14;
  901. writel(0, base + AACI_IE);
  902. writel(0, base + AACI_TXCR);
  903. writel(0, base + AACI_RXCR);
  904. }
  905. writel(0x1fff, aaci->base + AACI_INTCLR);
  906. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  907. ret = aaci_probe_ac97(aaci);
  908. if (ret)
  909. goto out;
  910. /*
  911. * Size the FIFOs (must be multiple of 16).
  912. */
  913. aaci->fifosize = aaci_size_fifo(aaci);
  914. if (aaci->fifosize & 15) {
  915. printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
  916. aaci->fifosize);
  917. ret = -ENODEV;
  918. goto out;
  919. }
  920. ret = aaci_init_pcm(aaci);
  921. if (ret)
  922. goto out;
  923. snd_card_set_dev(aaci->card, &dev->dev);
  924. ret = snd_card_register(aaci->card);
  925. if (ret == 0) {
  926. dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
  927. aaci->fifosize);
  928. amba_set_drvdata(dev, aaci->card);
  929. return ret;
  930. }
  931. out:
  932. if (aaci)
  933. snd_card_free(aaci->card);
  934. amba_release_regions(dev);
  935. return ret;
  936. }
  937. static int __devexit aaci_remove(struct amba_device *dev)
  938. {
  939. struct snd_card *card = amba_get_drvdata(dev);
  940. amba_set_drvdata(dev, NULL);
  941. if (card) {
  942. struct aaci *aaci = card->private_data;
  943. writel(0, aaci->base + AACI_MAINCR);
  944. snd_card_free(card);
  945. amba_release_regions(dev);
  946. }
  947. return 0;
  948. }
  949. static struct amba_id aaci_ids[] = {
  950. {
  951. .id = 0x00041041,
  952. .mask = 0x000fffff,
  953. },
  954. { 0, 0 },
  955. };
  956. static struct amba_driver aaci_driver = {
  957. .drv = {
  958. .name = DRIVER_NAME,
  959. },
  960. .probe = aaci_probe,
  961. .remove = __devexit_p(aaci_remove),
  962. .suspend = aaci_suspend,
  963. .resume = aaci_resume,
  964. .id_table = aaci_ids,
  965. };
  966. static int __init aaci_init(void)
  967. {
  968. return amba_driver_register(&aaci_driver);
  969. }
  970. static void __exit aaci_exit(void)
  971. {
  972. amba_driver_unregister(&aaci_driver);
  973. }
  974. module_init(aaci_init);
  975. module_exit(aaci_exit);
  976. MODULE_LICENSE("GPL");
  977. MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");